Reducing ATE Cost in System-on-Chip Test

Transcription

1 Reducing ATE Cost in System-on-Chip Test Ilia Polian Bernd Becker Institute of Computer Science Albert-Ludigs-University Georges-Köhler-Allee Freiburg im Breisgau, Germany < polian, becker Abstract Traditional SoC test scheduling approaches minimize test time under additional constraints. We argue that test costs are not determined by test time alone. Indeed, the speed of used ATE channels influences both cost and test time. We present a case for using a mixture of high-speed and lo-cost ATE channels. To heuristics and an exact algorithm are proposed. Experimental results sho that such a mixture scenario can reduce the cost ith no impact on test time. Keyords: System-on-Chip test, Automatic test equipment, test economics 1 Introduction A System-on-Chip (SoC) is an integrated circuit hich consists of multiple cores on one single die. This paradigm is gaining popularity since several designers (and even different companies) can contribute to the same IC independently, yielding benefits in time-to-market. A core replaces a stand-alone chip, and an SoC implements the functionality for hich previously a board ith multiple chips has been required. The miniaturization of IC structures and the ability to manufacture in different technologies on the same die make the SoC concept possible. This design approach has led to a shift in test generation and test application. Traditionally, test patterns have been generated for the hole IC. In contrast, patterns for each individual core of an SoC are available, and it is highly desirable to re-use them instead of generating a ne, global test. One reason for this is that the test generation for such a big circuit might just be too complex. Moreover, some of the cores may have been designed by a different company and thus the information needed for test generation may be lacking. Conclusively, a test for each core of an SoC is to some extent independent from the test for other cores. For instance, it is possible that the tests are generated for different fault models. For application of the tests, each core is equipped ith a test access mechanism (TAM) and a core test rapper [1]. There exists a number of test architectures based on different types of TAMs. Cores can be either tested in parallel (concurrently) or one after another (sequentially). Hoever, there are some scarce resources hich the cores must share during the testing. One such resource is the available poer. If the poer supply is not sufficient to provide all cores simultaneously ith energy needed for testing, then they cannot be tested concurrently. Another constraint is the number of available IC pins. This number has not experienced the same spectacular exponential groth as the density of IC structures. With the number of available IC pins being comparable to the number of I/O ports of each individual core, there is no ay to connect each port of each core ith a pin simultaneously. Thus, one IC pin must serve multiple ports by some mean of serial access (e. g. using a solution like boundary scan). Obviously, there is negative impact on test application time. Figuring out ho to test an SoC in minimal time ithout violating the constraints is knon as the SoC test scheduling problem. There is substantial research on solving this problem [2, 3, 4, 5, 6, 7]. It is important to note that hile the basic problem is the same, the exact specification differs among the papers. The discriminating features include the exact architecture used (the kind of access to the cores) and the considered constraints (pin number, peak or average poer, place-and-route). Almost every paper on test scheduling minimizes test application time. This implies that the test costs are considered proportional to the test time. One exception is [8], in hich maximal test time is a constraint and the number of required pins is minimized. The present ork suggests a more differentiated vie to the definition of the test costs. With test time surely being one component, another part of these costs is the kind of automatic test equipment (ATE) involved in testing. A high-speed ATE channel is knon to be tremendously more expensive than a usual ATE channel. On the other hand, there is no reason preventing the usage of high-speed channels for testing one core and lo-speed channels for testing another core. We study the effect of such a mixture. Interestingly, e find that often lo-speed channels can be used ithout any negative impact on test time. The remainder of this paper is organized as follos. In the next section, e present the algorithm used for assigning ATE channels. Experimental results are given in Section 4. Possible directions for the future ork are discussed in Section 5. Section 6 concludes the paper.

2 control Core 1 out Core Core 3 in in control 0 1 Core Core 2 Core 3 out in 1 1 Core Core Core = out Figure 1: Architectures for SoC test: Multiplexing, Daisychain, Distribution 2 Channel Assignment In [9], three basic scan architectures are proposed: Multiplexing, Daisychain and Distribution architecture (Figure 1). In the Multiplexing architecture, each core is connected to the full idth of the TAM and only one core can be tested at a time. Daisychain architecture features cores connected in a ro (the outputs of a core are connected to the inputs of the next core), ith the option that a core can be bypassed. Finally, in the Distribution architecture, the bit-idth of the TAM is divided among cores and one or more bits of the TAM are uniquely assigned to a core. The Test Bus architecture [10] is a combination of the Multiplexing and the Distribution architectures; the TestRail architecture [11] is a combination of the Daisychain and the Distribution architectures. It is not a target of this ork to discuss the superiority of one architecture over another. Indeed, e concentrate on the impact of the ATE channel speed on the test time. For the sake of simplicity, e consider the Distribution architecture only. We assume that each core has (if at all) only scan memory elements and that its primary I/O ports are connected to a boundary scan. Furthermore, e assume that primary I/Os and memory elements (secondary I/Os) can be mixed in the same chain, so e indeed treat primary and secondary I/Os in the same ay. Letacorei have d i primary inputs, o i primary outputs, f i flip-flops and V i scan test vectors. Then, there are d i +f i bits to be shifted in and o i +f i bits to be shifted out. Let the IC have P pins, and let to kinds of ATE channels be available: fast and slo channels. A fast channel can be used for shifting in and out at device s nominal frequency, hereas a slo channel is assumed to allo shifting operation ith 1/lth of the frequency 1. 1 Thus, l = 2 means that slo channels are half as fast as fast channels. Note that in a realistic setting the scan frequency may be considerably belo the device s nominal frequency. In this case, and for, e ould have to replace nominal frequency and half nominal frequency by, maybe, 1/4th and 1/8th of the nominal frequency, respectively. Since shifting a test vector out can be done simultaneously ith shifting the next vector in (except the very last vector), the overall test time consumed hen one scan chain is available and fast pins are employed is t f i (1) = SI i (V i + 1), ith SI i = f i + max{d i,o i } being the shift time. If k chains (and thus k pins and channels) can be used, the test application time becomes t f i (k) = SI i/k (V i + 1). The test application time using slo channels is t s i (k) =l SI i/k (V i +1). In order to assign pins to cores, e use the algorithm allocate pins [9]. Procedure allocate pins Input: Number n of cores Input: Number P of available pins; P n Input: For each core i: number d i of inputs. Output: k 1,...,k n (1) for all i, 1 i n, setk i := 1; (2) for all i, 1 i n, compute t s i (1); (3) P := P n; (4) hile (P >0) (5) Choose core i ith maximal test time t max = t s i (k i ); (6) k i := k i +1; (7) Recompute t s i (k i ) (8) P := P 1; (9) end hile (10) return k 1,...,k n ; At first (Steps (1) (3)), each core gets one allocated pin. The rest of the pins is distributed in order to loer the test time requirements of the most critical core i. Note that the core i leading to the maximal test time (hich is chosen in Step (5)) does not have to be unique, since there may be multiple cores having the same test time. The procedure finishes (the hile loop in Step (4) is not re-entered), if no pins are left to allocate. If the priority queue is implemented using a heap, the run time of the algorithm ill be O(P log P ). No e assume that each core is connected to slo channels. Let F fast channels be available for testing. Given F, e connect as many cores as possible to fast channels instead of slo channels and evaluate the

3 saving in the test time. We do not allo a mixture of fast and slo channels for one core. The procedure assign fast channels is designed for this purpose: Procedure assign fast channels Input: Number n of cores Input: Number P of available pins; P n Input: Number F of avail. fast channels; 0 F P Input: For each core i: all k i pins assigned to it. Output: For each pin p, 1 p P, either channel(p) = Fast or channel(p) = Slo (1) for all p, 1 p P, set channel(p) := Slo ; (2) for all i, 1 i n, compute t s i (1); (3) hile (true) (4) Choose core i ith maximal test time t max = t s i (k i ); (5) If (fast channels already assigned to core i s pins) (6) break; (7) If (F <k i ) (8) break; (9) for each pin p assigned to the core i (10) channel(p) := Fast ; (11) Recompute test time as t f i (k i ) (12) F := F k i ; (13) end hile (14) return channel(1),..., channel(n); In order to minimize the test time, the core i ith maximal test time is selected and it is checked hether there are enough fast ATE channels to connect ith its k i pins (Step (7)). If no, the calculation is terminated; if yes, k i is subtracted from F, and the procedure is re-iterated. Note that if F<k i but there is some other core j ith F k j,itdoes not make sense to use the available fast pins for the core j because the overall test time is still determined by the core i. Note also that if fast channels are already assigned to the bottleneck core i, the process is terminated as assigning fast channels to other cores ould not loer the overall test time still determined by i (Step (5)). 3 Optimality Of the Algorithm The algorithm allocate pins is proven to be optimal if the ATE channels do not differ (for a detailed proof, see [12]). Furthermore, it is trivial that, if the channel assignment is fixed, it is optimal to distribute fast channels in the greedy fashion, as done in Procedure allocate fast channels (allocating fast channels to other cores ould not loer the overall test time). Hoever, although both parts of the algorithm are optimal for themselves, running Procedure allocate pins and then Procedure allocate fast channels does not alays lead to a global optimum. For a counterexample, consider an SoC consisting of to cores, having 12 and 2 inputs, respectively. For simplicity, e assume that there are no flip flops and e take the scan time (l d i /k if the core i is connected to slo channels or d i /k if it is connected to fast channels) as the surrogate for the test time (if all test sets are of equal size, the test time is proportional to the scan time). Let 4 pins be available, and let 2 available channels be fast. Assume l =2. The algorithm allocate pins ould distribute 3 channels to Core 1 and 1 channel to Core 2. The scan time for Core 1 is l 12/3 =2 4 = 8; for Core 2 the scan time is 2 2/1 = 4. No, fast channels are distributed by Procedure allocate fast channels. Unfortunately, there are not enough fast channels to serve Core 1 (2 are available hile 3 are needed), and allocating fast channels to Core 2 ould not reduce the overall test time. Thus, Procedure allocate pins in conjunction ith Procedure allocate fast channels run afterards has lead to test time of 8. Hoever, allocating to channels, both of them fast, to Core 1, and the to remaining channels to Core 2 ould result in test time 12/2 = 6 for Core 1 (note the missing multiplication by l = 2 as the channels are no fast) and 2 2/2 = 2 for Core 2 and test time of 6. Note that if only 3 instead of 4 pins (and still 2 fast channels) ould be available, the algorithm ould have lead to the optimal solution (test time 6). Paradoxically, increasing available resources in this case actually leads to deterioration of results. One may be tempted to assume that the optimality is given if the test time is computed also for all smaller numbers of available pins P and the minimal test time is taken (after all, if not using some pins actually helps, there is no obligation to employ them; see [8] for arguments hy as fe of possible pins should be used for testing even if they are available). To differentiate this approach, e from no on refer to our current method (i. e. running Procedure allocate pins and Procedure allocate fast channels afterards) as Heuristic 1. In order to incorporate the mentioned change into the algorithm, e modify it as follos: e no distribute the fast channels (hich is done by calling Procedure allocate fast channels) in each iteration of Procedure assign pins, right after the line (8). We compute the test time and remember its minimal value. If in the test time computed in the last iteration of the algorithm exceeds this minimal value, the minimal value is reported instead. Unfortunately, it is also possible to give a counterexample for hich the algorithm modified in the ay indicated does not find the optimal solution: let there be three cores, ith 24, 10 and 4 inputs respectively. Let 4 pins and 2 fast channels be available and let l be 10. In the first iteration, the algorithm allocate pins ould allocate 1 pin to each core, leading to test times of 240, 100 and 40, respectively (if slo channels are used). No, an attempt is done to distribute 2 fast channels. Obviously, they are assigned to Cores 1 and 2, loering their test time to 24 and 10, so the overall test time is 40 as determined by Core 3. The fast

4 channel assignments are rolled back and the next iteration of the algorithm is run, resulting in one more pin assigned to Core 1. The test time assuming slo channels ould no become 120, 100 and 40. Both fast channels ould be assigned to Core 1, loering its test time to 12. Hoever, there are no more fast channels to assign to Core 2, so its test time of 100 determines the overall test time. Since e have stored the test time 40 in the first iteration, the algorithm reports 40 as the optimum. Hoever, allocating one fast channel to both Core 1 and Core 2 and to slo channels to Core 3 results in test times 24, 10 and 20 and thus a minimal solution hich the modified algorithm has not found despite the additional effort. We ant to refer to the modified algorithm as Heuristic 2. For comparison purposes e also have implemented an exact algorithm based on exhaustive enumeration. It considers each possible pin assignment (but not every assignment of fast channels). For instance, for an SoC consisting of three cores and 5 available pins folloing six assignments are considered: (1, 1, 3); (1, 2, 2); (1, 3, 1); (2, 1, 2); (2, 2, 1); (3, 1, 1). For each assignment, fast channels are distributed by Procedure allocate fast channels. Since the greedy allocation of fast channels leads to the optimal test time if the pin assignment is fixed, considering all pin assignments yields the global optimum. 4 Experimental Results Circuit PI PO FF Test size s s838, s s s s s s s s Table 1: Circuit data We report the results for three hypothetical SOCs, here the first SOC consists of 10 ISCAS-89 [13] benchmark circuits. In Table 1, the names of used circuits accompanied by the number of primary inputs, primary outputs and flip flops, are given. In the last column of Table 1, the number of vectors in the test set is shon. This number is a best of selection from [14, 15, 16]. The second SOC consists of the four biggest circuits of the ten circuits from Table 1, given in its four last ros. The third SoC contains five instances of s420.1 and five instances of s (it is meant to demonstrate the behavior for SoCs having multiple instances of the same core). The results for Heuristic 1 are given in graph form in Figure 2. Each graph contains several measurements for different numbers of available pins P,shon to the right hand side. At the X-axis, the number F of available fast ATE channels is given, the overall test application time (in clock cycles) is depicted at the Y-axis. Note that the values F>Pare not considered. The speed ratio beteen fast and slo channels, l, is set to 2 in all experiments. Thus, slo channels allo for scan chains operating ith half the nominal frequency of the IC. For instance, consider to upper curves in the graph for SOC 1. For the number 5 at the X-axis, the Y coordinates of the curves are 128,928 and 92,664, respectively. This means that for 15 available pins, 5 of hich are connected to the fast channels and the remaining 10 to the slo ones, Heuristic 1 delivered a solution resulting in the test time of 128,928 clock cycle. For 20 available pins (5 of hich are fast and the rest slo), Heuristic 1 created an architecture so that 92,664 clock cycles are required for applying all test sets. Thus, each curve corresponds to a fixed number P of available pins (fast and slo together, the number is given in the legend to the right hand side), and the X-coordinate specifies ho many pins are connected to a fast channel (F ). Note that for F = 10, the upper curve is belo the loer one. From the graphs, one can see that most curves have large horizontal segments. Theses indicate that providing more high-cost, high-speed ATE channels actually does not yield an improvement in test time. It is especially noteorthy that many curves have such a horizontal segment at their end, meaning that using fast channels solely is not efficient since replacing some of them ith slo pins ould result in the same test time. Thus, there is a case for mixing slo and fast channels hen testing a System-on-Chip. Apart from these horizontal segments, increasing F leads to test time reduction. The absolute amount of this reduction seems to decrease for higher values of F. Thus, the question hether the gain in cost due to reduced test time exceeds the cost of using a high-speed ATE channel should determine the final decision. In Figure 3 a comparison beteen different approaches is given. It can be seen that Heuristic 2 does indeed lead to test time reduction compared to Heuristic 1 but that there is still a gap to the optimal algorithm. Hoever, the gap is often not very large. All phenomena noted for the curves obtained using Heuristic 1 also hold for Heuristic 2 and the exact algorithm; a mixture of high-speed and lo-cost ATE channels seems to yield most cost-efficient results also here. The CPU time as negligible for all three experiments involving Heuristics 1 and 2. For the exact algorithm, all measurements (including some not re-

5 SOC 1 15 available pins 20 available pins 25 available pins 30 available pins 35 available pins SOC 1 15 available pins (heuristic 1) 15 available pins (heuristic 2) 15 available pins (exact) 30 available pins (heuristic 1) 30 available pins (heuristic 2) 30 available pins (exact) SOC 2 10 available pins 15 available pins 20 available pins 25 available pins 30 available pins 35 available pins SOC 2 27 available pins (heuristic 1) 27 available pins (heuristic 2) 27 available pins (exact) SOC 3 30 available pins 40 available pins 50 available pins 60 available pins 70 available pins 80 available pins 90 available pins SOC 3 25 available pins (heuristic 1) 25 available pins (heuristic 2) 25 available pins (exact) Figure 2: Experimental Results: Heuristic 1 Figure 3: Experimental Results: Method Comparison ported on here) have been conducted ithin one CPU hour on a Pentium/Linux system. This suggests that Heuristic 2 can be routinely used instead of Heuristic 1 in order to produce better results, hile the computational complexity of the exact algorithm probably makes it orth running it only in case of exceptionally scarce test resources or for very small SoCs. 5 Future Work This paper considers the test cost as a function of to variables, test time and ATE channel speed. No specific assumptions are made about the exact shape of the cost function. Under this presumption, a definitive conclusion can only be made if one cost factor can be reduced ithout affecting the other one. This actually happens, as e sho that fast channels can replace their slo counterparts ithout test time penalty. This being suggestive for itself, it can- not alays determine the cost-optimal number of fast channels to provide. Determining the exact test cost function depending from these to parameters ould allo to obtain the cost-minimal solution. Another interesting point orth further consideration is the impact of ATE channel speed to poer consumption. In CMOS technology poer is assumed to be consumed mainly during sitching operation. Loering the sitching activity by reducing frequency reduces average poer, hile peak poer is not necessarily reduced. One interesting approach ould be to let several slo channels perform their operation asynchronously, i. e. some slo channels sitch in clock cycles 1, 3, 5,..., hilst some other dosoincycles2, 4, 6,...Thisould reduce also the peak poer of the hole SoC. Note that using different nominal frequencies for different inputs of the circuits has been done in context of Built-In Self Test (BIST) [17, 18, 19]. More generally speaking, the problem of satisfying

6 poer constraints in SoC test ith additional flexibility of using fast or slo ATE channels can be seen as a kind of SoC test scheduling problem. To our best knoledge there is no research yet exploiting this flexibility. Also other cost components like memory-perpin or the impact on multi-site testing are a possible subject of future research. 6 Conclusions We studied the effects of mixing fast and slo ATE channels in SoC test. Concentrating on the Distribution Arcitecture, e allocated fast channels among the cores using to heuristics orking on top of the optimal pin assignment algorithm but not alays leading to the global optimum and an exact algorithm based on exhaustive enumeration. Experimental results demonstrated that often providing more fast channels results in little or no test time reduction thus only increasing test costs. There is furthermore a potential for optimizing poer consumption. One objection against the proposed method is the fact that the scan frequency in modern ICs is far belo the performance of high-end tester channels. Hence, the channels employed for scan testing are already lo-cost ones, so that taking even sloer ones instead might not have significant impact on the cost. While this may be true for brand-ne ATE, the situation changes if older equipment is in place. Then, purchasing relatively fe faster channels can lead to results similar to replacing all channels by ne ones. (Note that test systems alloing to mix channels ith different performance have already been available in the past, e. g. from Agilent.) Similarly, our results suggest that in the future, hen the scan frequency ill increase, it may be feasible to replace only some of the channels, thus extending the life cycle of today s investition. We conclude that mixing fast and slo pins may be a free lunch since ATE costs are reduced ith no test time penalty. 7 References [1] Y. Zorian, E. J. Marinissen, and Sujit Dey. Testing embedded-core based system chips. In Int l Test Conf., pages , [2] K. Chakrabarty. Test scheduling for corebased systems using mixed integer-linear programming. IEEE Trans. on CAD, 19(10): , [3] K. Chakrabarty. Design of system-on-chip test access architectures using integer linear programming. In VLSI Test Symp., pages , [4] C. P. Ravikumar, A. Verma, and G. Chandra. A polynomial-time algorithm for poer constrained testing of core based systems. In Asian Test Symp., pages , [5] C. P. Ravikumar, G. Chandra, and A. Verma. Simultaneous module selection and scheduling for poer-constrained testing of core based systems. In VLSI Design, [6] M. Sugihara, H. Date, and H. Yasuura. A novel test methodology for core-based system LSIs and a testing time minimization problem. In Int l Test Conf., pages , [7] Y. Huang, W.-T. Cheng, C.-C. Tsai, N. Mukherjee, O. Samman, Z. Yahia, and S. M. Reddy. Resource allocation and test scheduling for concurrent test of core-based SOC design. In Asian Test Symp., pages , 20. [8] V. Iyengar, S.K. Goel, E.J. Marinissen, and K. Chakrabarty. Test resource optimization for multi-site testing of SOCs under ATE memory depth constraints. In Int l Test Conf., pages , [9] J. Aerts and E. J. Marinissen. Scan chain design for test time reduction in core-based ICs. In Int l Test Conf., pages , [10] P. Varma and S. Bhatia. A structured test reuse methodology for core-based system chips. In Int l Test Conf., pages , [11] E. J. Marinissen, R. Arendsen, G. Bos, H. Dingermanse, M. Lousberg, and C. Wouters. A structured and scalable mechanism for test access to embedded reusable cores. In Int l Test Conf., pages , [12] I. Polian and B. Becker. Optimal bandidth allocation in concurrent soc test under pin number constraints. In Workshop on RTL and High Level Testing (WRTLT), pages 12 17, [13] F. Brglez, D. Bryan, and K. Kozminski. Combinational profiles of sequential benchmark circuits. In Int l Symp. Circ. and Systems, pages , [14] I. Hamzaoglu and J.H. Patel. Ne techniques for deterministic test pattern generation. Jour. of Electronic Testing: Theory and Applications, 15:63 73, [15] S. Kajihara, I. Pomeranz, K. Kinoshita, and S.M. Reddy. Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits. IEEE Trans. on CAD, 14(12): , [16] I. Pomeranz, L.N. Reddy, and S.M. Reddy. COMPACTEST: A method to generate compact test sets for combinational circuits. In Int l Test Conf., pages , [17] S. Wang and S.K. Gupta. DS-LFSR: A ne BIST TPG for lo heat dissipation. In Int l Test Conf., pages , [18] R. Sankaralingam, B. Pouya, and N. Touba. Reducing poer dissipation during test using scan chain disable. In VLSI Test Symp., pages , 20. [19] N.Z. Basturkmen, S.M. Reddy, and I. Pomeranz. A lo-poer pseudo-random BIST technique. In Int l Conf. on Comp. Design, pages , 2002.