Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling

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1 Manuscript - Main file Click here to download Manuscript: JETTA.tex Click here to view linked References Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling Spencer K. Millican and Kewal K. Saluja Department of Electrical and Computer Engineering, University of Wisconsin-Madison, WI Engineering Dr., Madison, WI 0 smillican@wisc.edu, saluja@ece.wisc.edu Abstract As a consequence of technology scaling and increasing power consumption of modern high performance designs, various techniques, such as clock gating and Dynamic Voltage and Frequency Scaling (DVFS), have been adapted to address power issues. These techniques are important and desirable to address reliability needs as well as economic issues. From a testing point of view, introduction of power constraints during testing is needed to achieve the desired product quality and to avoid yield loss. Unlike designers who have benefited from the Design-for- Test hardware introduced for testing, test engineers have rarely taken advantage of the extra hardware introduced to meet design needs. In this paper, we make use of the DVFS technology and its associated hardware to improve test economics. We formulate the power constrained testing problem as an optimization problem that makes use of DVFS technology. We show that we can obtain superior test schedules for both session-based and sessionless testing methods relative to existing and traditional methods of obtaining test schedules. I. INTRODUCTION System-on-Chip (SoC) designs have become commonplace in modern Integrated Circuit (IC)s. A SoC consists of existing designs of Intellectual Property (IP) cores combined into a single package, thus creating a large design in a relatively short period of time. These IP cores can either exist as hard cores, cores in which the SoC designer cannot make changes to the design, or soft cores, cores in which the designer has some leeway in the implementation of the design. However, combining several modules into a single package makes the testing of devices more challenging. When IP core providers create their designs, they often provide pre-defined tests to the user, with the guarantee that the test vectors given will thoroughly test the core. This is because the implementation of the core is often hidden from the user to keep the core design proprietary, and thus the SoC designer may not be able to create their own tests. Because of these proprietary test sets, the objective of SoC testing is to apply a given set of tests for each module in the shortest possible time while testing all modules in the SoC. In this paper, a test is defined as a set of vectors given by an IP core provider to test a core. In some cases, more than one test may be required to test a core, for instance in the case that a core may need to be tested by different sets of vectors, or under different conditions, etc. SoC test scheduling originated as a hardware-constrained problem [] []. Since individual modules of a SoC often share common hardware to save chip area or for reasons such as performance or power issues, simultaneous testing of all modules of an SoC that have such commonalities is often infeasible. These kinds of hardware constraints can either come from test-specific hardware used to apply tests or the presence of other hardware shared between cores, like shared memories. The goal in SoC test scheduling has always been to schedule all tests of an SoC in the smallest possible period of time while not violating the given hardware constraints [], []. In some scheduling models the test scheduler has hardware constraints pre-defined [], while in others the hardware for applying tests could be generated by the scheduler, often with some constraints on the hardware to be generated []. Although the latter model has the ability to obtain higher quality (shorter) test schedules, the tester often does not have the ability to influence the hardware of the final design. Although this is a relatively simple problem compared to testing designs with modern temperature and power constraints, this is still an NPhard problem []. As the feature sizes of devices under test have become smaller, the number of transistors per unit area have introduced new constraints, such as power during test. Although Moore s law originally assumed that the power per unit area of a silicon chip would stay constant [], this assumption is being violated. Instead, the power density of ICs during normal operation has increased. During test, the power density of ICs is further increased not only by the use of test-specific hardware not utilized during normal operation, but also due to the higher switching activity of circuits from time-saving tests [], []. As a result, power during SoC test has become yet another problem to address. A very high power dissipation can cause damage to the device under test, or it can create voltage sag induced false failure(s) []. Both of these problems reduce device yield, and therefore increase manufacturing cost. The result of all of this is that power consumption during test has become a new constraint during testing. With powerconstrained testing, not only must the hardware constraints be met, but also a given maximum power value, set either based on the power supply used or by the properties of the devices, must not be violated. Like hardware-constrained testing, this is an NP-hard problem, but the practical complexity grows significantly compared to hardware-constrained test scheduling. Like hardware-constrained testing, several methods have

2 been proposed to solve power-constrained testing, such as graph formulations [], ILP formulations [], and various other algorithms [], [], [], each providing a trade-off between test schedule quality and test schedule computation time. A new technology which can provide potentially better schedules in exchange for more complex scheduling is dynamic voltage and frequency scaling (DVFS). DVFS has been used in recent high-performance designs to allow processors to save power and energy during less demanding intervals of operations by decreasing their operating frequency and voltage supply []. This decrease in voltage and frequency effectively slows down the operation of a given core or module of the SoC while at the same time lowering its power consumption. Although not its original intended purpose, DVFS technology can also be used to scale the power and test application time (Test Application Time (TAT)) of individual tests. This can either be done to test devices more thoroughly [], [], or to find more compact test schedules under power constraints [] []. Test scheduling using DVFS has been studied in the recent past [], [] [], but the methods proposed in literature have either ignored the power during test aspect, or the solutions proposed have been less than optimal by relying on session-based formulations and other more restrictive than desired constraints. In our earlier work presented in [] we addressed this problem to an extent. This paper is an extension of the study done in []. Extensions include a new and superior formulation to address optimality concerns. The main contributions of this paper are as follows: An optimal formulation for SoC test scheduling under power and hardware constraints using DVFS is presented, for both session-based and sessionless environments. It is shown that DVFS scheduling can provide better and more compact test schedules for power constrained testing compared to schedules without utilizing DVFS technology. Sessionless formulations are shown to generate superior test schedules compared to session-based formulations without excessive computation overhead. The remainder of the paper is organized as follows. Section II gives a brief history of power-constrained and DVFS testing. Section III gives a session-based formulation for DVFS to obtain optimal test schedules, while Section IV gives a sessionless formulation. Section V gives the experimental setup used to evaluate the effectiveness of the two formulations, while Section VI provides the results for various SoC benchmarks, and the paper concludes with Section VIII. II. PAST WORK A. Session-Based & Sessionless Test Scheduling After the introduction of hardware-constrained test scheduling [], the first modifications to be investigated were the formulation of various scheduling strategies and their relative merits while scheduling under hardware constraints []. In particular, two strategies were investigated for the case when duration, i.e. TAT, of each test is not same. The two strategies were session-based and sessionless scheduling. Scheduling tests in a session-based manner can be viewed as a bin selection problem, where each test must be assigned to a bin, but no two tests can be assigned to the same bin if they are incompatible (due to sharing of resources, such as common hardware). After each test has been assigned to a bin, the TAT of each bin is the TAT of the longest test in the bin, and the TAT of the schedule is the sum of the TAT of each bin. Initial test-scheduling formulations were for session-based testing due to their simplicity []. Sessionbased scheduling problems can be expressed in many different formulation styles, such as graph-based algorithms or Mixed- Integer Linear Programming (MILP) formulations. However, a deficiency of session-based formulations is that they lack the ability to exploit potential overlaps. When tests are assigned to sessions, it is impossible to overlap tests with any other test outside of the session, even if those tests are compatible. This occurs because every test assigned to a session must be compatible with each other. Because every test in a session must be compatible, partial overlaps cannot be taken advantage of (see Figure ). Although these partial overlaps may not decrease the total TAT by large amounts, small decreases in TAT can still lead to significant reductions in test cost. t t t t t t Session Session Session a) session-based schedule b) sessionless schedule t t t t t t Fig.. Presuming that tests t and t are compatible, test time can be reduced by eliminating session requirements. Formulations for sessionless test scheduling have attempted to remedy the overlapping restraints of session-based formulations as follows. For any sessionless scheduling method, tests must be able to be scheduled arbitrarily in time (either continuously in time or at discrete time intervals). This requirement intuitively increases the complexity of sessionless scheduling methods, since many more candidate tests schedules are available to choose from. Due to their more complex nature, solutions for sessionless scheduling often make use of heuristics, and a common heuristic is to use list-based algorithms []. However, there have also been instances of using MILP-style formulations for hardware-constrained test scheduling [0]. Although these formulations often have to make presumptions on the nature of tests (e.g., the power throughout a test is constant), they have the benefit of being deterministic and always giving an optimal solution for the given test model. Although sessionless formulations are successful in finding shorter test schedules, as suggested earlier they intuitively do so at the expense of longer computation times or heuristic based results while providing no guarantee that the quality of the solution will be better. Because every session-based schedule can be expressed as a sessionless schedule, it is impossible for an optimal sessionless formulation to obtain a worse test schedule than an equivalent session-based for-

3 mulation. However, if there are no partial overlaps to take advantage of, then both formulations will obtain the same result. Given this is the case, one may be hesitant to make use of a sessionless formulation if the computational overhead is too great. However, it will be shown in Section VI that this may not be the case, which would therefore mean one should always take advantage of a sessionless formulation. B. Power & DFVS Test Scheduling One of the first studies into power-constrained test scheduling was done by Chou et. al. []. In this study, the complexities of power-constrained test scheduling were first observed as an extension to hardware-constrained test scheduling. The scheduling problem was viewed as a hardware-constrained test scheduling problem with a test or a set of tests being designated as incompatible with other tests if their combined power was greater than the given power bound. This constraint was not just applied to pairs of tests, as would be the case with hardware constraints, but to all combinations of tests. This was because two combined tests may have adequate power consumption, but adding a third may put the power consumption over the limit. This study implied that powerconstrained test scheduling is more complex than hardwareconstrained test scheduling. The approach used to solve the test scheduling problem was a graph-based approach, in which all possible cliques and their sub-cliques of a graph are found, with each clique or sub-clique corresponding to a test session. This approach relied on an earlier implementation of hardware-constrained test scheduling [], where each test in a clique must be hardware compatible. However, if power constraints are enforced then an additional requirement is that the sum of power of all tests in a clique or sub-clique must also be lower than the given power constraint. This graphbased approach has effectively been implemented in MILP formulations in [], [], []. As power during test has become larger due to smaller IC feature sizes, DVFS has been explored as a new technique to achieve better test schedules without violating power constraints. The original purpose of DVFS was to decrease the operating voltage and frequency of a module or core when the workload on it decreased so as to save power without hindering performance []. However, DVFS can also be used to slow down or speed up individual tests during scheduling to allow for better test compaction (reduced TAT) under power constraints. If the operating voltage or frequency is lowered for a test, then the test will take longer to complete, but at the same time the test will consume less power. This can allow for two tests, that normally could not run in parallel due to their combined power being too high, to be made compatible by lower operating voltage or frequency for one or more of the tests. Likewise, a test that must be run individually can increase its operating voltage and frequency to decrease the time needed to apply the test at the expense of increased power consumption. Initial work on DVFS test scheduling focused on scheduling all possible voltage or frequency combinations of a given core, thereby thoroughly testing a device []. DVFS hardware can be used to apply different operating voltages to reveal faults caused by improper transistor operation, and to apply different operating frequencies to reveal delay faults and other voltage/frequency dependent faults. Studies to schedule such tests take the form of a hardware-constrained test scheduling problem, since the goal of such studies is to test all possible DVFS combinations for each IC regardless of power. However, such test models presume tests need to be applied at multiple voltage values, which is not the case for non-voltage dependent faults. Therefore, such studies have not considered that only a single voltage and frequency pair or a subset of voltage frequency pairs need be scheduled for a given test, nor have they considered the power dissipated during test as a constraint. Some recent work focuses on scheduling tests such that every test is scheduled with a single voltage and frequency pair under power constraints [], [], with the goal being to schedule each test at least once. Initial work focused on only frequency scaling [], which was considered to be a simpler problem since power scales linearly with operating frequency. After frequency scaling alone was studied, voltage scaling was added []. Both cases showed that allowing for voltage or frequency scaling would result into significantly better test schedules with power constraints. However, these studies not only presumed that scheduling was done in sessions, but they also presumed that for any given session the voltage and frequency pair for every test in the session must be the same, which can lead to inferior results. III. SESSION-BASED TESTING The first formulation presented in this paper is for sessionbased testing of SoCs. This formulation is presented for the purpose of gaining an understanding of DVFS scheduling, as well as to gain a perspective on the deficiencies of sessionbased formulations. A. Test Environment and modeling Before a formulation can be made, the model that is used for power during test must be stated, as well as the model which defines how DVFS is used during test. Since using different models can give different test schedules, Section VIII will discuss what effect other testing and DVFS models will have on this study and how the proposed formulations can be extended to fit other models. The first presumption of the test model is that the power dissipated by a test is constant throughout the entire test. This assumption is made so that the power values of a test can be directly used in an MILP-style formulation, because changing power values during test not only drastically increases the complexity of any formulation, but also makes it difficult to model the scheduling problem with linear constraints. This assumption, that the power during test is constant, has been made by majority of the formulations in the past due to its simplicity. For tests that do not have constant power dissipation, the power dissipation can be presumed to be the maximum power dissipation of a test, otherwise overlapping tests may cause a combined power violation. The implications of nonconstant power modeling are further discussed in Section VII.

4 Power (W) Frequency Scaling Only Frequency (GHz) Frequency & VDD Scaling Fig.. By scaling V DD with frequency as opposed to frequency alone, better power reduction can be achieved. It is also assumed that the V DD and frequency of any test can be independently controlled at any time, regardless of what session it is scheduled in or what other tests it overlaps with. Modeling in this manner will make this formulation different and more practical compared to the formulation proposed in []. In [], it was assumed that every test in a session must have the same V DD and frequency applied to it. By eliminating this assumption, better schedules can be obtained by allowing for better compaction of tests within a session. However, this will not always be the case since several cores may share a voltage and/or frequency source. If this were the case, specific constraints can be added to enforce incompatibility between tests if they used different voltage and frequency values (i.e., if the tests overlap that share DVFS hardware, then their operating voltage and/or frequency must be the same). In this paper it is assumed that the time overhead required to change the operating V DD and frequency of a test is negligible. This lack of switching overhead implies that a test can change from any voltage and/or frequency value to any other value instantly. However, in real hardware this is not the case. Although the time overhead to change operating frequency through clock division is relatively negligible [], this is often not the case with changing voltage []. The simplest way to incorporate this switching overhead is to increase the time of every test to include this switching overhead. For instance, the time to switch from normal operating voltage to 0.V is added to the TAT of a 0.V test. The last aspect of modeling is how operating V DD and frequency are chosen for test scheduling. An initial assumption is that during normal V DD operation (in this study, V ), the operating frequency is chosen so as to not violate timing constraints. This means the operational frequency of a test can be increased (therefore decreasing the length of the test) only if the operating voltage is increased. Likewise, if the frequency of a test is decreased (test length increased), the operating voltage may be decreased since there is no requirement to have a higher voltage drive the lower operating frequency. Given this observation, every voltage value should have only the highest possible frequency value assigned to it, since assigning any lower frequency value would only waste power and increase test time or both. The same can be said of assigning voltage values to frequency values, but in this study pairs are chosen based on voltage since it is presumed that frequency can be scaled more finely, whereas voltage can only be scaled by set amounts, which is often the case with DVFS due to the high hardware overhead of implementing voltage scaling []. From this, for a given voltage value, the frequency can be set according to the alpha power law [], [], where f s is the factor by which frequency is scaled: f s (V DD V T H ) α V DD The motivation for scaling voltage with frequency as opposed to scaling frequency alone is that scaling voltage along with frequency allows for less power to be consumed. If the scaling of frequency is done alone, the dynamic power consumption is scaled by the same factor. However, scaling to a lower frequency allows for voltage to be scaled lower as well. By scaling voltage to the lowest possible value for a given frequency, the relation between frequency and power is no longer linear, but is instead cubic, since the relation between dynamic power consumption and DVFS is P f V DD, where f is frequency. This concept is illustrated in Figure, which presumes a normal operating frequency of GHz and normal power consumption of W. In this paper, it is assumed that modern short-channel MOSFET technology is used, with V DD = V, V T H = 0.V, and α =. []. B. Formulation The formulation for both session-based and sessionless scheduling are given in the form of a MILP formulation. In this section a session-based formulation is given, and the sessionless formulation is introduced in Section IV. Because of the analysis of Section II, this style of formulation was chosen due to its deterministic nature. A detailed formulation of the session-based scheduling problem is given below. The first constraint of any scheduling formulation is to define the objective, and the objective in this case is to minimize the total TAT of the schedule, given in the formulation as finish. Also in this notation, S is the set of sessions. Since the constraint must be made linear, this can be done by forcing the overall TAT to be greater than or equal to the end time of each session s S, E(s). minimize f inish subject to... s S : finish E(s) Clearly, the begin time and end time of each session, B(s) and E(s), is dependent on the TAT length of the session, L(s). Also, the begin time of each session is guaranteed to be the end time of the previous session, since doing otherwise would only waste time. Note that the maximum possible number of sessions is equal to the number of tests, t T (i.e., S = T, since the worst-case schedule would have every test assigned to its own session, i.e., no two tests would run in parallel). Also, in this formulation it is possible for some sessions s S to be empty (i.e., have no tests in them), and therefore have a TAT length L(s) = 0. s S : E(s) = B(s) + L(s)

5 s =... S : B(s) = E(s ) B() = 0; To allow tests to be assigned to sessions with a given DVFS pair assigned to it, the variable Θ(t, s, n) is introduced. Here, each t T is a test, each s S is a session, and each n N is one of the N possible voltage/frequency pairs at which a test can run. This variable will force tests to belong to one and only one session while also forcing tests to use one and only one DVFS pair. if the test t is assigned to session s Θ(t, s, n) = and assigned to V DD /frequency pair n t T : s S Θ(t, s, n) = If two tests are hardware incompatible due to hardware constraints, then it is impossible for them to be scheduled in the same session regardless of a power constraint. Such hardware constraints are included to address shared computation resources (e.g., memory or I/O) or test-specific hardware (e.g., Built-in Self-test (BIST) or Test Access Mechanism (TAM)). More implications on the specific hardware constraints used are discussed in Section VII. The constant Γ(t, t ) is introduced to enforce hardware compatibility constraints. { if tests t and t Γ(t, t ) = are incompatible t, t T, s S : Θ(t, s, n) + Θ(t, s, n) Γ(t, t ) The TAT of each session is defined as the longest time amongst all tests within the session. Since the number of sessions is set to the number of tests, some sessions may be unused. If such is the case, the TAT of each session must be at least 0. Here, L t,n is the TAT of a test t if the n th voltage/frequency pair is chosen for it. s S : L(s) 0 s S, t T, n N : L(s) L t,n Θ(t, s, n) To satisfy a given power constraint, the sum of power from all tests in a session must be lower than the given power bound in every session (even if the session is empty). Below, P t,n is a constant equal to the power of a test t if the n th voltage/frequency pair is chosen for it. s S : t T P t,n Θ(t, s, n) P BOUND IV. SESSIONLESS TEST SCHEDULING As was stated in Section II-A, session-based formulations will often fail to find a low test time solution due to their restricted nature. It is easy to see that any possible sessionconstrained schedule can be converted to a sessionless schedule in the sense that no resource and power constraints are violated, but not every sessionless schedule can be stated as a session-based schedule. Therefore, if there is any test set which has a better sessionless schedule than an optimal session-based formulation, then sessionless formulations are guaranteed to find a schedule which is no worse (but often better) than a session-based formulation. Such a schedule has already been presented in Figure. Although a previous formulation gave a method for enforcing a power constraint for non-sessionbased scheduling [], the method had some limitations. The constraint given therein was in the form of for every test, the sum of powers of all other tests that overlap with this test (including itself) must be less than the power boundary. This style of constraint will successfully implement a sessionbased schedule, and it will also allow for some schedules that session-based scheduling cannot implement, but it was unable to search for all sessionless schedules. The formulation presented here, however, will provide a truly optimal sessionless schedule. Unlike with session-based test scheduling, tests can be scheduled arbitrarily in time as long as no two overlapping tests have a hardware constraint. Because of this, timing constraints need to be redefined. First, test application time is no longer based on sessions, but based on individual tests. Therefore, the terms B(s) and E(s) are redefined as B(t) and E(t), i.e., they are based on each test t T instead of each session s S. minimize f inish subject to... t T : finish E(t) t T : E(t) = B(t) + L(t) t T : B(t) 0 The TAT of each test, L(t), is dependent on the DVFS pair chosen for that test. A new binary variable Ψ(t, n) is introduced for this purpose. Ψ(t, n) = t T : if the test t is assigned to V DD /frequency pair n n=...n t T : L(t) = Ψ(t, n) = L t,n Ψ(t, n) To keep tests from overlapping that have a hardware incompatibility between them, the constant Γ(t, t ) can be reused. However, the fashion in which the constant is used must be changed, since tests are no longer assigned to sessions, but instead can overlap arbitrarily. To define how tests can overlap, the method from [0] is borrowed to accomplish this. Here, λ is defined as the longest possible test schedule, which is the

6 sum of run times of all tests at their slowest frequency. Setting λ to such or a higher value allows for the arbitrary scheduling of the start time of any test from time 0 to λ L(t) while defining overlapping tests. η(t, t ) = if the test t finishes before the test t begins t, t T : E(t ) B(t ) + ( η(t, t )) λ t, t T : B(t ) < E(t ) + η(t, t ) λ Two tests t and t are overlapping if both η(t, t ) and η(t, t ) = 0. Using this, hardware compatibility can be enforced. t, t T : η(t, t ) + η(t, t ) t, t T : η(t, t ) + η(t, t ) Γ(t, t ) From this, a simple variable stating if two tests overlap can be made, Ω(t, t ) : { if test t overlaps with test t Ω(t, t ) = t, t T : Ω(t, t ) = (η(t, t ) + η(t, t )) To enforce a sessionless power constraint, it can be observed that as long as the power during a test is constant, the only time the power constraint needs to be checked is when any test begins. The reason for this is that the only time the power consumption can increase is when a test begins. When a test finishes, the power consumption of the test can obviously only decrease, and if the power during a test is constant, the power consumption of a test cannot increase after a test has already begun. Although it is possible for the power of a device to increase when a test finishes if another test begins at the same time, this event coincides with the start of the second test. To check the power of a device whenever a new test begins, a new variable π(t, t ) is introduced. π(t, t ) = if the test t begins before or when the test t begins t, t T : B(t ) B(t ) + ( π(t, t )) λ L t, t T : B(t ) > B(t ) + π(t, t ) λ L t T : π(t, t) = Using this new π(t, t ) variable and Ω(t, t ), the power constraint should only be checked when each test starts. A new variable is introduced, P (t, t ), which is the power of test t at the time when t starts. The purpose of the first two equations below is to force P (t, t ) to be 0 if either π(t, t ) or Ω(t, t ) is 0, while the third equation forces P (t, t ) to be the power of test t with both π(t, t ) and Ω(t, t ) are. Below, λ p is largest possible power value of P (t, t ) (i.e., all tests executed in parallel at their highest voltage and frequency). t, t T : P (t, t ) Ω(t, t ) λ P t, t T : P (t, t ) π(t, t ) λ P t, t T : P (t, t ) Ψ(t, n) P t,n ( Ω(t, t )) λ p ( π(t, t )) λ p The final power constraint for sessionless test scheduling can be expressed as for every test t, the sum of power from every test that starts at the same time or before t that also overlaps with t must be less than the power bound. This constraint is implemented below. Note that since Ω(t, t) = and π(t, t) =, a lone test will always have its power checked. t T : P (t, t ) P BOUND A. Benchmarks t T V. EXPERIMENTAL SETUP The Benchmarks used in this study are based off the ITC 0 benchmarks []. These benchmarks represent SoCs and provide test length and complexity information in the form of the number of vectors, the number of scan flip-flops, and the number input and output pins to the module. Although they provide this module information for the purpose of generating various test related hardware during test scheduling (i.e. TAM pin and bus assignments), this study generates hardware compatibility graphs by solving a non-power constrained, non- DVFS schedule using the method given in [] while imposing modest TAM pin constraints, since hardware compatibility is not the focus of this study. Since the original benchmarks do not contain significant power information, power traces for individual modules and their tests are generated by simulating ITC circuits []. Power traces are assigned to modules by matching the size and complexity of the ITC 0 modules to the relative size and complexity of the ITC circuits based on pin count and flip-flop count. It is assumed that that the more input/output pins a module posses, the greater the area of a module, and therefore the greater the power dissipation. By matching the largest ITC 0 benchmark to a reasonable size and test power density ( mm x mm footprint, and. W/mm test power density), power densities can be assigned to all other benchmarks. Also, a test power constraint of W/mm is set on each benchmark, which is purposely set lower than the maximum test power dissipation since the maximum test power can either destroy a device, as test power is often greater than normal operating power []. Also, combinations of the u, g, f, q, and a ITC 0 benchmarks are taken to generate more complex benchmarks. This subset of benchmarks was chosen due to the high computation time of session-based scheduling, as will be seen in Section VI. B. Implementation The purpose of the first experiment is to evaluate the effectiveness of session-based scheduling as opposed to sessionless scheduling across a series of benchmarks. Information on the sixteen benchmarks used to evaluate the scheduling methods is provided in Table I, which includes the number of tests in the

7 TAT (/MAX) TABLE I BENCHMARK INFORMATION Bench ITC 0 Benchmarks # Tests Max Pow P BOUND u 0..0 g..0 f.. q.0. a.0.0 u, g.. u, f.. u, q.0. u, a.0. g, q, u.0. f, q, u.0. q, a, u 0.0. g, q, a.0. g, f, a.. g, f, q.0. u, q, a 0.0. TABLE II BENCHMARK RESULTS Bench TAT (us) CPU Time (s) Sessionless Sessions Sessionless Sessions benchmark, the maximum power consumed by any given test in the benchmark, and the power bound for each benchmark, which are generated based on pin count information described in the previous section. The first experiment records two results for each scheduling method on each benchmark: the optimal scheduled TAT, used for the purpose of evaluating the quality of the schedule, and the computation time required to obtain the optimal schedule, to evaluate practicality of the formulation. The second experiment is done to evaluate the effectiveness of DVFS scheduling as more DVFS pairs become available to schedule. The sixteen benchmarks and are run with a varying number of DVFS pairs available for scheduling to observe the effect DVFS has on TAT. This will give insight to the effect DVFS has on power-constrained test scheduling. All MILP formulations are implemented using IBM ILOG CPLEX, and they are run to completion to find an optimal solution for a given formulation. VI. RESULTS Table II shows the results of session-based and sessionless DVFS scheduling on sixteen benchmarks, presuming a normal operating V DD value of V and a normal operating frequency of MHz. For these benchmarks, four V DD values were Lowest Possible VDD (V) Fig.. As more voltage options become available, better schedules can be obtained. available for each test to choose from (, 0., 0., and 0.V). The frequency values corresponding to these V DD values are obtained using the method as described in Section III-A. The results in Table II clearly show that for any benchmark the schedule obtained by sessionless scheduling is always equal to or better than that achieved by session-based scheduling. The reason for this, as explained in Section II-A, is that any session-based schedule is possible with sessionless scheduling, but certain sessionless schedules cannot be expressed as session-based schedules. Although there are instances where session-based scheduling achieves the same result as sessionless scheduling, it clearly can never obtain a higher quality schedule. Although sessionless scheduling can clearly give better TAT results, the primary motivation behind session-based scheduling is the simplicity of implementation, and thus reduced design effort and hardware complexity. Also, it is intuitively expected that the computation effort to find a solution to session-based scheduling is lower than that for sessionless schedules. However, the results in Table II show a contrary phenomenon. The scheduling time for sessionless scheduling is negligible for all sixteen benchmarks, but for two benchmarks ( and ), the computation time increases dramatically for session-based scheduling. The reason for this anomaly is unclear, although it may be that both methods require a similar number of variables to solve, even though the sessionbased scheduling problem is intuitively simpler. In sessionless scheduling, the primary variable in question is the start time of each test (B(t)), while in session-based scheduling the primary variable is which session a test belongs to (in this study, implemented using Θ(t, s, n)). From the point of view of a MILP solver, session-based scheduling may actually be more complex since the primary variable is implemented using several binary variables as opposed to a single integer variable. It may be possible to make the session-based formulation more efficient, but the point remains clear that a sessionless formulation is by no means overly complex to implement or time-consuming to solve. Figure gives the TAT of sessionless formulations for the sixteen benchmarks as the allowed range

8 TAT (us) Lowest Possible VDD (V) Session-Based Sessionless Fig.. Even as more voltages become available for scheduling, sessionless scheduling will still give better schedules than session-based schedules. of voltage values increase. The figure gives the TAT as a fraction of the TAT when no DVFS is allowed, i.e., scheduling with only V V DD and MHz available for scheduling. The value at the X-axis represents the lowest possible voltage value allowed, with the all voltage values allowed between that value and V with a 0.0 V granularity. For instance, for the 0. V data point, the voltage values available to schedule for each test is, 0., 0., 0., and 0. V. One observation based on Figure is that as lower voltage values are allowed for scheduling, the TAT can be greatly reduced. It is true that lowering voltage values can allow for the overlapping of tests that was not possible before due to power constraints, but at the same time lowering voltage values (and in turn lowering operating frequency) increases individual test lengths. This leads to the conclusion that the effect of reducing test power outweighs the effect of increasing test time due to greater test overlap potential. A second observation from Figure is that DVFS may make test scheduling possible for circuits that were not testable without DVFS, because a test along at normal operating voltage may violate the power constraint. This is shown in Benchmark #, which is not possible to schedule until 0. V V DD is allowed, as is evident in Figure. Although it is not wise to create a design with test power higher than a given limit, this may be the case with high-power designs, since test power is often higher than normal operating power []. This may also be the case if leakage power is added to the power model, which is not done in this study. Figure gives the TAT of both session-based and sessionless formulations for Benchmark # as the allowed range of voltage values increases. An observation based on Figure is that for any DVFS value available for scheduling, sessionless schedules always perform better than session-based schedules. This is a trend observed in all benchmarks. This is confirmation of the statement made in Section II-A, since adding DVFS generates more scheduling possibilities and sessionless scheduling can take more advantage of these scheduling options which session-based scheduling cannot. VII. DISCUSSION Although this study presumed hardware constraints to be pre-defined, allowing a scheduler to configure test-specific hardware in order to reduce TAT, like TAM pin allocations, may be implemented using using this formulation as well As stated in Section III, the scheduling method in this study presumes that tests have pre-defined hardware constraints between them that prevent their simultaneous execution. Examples of such hardware constraints can be shared resources, such as shared memory or shared I/O ports, or can be shared testspecific hardware, like BIST or TAM hardware. However, if the scheduler has the ability to control how limited TAM and BIST resources are allocated during the scheduling process, then achieving a shorter TAT is possible. Such scheduling formulations have been implemented in the past, where the total number of TAM pins is a constraint of the scheduling process []. Although the formulation presented here does not incorporated TAM pin constraints in the scheduling process, the authors believe that it is possible to include such a constraint in the formulation. The authors believe that once such a constraint is introduced, the test scheduling formulation will not only be more accurate, but also will be able to achieve more effective test schedules. This incorporation of TAM constraints is left for future work. Although solving MILP formulations requires the use of NP-hard algorithms, which in turn makes the solving of MILP problems infeasible for large instances, such MILP formulations are still useful for large problems. As the number of cores on SoCs scales upward, solving an MILP scheduling formulation may become infeasible. If this is the case, a heuristic approach will be needed instead of finding an optimal solution. However, many MILP solvers can still be used to find a non-optimal solution, in essence turning an MILP formulation into a heuristic. Clearly a heuristic in which an SoC test scheduling problem is split into several smaller scheduling groups, which in turn can be solved optimally using an MILP formulation, can be very useful in finding a nearly optimal schedule for a large problem. In either of these cases, solving optimally or solving using a heuristic, an MILP formulation can be used. Also a challenge to further improving the quality of SoC test scheduling is modeling tests more accurately, thereby achieving higher quality test schedules. A major assumption made in this and other studies is that the power of a test is constant during its application. Depending on the nature of tests involved, this may not be the case, since the power of a test can fluctuate greatly, thereby making the actual power of a test far from its model power, which must be the maximum power of a test to avoid invalid test schedules. If the maximum power dissipated by a test is much higher than the actual power of a test, then it is possible that not all potential test overlap is being taken advantage of. Although the current test scheduling formulations can more closely model the actual power of a test by modeling a single test as several smaller tests [], such methods exponentially increase the complexity of the scheduling problem. Also, depending on the specific DVFS hardware of the SoC, it may be impossible for two or more tests to execute simultaneously at different

9 voltage and/or frequency values. Scheduling tests under such environments has been explored [], although the nature of such scheduling formulations makes other assumptions which produce a less-than optimal test schedule. It is left for future work to overcome these challenges. The benefit of the TAT reduction achieved by the proposed formulations can also be further applied to different DVFS test scheduling models. For models that presume tests must be scheduled for every DVFS voltage, each test is replicated to represent running a test at a particular voltage level and the variable determining operating voltage will also determine the operating frequency for a test. To model the existence of voltage islands (multiple modules sharing the same voltage/frequency source), a new MILP constraint can be added to force the Ψ values of two tests to be equal if they are scheduled simultaneously and they share the same voltage/frequency source. In both cases, the proposed formulations will achieve lower TAT compared to previous formulations, and sessionless scheduling will allow for lower TAT than session-based scheduling. VIII. CONCLUSIONS Scheduling tests in a DVFS environment shows the potential for greatly reducing TAT for multi-core SoCs under power constraints. As voltages are scaled lower, individual test times are sacrificed for reduced power consumption. This trade off allows for greater test time compaction under power constraints, which in turn leads to better test economy. To take maximum advantage of DVFS scaling, the sessionbased test scheduling barrier must be broken. By breaking this barrier, better test schedules can be found, thereby reducing TAT and leading to better test economy. Although sessionbased scheduling has been previously implemented to reduce schedule computation time through simpler formulations, this study has shown that the computation time of sessionless formulations is by no means a hindrance to their implementation. REFERENCES [] C. Kime and K. Saluja, Test Schduling in Testable VLSI Circuits, in Twenty-Fifth International Symposium on Fault-Tolerant Computing, (Santa Monica), pp. 0, IEEE,. [] K. Chakrabarty, Test scheduling for core-based systems using mixedinteger linear programming, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol., no., pp., 000. [] Y. Zorian, A distributed BIST control scheme for complex VLSI devices, in Digest of Papers, th Annual IEEE VLSI Test Symposium, pp., IEEE Comput. Soc. Press,. [] G. Moore, Cramming more components onto integrated circuits, Electronics, vol., no.,. [] S. Samii, M. Selkala, E. Larsson, and K. Chakrabarty, Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol., pp., May 00. [] P. Girard, N. Nicolici, and X. Wen, Power-Aware Testing and Test Strategies for Low Power Devies. Springer, 0. [] M. Nourani and J. Chin, Power-time tradeoff in test scheduling for SoCs, in Proceedings of the st International Conference on Computer Design, pp., IEEE Comput. Soc, 00. [] R. Chou, K. K. Saluja, and V. D. Agrawal, Scheduling Tests for VLSI Systems under Power Constraints, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol., pp., June. [] Z. He, Z. Peng, and P. Eles, Power Constrained and Defect-Probability Driven SoC Test Scheduling with Test Set Partitioning, in Proceedings of Design, Automation & Test in Europe (DATE), pp., IEEE, 00. [] D. Zhao and S. Upadhyaya, Dynamically partitioned test scheduling with adaptive TAM configuration for power-constrained SoC testing, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol., pp., June 00. [] K. Nose and T. Sakurai, Optimization of VDD and VTH for Low- Power and High-Speed Applications, in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), pp., IEEE, 000. [] X. Kavousianos, K. Chakrabarty, A. Jain, and R. Parekhji, Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands, IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, vol., pp., Nov. 0. [] X. Kavousianos, K. Chakrabarty, A. Jain, and R. Parekhji, Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands, in 0th Asian Test Symposium, pp., IEEE, Nov. 0. [] S. K. Millican and K. K. Saluja, Formulating Optimal Test Scheduling Problem with Dynamic Voltage and Frequency Scaling, in nd AsianTest Symposium (ATS), pp., IEEE, Nov. 0. [] V. Sheshardi, V. D. Agrawal, and P. Agrawal, Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages, in th International Conference on VLSI Design and International Conference on Embedded Systems, (Pune, India), pp., Jan. 0. [] V. Sheshardi, V. D. Agrawal, and P. Agrawal, Optimal Power- Constrained SoC Test Schedules With Customizable Clock Rates, in IEEE International SOC Conference (SOCC), (San Jose, CA), pp., Oct. 0. [] H. Salamy and H. M. Harmanani, An optimal formulation for test scheduling network-on-chip using multiple clock rates, in th Canadian Conference on Electrical and Computer Engineering (CCECE), pp., IEEE, May 0. [] G. Craig, C. Kime, and K. K. Saluja, Test scheduling and control for VLSI built-in self-test, IEEE Transactions on Computers, vol., no., pp.,. [] C. Yao, K. K. Saluja, and P. Ramanathan, Power and Thermal Constrained Test Scheduling Under Deep Submicron Technologies, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 0, pp., Feb. 0. [0] D. R. Bild, S. Misra, T. Chantemy, P. Kumar, R. P. Dick, X. S. Huy, and A. Choudhary, Temperature-aware test scheduling for multiprocessor systems-on-chip, in IEEE/ACM International Conference on Computer- Aided Design (ICCAD), pp., IEEE, Nov. 00. [] K. Choi, R. Soma, and M. Pedram, Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Trade-Off Based on the Ratio of Off-Chip Access to On-Chip Computation Times, in Proceedings of the conference on Design, automation and test in Europe (DATE), p. 00, Feb. 00. [] J. Park, D. Shin, N. Chang, and M. Pedram, Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors, in ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED), (Austin, TX), pp., 0. [] W. H. Cheng and B. M. Baas, Dynamic voltage and frequency scaling circuits with two supply voltages, in IEEE International Symposium on Circuits and Systems (ISCAS), pp., IEEE, May 00. [] T. Sakurai and A. Newton, Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas, IEEE Journal of Solid-State Circuits, vol., pp., Apr.. [] E. Marinissen, V. Iyengar, and K. Chakrabarty, A set of benchmarks for modular testing of SOCs, in Proceedings of the International Test Conference, (Baltimore, MD), pp., IEEE, Oct. 00. [] V. Iyengar, K. Chakrabarty, and E. Marinissen, Test access mechanism optimization, test scheduling, and tester data volume reduction for system-on-chip, IEEE Transactions on Computers, vol., pp., Dec. 00. [] S. Davidson, ITC Benchmark Circuits - Preliminary Results, in Proceedings of the International Test Conference, pp., Int. Test. Conference,. [] S. K. Millican and K. K. Saluja, Linear Programming Formulations for Thermal-Aware Test Scheduling of D-Stacked Integrated Circuits, in 0 IEEE st Asian Test Symposium, (Niigata, Japan), pp., IEEE, Nov. 0.