Interconnect testing of FPGA

Transcription

1 Center for RC eliable omputing Interconnect Testing of FPGA Stanford CRC March 12, 2001 Problem Statement Detecting all faults in FPGA interconnect resources Wire segments Programmable interconnect points matrices Muxes Application independent test 1 2 Outline Virtex FPGA Model Introduction Previous work Limitations Theoretical aspects Suggested Methods Future Work CLB Mux 3 4 Sparse Pipulation W1 W2 W3 N1 N2 N3 S1 S2 S3 E1 E2 E3 PIP : Programmable Interconnect Point One or path of pass transistors No PIP between each possible pair of pins Each node connectable to all others Proper positioning of PIPs matrix as a connected graph some pairs connected via multiple PIPs Different delays between different pairs + Fewer pass transistors + More density 5 6 Page 1

2 Interconnect Hierarchy of interconnects Single (link each adjacent CLB) Hex (every 3 and 6 CLB) Long (every 6 and 12 CLB) Longer lines are not necessarily slower Fatter Buffered Hierarchy to support speed and density BIST-based methods Comparison-based Parity-based Bus-Based Testing Previous Work 7 8 BIST-based Methods BIST-based Methods Wire Under Test (WUT) Comparison-based techniques [Stroud98] Same test to two groups of WUT Compare the results Parity-based techniques[sun00] TPG generates parity line for k WUTs ORA computes parity for k lines and compares it to original parity line Transparency of logic cells Implement identity function 9 10 Parity-based BIST Bus-based Testing Parity-checker (implemented by a CLB) Configure all wiring segments as long buses [Renovell 00, 98, 97] Bus : Multiple concatenated wires TPG WUTs k WUTs-Parity PCG-Parity Parity Code Generator Comparator ORA P/F At least 3 configurations Orthogonal Diagonal-1 Diagonal-2 Use conventional bus testing approaches Page 2

3 Limitations of Previous Work Theoretical Aspects Too simplistic model of switch matrix connectable pairs table is not regular ON-set Set of all used PIPs in the configuration Almost neglect the hierarchy of interconnect Real implementation issue How to read in and out the WUTs? Limitations in number of s per boundary cell Buffering and clocking long WUTs Lack of at-speed test Disability to detect delay faults OFF-set Set of unused PIPs that are incident with some used PIP at least one end Able to detect stuck-at-off faults of ON-set Causes open fault at line passing through Able to detect stuck-at-on faults of OFF-set Unused lines are driven Causes short between incident lines Example Theoretical Aspects W1 W2 W3 N1 N2 N3 E1 E2 E3 ON-set = {(N2,S2),(N3,S1),(E1,S3), (E3,W3) } OFF-set = {(N2,E2),(N3,S3),(S2,W1), (N1,S1),(E2,W3),(N1,E3), (E1,W1)} Full PIP coverage Detects all stuck-on and stuck-off of all PIPs Enough number of configuration such that Each PIP appears in at least one ON-set Each PIP appears in at least one OFF-set Full PIP coverage full interconnect coverage Some shorts may still remain uncovered Need other configurations to cover S1 S2 S Complete Configuration Each pin of switch matrix is incident to one and only one active PIP All unused PIPs are in OFF-set Corresponds to perfect matching problem matrix as a graph Full PIP coverage = Complete configurations to visit all PIPs + Polynomial time optimized algorithm[west 96] Minimum number of configurations Practical Limitations Need to at-speed testing Number of flip-flops per CLB 4 per each CLB in current FPGAs Limits the width of WUT Number of s per s The same as above Restricted routing from O-Mux to matrix O-Mux : MUX from LE output to switch matrix Page 3

4 Methods Bus Testing Bus testing Wires passing only through switch matrices Scan testing Wires passing through switch matrices, lo muxes, and flip-flops Long concatenation of wires passing through switch matrixes k Bus Testing + No need to pass through logic s + Wider WUTs More PIP coverage per configuration - Very large propagation delay Unable to detect delay faults - Bus width(k1) limited by number of per s Scan Testing Wires passing through switch matrixes and flip flops Register Scan Testing Solution + At-speed testing More compatible with real designs - Narrower WUTs Width limited by number of FFs per CLB Far less than number of compatible PIPs per switch matrix More configurations to cover all PIPs Shifted scan testing Register Page 4

5 Shifted Scan Testing Two categories of configurations Orthogonal for EW, NS PIPs Diagonal for NE,NW, SE,SW PIPs + At-speed testing Able to detect delay faults + More concurrent WUTs Less configurations + Able to detect shorts among different WUTs Future Work Considering -Muxes Configuration generation Algorithm for full PIP coverage Reasonable number of configurations Test Vector generation References [Sun 00] X. Sun, J. Xu, B. Chan, P. Trouborst, Novel Technique for Built-In-Seft Test of FPGA Interconnects, proc. of International Test Conference, 2000 [Renovell 00] M. Renovell, Y. Zorian, Different Experiments in Test Generation for XILINX FPGAs, proc. of International Test Conference, 2000 [Stroud 98] C. Stroud, S. Wijesuriya, C. Hamilton, M. Abramovici, Built-in self -test of FPGA interconnect, International Test Conference, Page(s): , [Renovell 98] M. Renovell, J. M. Portal, J. Figuras, Y. Zorian, Testing the Interconnect of RAM -Based FPGAs, IEEE Design & Test of Computers, Page(s): 45-50, January-March References [Renovell 97] M. Renovell, J. Figuras, Y. Zorian, Test of RAM - Based FPGA: Methodology and Application to the Interconnect, VLSI Test Symposium, Page(s): , [Tavana 97] D. Tavana, FPGA Architecture with Repeatable Tiles Including Routing Matrices and Matrices, Patent US , [West 96] D. B. West, Introduction to Graph Theory, Prentice Hall, Page 5