Update of IEEE P1500 Core Wrapper Architecture
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1 Update of IEEE P1500 rapper Architecture Presented by Lee hetsel on behalf of CTAG orking Group International Conference October 7, 2002
2 Topics - rapper Overview & Applications - rapper Architecture & Instructions - rapper Harness Cells - Summary
3 lock Level Overview of a P1500 rapper User Defined Port for Flexibility rapper Parallel Input PI rapper Parallel Control PC Optional rapper Parallel Port (PP) rapper Parallel Output PO SI rapper Serial Input equired rapper Serial Port (SP) rapper SC rapper Serial Control SO rapper Serial Output Standardized Port for Plug & Play
4 P1500 rapper Configuration Examples User Defined Access Mechanisms (TAM) PI PCPO PI PC PO PI PC PO ENA ENA ENA PP PP PP SI rapper SP rapper SP rapper SP SO SC Standardized Plug&Play rapper Serial Ports
5 P1500 rapper Configuration Examples PC PI Daisychained TAM PO ENA ENA ENA PP PP PP SI rapper SP rapper SP rapper SP SO SC Standardized Plug&Play rapper Serial Ports
6 P1500 rapper Configuration Examples PC PI ussed TAM PO ENA ENA ENA PP PP PP SI rapper SP rapper SP rapper SP SO SC Standardized Plug&Play rapper Serial Ports
7 P1500 rapper Configuration Examples PC PI PO PC PI Direct Access TAM ENA ENA ENA PP PP PP PO PO PC PI SI rapper SP rapper SP rapper SP SO SC Standardized Plug&Play rapper Serial Ports
8 P1500 rapper Configuration Examples Local TAM Controllers Controller Controller Controller ENA ENA ENA PP PP PP SI rapper SP rapper SP rapper SP SO SC Standardized Plug&Play rapper Serial Ports
9 rapper Architecture & Instructions
10 View of the equired P1500 rapper Architecture CTO CTI C Cell C C Cell C CTI CTO Functional Inputs Functional Outputs Functional Outputs Functional Inputs SI 1 ypass 1 I SO Update Shift (ST, CLK, Select, Capture, Shift, Update, Transfer) 7 SC
11 P1500 rapper Instructions * * S_YPASS - equired S_PELOAD - Optional P_PELOAD - Optional _CLAMP - Optional _SAFE - Optional S_INTEST_ ING - Optional S_INTEST_ SCAN - Optional P_INTEST_ ING - Optional P_INTEST_ SCAN - Optional H_INTEST - Optional S_EXTEST - equired P_EXTEST - Optional H_EXTEST - Optional At Least One Optional INTEST is equired * Under consideration as a Standard Optional Intest instruction
12 * * P1500 rapper Instructions Instruction Controlling Port S_YPASS SP S_PELOAD SP P_PELOAD PP _CLAMP SP _SAFE SP S_INTEST_ ING SP S_INTEST_ SCAN SP P_INTEST_ ING PP P_INTEST_ SCAN PP H_INTEST SP and/or PP S_EXTEST SP P_EXTEST SP or PP H_EXTEST SP and/or PP
13 Instruction Field Naming Conventions [ Field 1 ] [ Field 2 ] [ Field 3 ] [ Field 4 ] rapper Access Mode Configuration Serial = S Parallel = P Hybrid = H ypass Preload Clamp Safe Intest Extest User ing Scan User S_Intest_ing
14 rapper Serial ypass (S_ypass) Instruction Enabled Mission Mode Mission Mode Mission Mode Mission Mode SI ypass I SO SP Data Path indicated in Yellow SC S_ypass
15 rapper Serial Preload (S_Preload) Instruction Enabled Mission Mode Mission Mode Mission Mode Mission Mode SI ypass I SO SC S_Preload
16 rapper Parallel Preload (P_Preload) Instruction PC PC signals are User-Defined PO Mission Mode PI PO Mission Mode PI Enabled PI Mission Mode PO PI Mission Mode PO SI PP Data Paths indicated in Green ypass I SC P_Preload SO
17 rapper Clamp (_Clamp) Instruction Inputs may also be controlled to preloaded states Disabled Preloaded States Preloaded States SI ypass I SO _Clamp is preceded by S/P_Preload SC _Clamp
18 rapper Safe (_Safe) Instruction Inputs may also be controlled to safe states Forced Safe States Disabled Forced Safe States SI ypass I SO _Safe does not require S/P_Preload SC _Safe
19 rapper Serial Intest ing (S_Intest_ing) Mode is applied via SC Controlled Scan Path SI ypass I SO SC S_Intest_ing
20 rapper Serial Intest Scan (S_Intest_Scan) Mode is applied via SC Controlled & Internal Scan Path Internal Scan SI ypass I SO SC S_Intest_Scan
21 rapper Parallel Intest ing (P_Intest_ing) Mode is applied via PC Controlled Segments PC PO PI PO PI PI PO PI PO SI Under Consideration as a Standard Instruction ypass I SC SO P_Intest_ing
22 rapper Parallel Intest Scan (P_Intest_Scan) Mode is applied via PC Controlled & Internal Scan Segments PI PC Internal Scan Internal Scan PO PI PO SI Under Consideration as a Standard Instruction ypass I SC SO P_Intest_Scan
23 rapper Hybrid Intest (H_Intest) Mode PC PO PI is applied via SC & PC Controlled Segments Internal Scan PI PO SI ypass I SO SC H_Intest
24 rapper Serial Extest (S_Extest) Mode is applied via SC Controlled Scan Path Disabled UDL UDL UDL UDL SI ypass I SO SC S_Extest
25 rapper Parallel Extest (P_Extest) Mode PO UDL PI PO UDL PI Disabled PI UDL PO PI UDL PO SI is applied via SC Controlled Segments ypass I SC P_Extest SO
26 rapper Parallel Extest (P_Extest) Mode PC PO UDL PI PO UDL PI Disabled PI UDL PO PI UDL PO SI is applied via PC Controlled Segments ypass I SC P_Extest SO
27 rapper Hybrid Extest (H_Extest) Mode PC PO UDL PI Disabled PI UDL PO UDL UDL SI is applied via SC & PC Controlled Segments ypass I SC H_Extest SO
28 rapper Harness Cells
29 Applying rappers to Only Inputs & Outputs educed Functionality Harness Cells Inputs (TI) Outputs (TO) educed Functionality Harness Cells Functional Inputs Functional Outputs Functional Outputs Functional Inputs SI ypass I SO SC
30 PI ENA PI Pass-Through Harness Cells TI TI PC TO TO ENA PO PO Functional Inputs Functional Outputs Functional Outputs Functional Inputs SI ypass I SO SC
31 CTO Scan-Through Harness Cells PC CTI TI TO CTI TI TO CTO Functional Inputs Functional Outputs Functional Outputs Functional Inputs SI ypass I SO SC
32 Pass/Scan-Through Harness Cells PI SO TI PC TO SI PO SI ENA PI TI TO SO PO ENA Functional Inputs Functional Outputs Functional Outputs Functional Inputs SI ypass I SO SC
33 Example Using Pass-Through Harness Cells Pass-Through Harness Cells PI TI PC TO Pass-Through Harness Cells PO SI ypass I SO SC H_Intest
34 Example Using Scan-Through Harness Cells Scan-Through Harness Cells Scan-Through Harness Cells TI TO SI ypass I SO SC S_Intest
35 Example of Pass/Scan Through Cells in Pass Mode Pass/Scan-Through Harness Cells in Pass Mode PI TI PC TO Pass/Scan-Through Harness Cells in Pass Mode PO Enables Factory ing using Parallel Access SI ypass I SO SC P_Intest
36 Example of Pass/Scan Through Cells in Scan Mode Pass/Scan-Through Harness Cells In Scan Mode TI TO Pass/Scan-Through Harness Cells in Scan Mode Enables In-System ing using Serial Access SI ypass I SO SC S_Intest
37 Summary - A Standard rapper has been presented - Its Architecture is Simple and Extendable - Its Serial Port is Plug&Play for Standardized ing - Its Parallel Port is User Defined for Flexibility - Its Instruction Set is ell Defined and Expandable - A Draft is in preparation for allot in early 2003
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