l Some materials from various sources! Soma 1! l Reduce test generation difficulty, especially

Transcription

1 cknowledgements! esign-for-test ethodologies! ani Soma! l Some materials from various sources! n r. hil igh, B! n rinciples of Testing Electronic Systems by S. ourad & Y. Zorian! n Essentials of Electronic Testing by.l. Bushnell and V.. grawal! Soma! Soma 2! Outline! l otivation! l d-hoc techniques! l Structured techniques! l onclusion! otivation! l Reduce test generation difficulty, especially for sequential circuits! l Reduce test cost! l Shorten test development time! l Facilitate testing at system level! n hips to boards to systems! l mprove overall product quality! Soma 3! Soma 4! d-hoc FT Techniques! l nitialization facilities! l Test point insertion and multiplexers! l artitioning large circuits into smaller testable blocks! l onstant-testability designs (-testable designs)! nitialization methods! l nitialization of sequential circuits! n at power-up! n before test application to get to a known initial state! n after an operation to return to a known initial state! n reduce cost of long homing sequences! l synchronous Set, lear, Reset, reset, etc.! Soma 5! Soma 6!

2 Test point insertion! Test point examples! l sually for observation! n critical signals! l ontrol test point breaks signal path! n multiplexers! n additional delays! l nsert based on! n some measures of observability and controllability! n designer s experience! W (a) W (c) 2 W W (b) (d) O Soma 7! Soma 8! Test point examples (3)! Test point examples (2)! l dd internal probe points! n issues in testing and probe card design! ata bus hip nputs ata bus R hip Outputs hip nputs R hip Outputs extra input ata bus R Soma 9! extra output Soma! artitioning for test! artitioning with! l ivide-and-conquer! l Test application to specific blocks! n known available test set! n pseudo-exhaustive test set! G G2 G G2 Origin al ci rcuit Soma! (a) ircui t wit h partitio ning Soma 2!

3 ormal and test modes! seudo-exhaustive test! G G2 G G2 l Subsystems can be tested exhaustively! l oncatenation of test vectors to test several subsystems concurrently! l Sometimes might need partitioning using! (b) ormal mod e (c) Test mode for subcircuit G Soma 3! Soma 4! ircuit example! Test set construction! Test! a! b! c! d! e! f! g! h! x! y!!!!!!!! 2!!!!!!! 3!!!!!!! 4!!!!!!! l (c,d,e): exhaustive test! l f: sensitizes path! l h: propagates to y! 5!!!!!!! 6!!!!!!! 7!!!!!!! 8!!!!!!! Soma 5! Soma 6! Test set construction (2)! Test set construction (3)! Test! a! b! c! d! e! f! g! h! x! y!!!!!!!! 2!!!!!!! 3!!!!!!! 4!!!!!!! 5!!!!!!!!!!! 6!!!!!!!!!!! 7!!!!!!!!!!! l (a,b): exhaustive test! l use rows where h= to sensitize! l g propagates to x! l add two tests (9,) to form (f,h) exhaustive test! Test! a! b! c! d! e! f! g! h! x! y!!!!!!!! 2!!!!!!! 3!!!!!!! 4!!!!!!!!!!! 5!!!!!!!!!!! 6!!!!!!!!!!! 7!!!!!!!!!!! l odify tests (4,9) to form (g,h) exhaustive test! l Total of tests (vs. 64 exhaustive tests)! 8!!!!!!!!!!! 8!!!!!!!!!!! 9!!!!!!! 9!!!!!!!!!!!!!!!!!!!!!!!!! Soma 7! Soma 8!

4 -testable designs! L structures! l terative Logic rrays (L)! n structured designs using arrays of identical cells! Ø adders, multipliers, etc.! Ø R! Ø FG! Ø bit-slice processors! l rray test set based on cell test set! n -testable: array test set size is independent of number of cells in array! i- i i+ -dimensional i,j 2-dimensional Soma 9! Soma 2! Full adder example! i Yi o i i+ i i- i! Yi! i! o! Si!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! Si l 6 tests with identical carry values! l 2 alternate-cell tests with opposite carry values! l total = 8 tests! Soma 2! Structured FT Techniques! l dominates digital FT! n lassical scan! n Boundary scan! l design guidelines! l Built-in Self Test (BST) techniques! n in other lectures! Soma 22! concept! LSS system diagram! 2 3 ombinational circuit Z Z2 Z3 Y[..3] (in) omb. network L L2 Z(out) SO LK 2 3 ombinational circuit Z Z2 Z3 L L2 scan path y[..3] feedback S SE LK SO SKB K SK S L L2 Soma 23! Soma 24!

5 latch design example! Typical scan chains! =L S S2 S3 S4 S5 S6 S7 2=L2=SO K S SK SKB S: scan data in! SK, SKB: scan s! SO: scan data out! primary inputs primary outputs : normal data in! K: system! : normal latch output! Soma 25! SO SO2 SO3 SO4 SO5 SO6 SO7 Soma 26! testing! Typical scan chain tests! l onfigure FF into shift register and test! l Generate tests for combinational logic! l pply tests using scan FF to provide /O to combinational logic! n easier and faster justification! n easier and faster propagation! Soma 27! l nitialization! l Flush / Flush patterns of all chains in parallel! l in and scan out same data, all chains in parallel! l pply a test (loop for each test vector)! n scan in test (contents of FF)! n set up inputs (combinational logic inputs for test )! n exercise system once! n scan out contents of FF! n check scan outputs! Soma 28! -O delay test with scan! L2-O delay test with scan! stim stim 2 system/scan 2 system/scan system system O strobe O strobe Soma 29! Soma 3!

6 stim 2 system/scan system O strobe L2-L delay test with scan! design rules! l ll latches must be scannable (full-scan)! l Every latch must be on a scan path! n There may be multiple scan paths! l on-overlapping s! l o gating between s! l ll s must be primary inputs! l S and SO must be primary /O! Soma 3! Soma 32! design advantages! l Testable sequential systems! n Test scan path using FF tests! l Ease of testing remaining combinational logic! n ccess to internal nodes via scan! l Fast test generation (all combinational)! l Ease of delay testing of combinational blocks! design advantages (2)! l omplete controllability of all registers! l omplete observability of all registers! l ombinational logic test generation! l se cheaper test systems! l dditional diagnostic capability! Soma 33! Soma 34! design cost! TG Example: S5378! l ore complex design! n area: 2-5%! l dditional delay! n ossible to minimize by clever designs! l ore /O required (-3 pins)! n Recover cost as part of system test facilities! l Slow test (not at speed)! n Time to scan long paths serially! n Larger wiring parasitics! umber of combinational gates umber of non-scan flip-flops ( gates each) umber of scan flip-flops (4 gates each) Gate overhead umber of faults /O for TG Fault coverage Fault efficiency time on S ltra, 2z processor umber of TG vectors sequence length Original 2,78 79.% 4,63 35/49 7.% 7.9% 5,533 s Full-scan 2, % 4,63 24/ %.% 5 s 585 5,662 Soma 35! Soma 36!

7 varieties! l Full-scan: increasing use! n partitioning issues in multiple scan chains! n optimal placement of FF in scan chain! l artial-scan! l Random-access scan! n ndividual latch addressable! n igh overhead! l Level-Sensitive esign! n o races and timing problems! artial Example! l ircuit: TL, 355 gates, 2 flip-flops! ax. cycle epth* TG Fault sim. Fault TG Test seq. flip-flops length s s cov. vectors length 4 4, % % 247, % 36, % 2, % 52,9 * yclic paths ignored Soma 37! Soma 38! Test Length Statistics! artial vs. Full : S5378! l ircuit: TL! 2 Original artial-scan Full-scan umber of faults umber of faults umber of faults 2 2 Without scan Test length 9 scan flip-flops scan flip-flops Test length Test length umber of combinational gates umber of non-scan flip-flops ( gates each) umber of scan flip-flops (4 gates each) Gate overhead umber of faults /O for TG Fault coverage Fault efficiency time on S ltra 2z processor umber of TG vectors sequence length 2,78 79.% 4,63 35/49 7.% 7.9% 5,533 s , % 4,63 65/ % 99.5% 727 s,7 34,69 2, % 4,63 24/ %.% 5 s 585 5,662 Soma 39! Soma 4! otivation for board test! Bed-of-nails testing! l igh-density boards / ultichip odules () not testable using bed-of-nails! l Board failure modes:! n stuck-at faults! n open! n shorts! n incorrect components! l Lack of test access! robe Spring Socket Wire-Wrap onnection Bed - of - ails Fixture nit under Test Soma 4! Soma 42!

8 Boundary standard! Boundary topology! l EEE 49.! n JTG (Joint Test ctivity Group)! l First release: 99! n under revisions! l Facilities to test for board failures! n optional instructions for internal testing! n usable in system-level tests! l any s now incorporate 49.! T ata_in ata_out BS internal logic internal logic TO T T internal logic internal logic internal logic T T T TO TO TS TK T TO TS TK T Soma 43! Soma 44! Boundary cell! Test access port (T)! ata_n T TO ata_out 2 ode ShiftR pdate R lockr l t chip /O only! l Electronic access to each chip pin! T Boundary Registers evice. Register Bypass Register nstruction Register (R) ontroller TO l TS! l TK! l T! l TO! l optional TRST (reset)! Soma 45! T TK Soma 46! T registers! T controller! l Bypass register! n removes chip from boundary scan path! n faster test application! l nstruction register! n mandatory instruction: Bypass, Extest, Sample / reload! n optional instruction: ntest, dcode, RunBist, lamp, ighz! Test-Logic- Reset Run-Test/ Select- dle R- apture-r Shift - R Exit - R ause - R Exit2-R pdate-r Select- R- apture - R Shift - R Exit - R ause - R Exit2 - R pdate - R l Simple state machine! l Load instruction! l Load test data! l Execute test! l nload (shift-out) test results! l nitialization! Soma 47! Soma 48!

9 Register operations! nstruction scan! l nstruction registers! n loaded serially for all s! n captured in parallel to each! l ata registers at chip pins! n loaded serially, captured in parallel! n test data and test results! TK TS ontroller State T ata input to R R shiftregister arallel output of R ata input to TR TR shiftregister Test-Logic- Reset Run-Test/ dle Select-R-- Select-R-- apture-r Shift-R Exit-R OE ause-r Exit2-R Shift-R Exit-R pdate-r Run-Test/ dle ew nstruction arallel output of TR Old data Register selected nstruction register TO enable nactive ctive nactive ctive nactive TO Soma 49! Soma 5! ata scan! ETEST example ()! TK TS ontroller State T ata input to R Run-Test/ dle apture-r Shift-R Exit-R ause-r Exit2-R Shift-R Exit-R pdate-r Run-Test/ dle Select-R- Select-R- Select-R- Test-Logic- Reset ata_n ata_n TO ata_out nternal Logic T Serial_n T Serial_n lock Serial_Out Shift/Load TO ata_out (a) lock Shift/Load Serial_Out R shiftregister arallel output of R ata input to TR TR shiftregister arallel output of TR nstruction Register nstruction Old data Test data register ew data OE (b) ata_n nternal Logic ata_n T Serial_n T Serial_n lock Serial_Out Shift/Load TO ata_out TO ata_out lock Shift/Load Serial_Out TO enable nactive ctive nactive ctive nactive TO Soma 5! Soma 52! ETEST example (2)! ata_n nternal Logic ata_n (b) T Serial_n T Serial_n lock Serial_Out Shift/Load TO ata_out ata_n nternal Logic ata_n 2 (c) T Serial_n T Serial_n lock Serial_Out Shift/Load TO ata_out TO ata_out lock Shift/Load Serial_Out TO ata_out lock Shift/Load Serial_Out Boundary design tools! l Boundary esign Language! n BSL! n facilitates incorporation and checking of correct BS designs! l utomatic synthesis of T controller! l Tools and automatic test generation available in most systems! n supported by numerous testers! Soma 53! Soma 54!

10 Boundary tradeoffs! l dditional pins (at least 4)! l dditional delays (minimal)! l dditional power (minimal)! l Structured FT technique for board test! n extensible to internal test (private instructions and proprietary FT methods)! n test access from system to pins! n computer-aided tools available! n usable for debug and diagnosis! design guidelines! l Structured FT methodology! l Built-in current sensor(bs)! n ircuit designs! n Test point selection: where to insert BS! l Fully static logic for low! l o pull-ups, pull-downs, pass gates! l o internal drive conflicts! l o floating nodes! Soma 55! Soma 56! l dvantages! Built-n urrent Sensors! n testing can be applied only for all non-analog circuitry on mixed-signal chips! n Better low-current resolution (e.g. partition chip)! n uch faster (e.g. four orders of magnitude)! l otential pplications! n igher quality chip testing! n testing at multiple levels of assembly! n ircuit breaker & cheap chip test for wafer-level burn-in! n ower-on, diagnostic or concurrent testing in system! n Reconfigurable systems! Built-n urrent Testing! l esigns have been experimentally verified (2)! n arnegie ellon, ewlett-ackard, otorola, Japanese niversities, uburn, a few others! Ø Speed: up to 2z! Ø Low current resolution: <u! Ø rea overhead: <%! Ø ircuit size: 2 transistors! l pparently, not yet implemented in manufacturing! l Long-term feasibility & effectiveness is not clear! Soma 57! Soma 58! FT examples! l dd pins for observability/controllability! l dd internal probe points! l Latch design with reset capability! l latch design (including level-sensitive scan design)! l Boundary scan on signal O pins! l esign for reduced pin count testing! l Layout modification for defect tolerance / avoidance! l Logical design modification to defect tolerance / FT examples (2)! l arity, error detection, error correction! l Built-in self test of logic! l esign for zero static current! l nclusion of electrostatic discharge (ES) diodes on all O pins! l emory redundancy! l emory built-in self-test! avoidance! Soma 59! Soma 6!

11 FT rules of thumb! l f possible, use full scan design! l se JTG 49. boundary scan for open market parts! l mplement full q testable designs! l void logical redundancy! l For sequential designs, try to avoid sequential feedback loops (e.g. large counters)! l For sequential designs, include reset operation on all latches! l se memory BST for large memories! FT rules of thumb (2)! l nclude ES protection diodes! l For scan designs, minimize length of longest scan chain! l nderstand all testing requirements (e.g. board vs. ) when defining chip-level test strategies! Soma 6! Soma 62! onclusion! l FT is unavoidable at system level! l Balance design and test tradeoffs! l Structured vs. ad-hoc FT! l Systems-on-a-chip (SO) FT:! n FT per core (in core-based designs)! n test integration issues! n core interface test! n mixed-signal FT issues! Soma 63!