Day 1 : Tuesday, 31st October 2017 (Tutorial) Vanue: Centre for Advanced and Professional Education (CAPE), Universiti Teknologi PETRONAS (UTP)

Transcription

1 Day 1 : Tuesday, 31st October 2017 (Tutorial) Vanue: Centre for Advanced and Professional Education (CAPE), Universiti Teknologi PETRONAS (UTP) Time Start Time End Venue: 8:00 9:00 Registration 9:00 17:00 Tutorial 1: Design Automation, Test, Error Recovery: Toward Secure, Dependable, and Adaptive Large-Scale Lab-on-Chip (LOC) Systems by Professor Dr Tsung-Yi Ho (National Tsing Hua University, Taiwan) Tutorial 2: CMOS SPICE Model Extraction for Analog Integrated Circuit Design by Dr. Philip Tan Beow Yew (Senior Manager of Device Modeling)

2 Day 2 : Wednesday, 1 November 2017 Vanue: Pullman Kuala Lumpur Bangsar Time Time Start End Track A: Studio 1 Track B: Studio 2 8:00 8:30 Registration 8:30 8:40 Welcoming Remarks Day 1 8:40 9:40 9:40 10:40 Keynote 1: Ultra-low voltage and micro-power analog design by Professor Franco Maloberti (President IEEE CAS Society, University of Pavia, Italy) Keynote 2: Keynote 2: The Coming of Age of Microfluidics: Connecting Algorithms and Foundations of Chip Design to Biochemistry and the Life Sciences by Professor Dr Tsung-Yi Ho (National Tsing Hua University, Taiwan) 10:40 10:50 World Best Chapter Award & Photo Session 10:50 11:00 Break 11:00 11: Analog Signal Path Circuit for a Four Transistor Pixel in Standard 0.13Micron CMOS 11:20 11:40 11:40 12:00 12:00 12:20 12:20 12:40 12:40 13: Fabrication of Fluidic-Based Memristor Sensor for Dengue Virus Detection Timing Generator for 120fps CMOS Image Sensors on 0.13μm CMOS Sensitivity of Piezoresistive Pressure Sensor with Inner Diaphragm Joule Heating Effects on Microdroplet in Flexible Electrowetting Chip Analysis of Dielectrophoresis AC Electrokinetic in Equilibrium Using Matlab Low Transient Voltage Dual Loop Buck Converter Using Digital Charge Control Technique A Variable Duty Cycle Pulse Train Charger for Improving Lead-Acid Battery Performance Design and Implementation of a High Efficiency Cost Effective EV Charger Using LLC Resonant Converter Transient Performance Estimation of DLDO by Building Model in MATLAB Simulink Spread of Chaotic Behavior in Scalefree and Random Networks Frustrated Coupled Oscillators with Anomalous Coupling Method 13:00 14:00 Lunch 14:00 15:00 Keynote 3: How Far SPICE Modeling Can Go In Capturing Future Advance Device Characteristics by Dr. Philip Tan Beow Yew (Senior Manager of Device Modeling Silterra Malaysia Sdn. Bhd. Foundry) 15:00 15:20 Break

3 15:20 15:40 15:40 16:00 16:00 16:20 16:20 16: Image Processing by Cellular Neural Networks with Switching Two Templates Multi-level Memristive Memory with Resistive Networks Moderate Traumatic Brain Injury Identification for MEG Data Using PU Learning Technique LED Lighting with Remote Monitoring and Controlling System for Indoor Greenhouse 16:40 17:00 Break Multi-Node Threshold Voltage Compensation Rectifier for Near-Field RF Energy Harvesting Applications A CMOS 180nm Class-AB Power Amplifier with Intergrated Passive Linearizer for BLE 4.0 Achieving 11.5dB Gain, 38.4% PAE and 20dBm OIP A Single Chip 2.4GHz Quadrature LNA-IQ Mixer in 180nm CMOS Intergrated Class C -VCO - Mixer for 2.45GHz Transmitter in 180nm CMOS

4 Day 3 : Thursday, 2nd November 2017 Vanue: Pullman Kuala Lumpur Bangsar Time Time Start End Track A: Studio 1 Track B: Studio 2 8:00 8:30 Registration 8:30 8:40 Welcoming Remarks 8:40 9:40 Keynote 4: Energy-Quality Scalable Integrated Circuits and Systems Continuing the Energy Scaling in spite of Moore s Law by Assoc Prof Dr Massimo Alioto (National University of Singapore, Singapore) 9:40 10:40 Keynote 5: Test and Reliability Challenges for the Internet of Things in the Interconnected World by Assoc Prof Dr Fawnizu Azmadi Bin Hussin (Director, Strategic Alliance Office, Universiti Teknologi PETRONAS, Malaysia) 10:40 11:00 Break 11:00 11:20 11:20 11:40 11:40 12:00 12:00 12:20 12:20 12:40 12:40 13: An Efficient Residue-to-Binary Converter for a Three Moduli Set Optimised Completion Detection Circuits for Null Convention Logic Pipelines xVDD Digital Output Buffer Insensitive to Process and Voltage Variations Area-Efficient CMOS Implementation of NCL Gates for XOR-AND/OR Dominated Circuits Robust IoT Communication Physical Layer Concept with Improved Physical Unclonable Function Generating Power-optimal Standard Cell Library Specification Using Neural Network Technique A Gain Boosting Single Stage Cascode LNA for Millimeter-wave Applications Design and Simulation of a Low- Power 0.18 Μm CMOS MedRadio Band LNA UWB CMOS Low Noise Amplifier for Mode Switching Power Control for Multimode Multiband Power Amplifier Deriving Voltage Gain Transfer Functions Without KVL/KCL Using Trajectance Analysis Stagger Tuning for BW Extension in Transimpedance Amplifiers 13:00 14:00 Lunch 14:00 15:30 Special Session with IEEE Journal Editors: Franco, Yoshifumi & Alioto 15:30 15:50 Break

5 15:50 16:10 16:10 16:30 16:30 16:50 16:50 17: Electrical Characterization of GO at Different ph Towards MCF7 and MCF10a-Preliminary Result Preliminary Results of Electrical Characterization of GO Towards MCF7 and MCF10a at Different Concentrations Proposing a Novel Enhanced Approach of Threshold Voltage Extraction for Nano MOSFET THz Radiation in Graphene Based on Quasi-Ballistic Electron Reflection Enhancing Magnetic IEDs Detection Method Utilizes an AMR-based Magnetic Field Sensor Virtualization Detection Strategies and Their Outcomes in Public Clouds Effects of Frequency and Voltage on the Output of CMOS-MEMS Device A 2.5-GS/S 8-Bit 0.56-fJ/Conv-Step in 45-nm CMOS SAR-ADC Using a Novel Charge-Shared Back Feeding Dynamic Comparator 17:10 17:30 Best Papers Award & Travel Award, Closing Ceremony