OBSOLETE AD8392. Low Power, High Output Current, Quad Op Amp, Dual-Channel ADSL/ADSL2+ Line Driver PIN CONFIGURATIONS FEATURES APPLICATIONS

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1 FEATURES Four current feedback, high current amplifiers Ideal for use as ADSL/ADSL+ dual-channel Central Office (CO) line drivers Low power operation Power supply operation from ± V (+ V) up to ± V (+4 V) Less than 3 ma/amp quiescent supply current for full power ADSL/ADSL+ CO applications (.4 dbm line power,. CF) Three active power modes plus shutdown High output voltage and current drive 4 ma peak output drive current 44 V p-p differential output voltage Low distortion 7 MHz second harmonic 8 MHz third harmonic High speed: 9 V/µs differential slew rate Additional functionality of AD839ACP On-chip common-mode voltage generation APPLICATIONS ADSL/ADSL+ CO line drivers XDSL line drives High output current, low distortion amplifiers DAC output buffer GENERAL DESCRIPTION The AD839 is comprised of four high output current, low power consumption, operational amplifiers. It is particularly well suited for the CO driver interface in digital subscriber line systems, such as ADSL and ADSL+. The driver is capable of providing enough power to deliver.4 dbm to a line, while compensating for losses due to hybrid insertion and back termination resistors. In addition, the low distortion, fast slew rate, and high output current capability make the AD839 ideal for many other applications, including medical instrumentation, DAC output drivers, and other high peak current circuits. The AD839 is available in two thermally enhanced packages, a 8-lead TSSOP/EP (AD839ARE) and a mm mm 3-lead LFCSP (AD839ACP). Four bias modes are available via the use of two digital bits (PD, PD). Low Power, High Output Current, Quad Op Amp, Dual-Channel ADSL/ADSL+ Line Driver V EE PD, PD, 3 +V IN 4 V IN V OUT 6 V CC 7 NC 8 V OUT 3 9 V IN 3 +V IN 3 NC NC 3 GND 4 NC V IN V OUT V CC NC V OUT 3 V IN 3 NC PIN CONFIGURATIONS 3 AD839 4 NC = NO CONNECT 8 GND 7 NC 6 NC +V IN 4 V IN 3 V OUT NC V CC V OUT 4 9 V IN 4 8 +V IN 4 7 PD 3, 4 6 PD 3, 4 V EE Figure. AD839ARE, 8-Lead TSSOP/EP V IN PD, PD, V EE GND NC = NO CONNECT V COM, NC +V IN NC 3 V IN V OUT AD839 NC V CC V OUT 4 V IN 4 NC V IN 3 NC V COM 3, 4 GND V EE PD 3, 4 PD 3, 4 +V IN 4 Figure. AD839ACP, 3-Lead LFCSP mm mm AD839 Additionally, the AD839ACP provides VCOM pins for on-chip common mode voltage generation. The low power consumption, high output current, high output voltage swing, and robust thermal packaging enable the AD839 to be used as the CO line drivers in ADSL and other xdsl systems, as well as other high current, single-ended or differential amplifier applications Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Specifications... 3 Absolute Maximum Ratings... Thermal Resistance... Power Management... Driving Capacitive Loads... Thermal Considerations... 3 ESD Caution... Typical Performance Characteristics... 6 Theory of Operation... Applications... Supplies, Grounding, and Layout... Resistor Selection... REVISION HISTORY 3/ Rev. to Rev. A Changes to Figure and Figure... Changes to Ordering Guide /4 Revision : Initial Version Typical ADSL/ADSL+ Application... 3 Multitone Power Ratio... 4 Lightning and AC Power Fault... Outline Dimensions... 6 Ordering Guide... 6 Rev. A Page of 6

3 SPECIFICATIONS VS = ± V or +4 V, RL = Ω, G = +, PD = (, ), T = C, unless otherwise noted. Table. Parameter Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE 3 db Small Signal Bandwidth 3 4 MHz VOUT =. V p-p, RF = kω 3 db Large Signal Bandwidth MHz VOUT = 4 V p-p, RF = kω Peaking. db VOUT =. V p-p, RF = kω Slew Rate 8 9 V/µs VOUT = V p-p, RF = kω NOISE/DISTORTION PERFORMANCE Second Harmonic Distortion 7 dbc fc = MHz, VOUT = V p-p Third Harmonic Distortion 8 dbc fc = MHz, VOUT = V p-p Multitone Input Power Ratio 7 dbc 6 khz to. MHz, ZLINE = Ω Differential Load Voltage Noise (RTI) 4.3 nv/ Hz f = khz +Input Current Noise pa/ Hz f = khz Input Current Noise 3 pa/ Hz f = khz INPUT CHARACTERISTICS RTI Offset Voltage. ±3. +. mv V+IN V IN +Input Bias Current.. µa Input Bias Current.. µa Input Resistance 4 kω Input Capacitance. pf Common-Mode Rejection Ratio db ( VOS, DM (RTI))/( VIN, CM) OUTPUT CHARACTERISTICS Differential Output Voltage Swing V VOUT Single-Ended Output Voltage Swing.. 3. V VOUT Linear Output Current 4 ma RL = Ω, fc = khz POWER SUPPLY Operating Range (Dual Supply) ± ± V Operating Range (Single Supply) 4 V Total Quiescent Current PD, PD = (, ) ma/amp PD, PD = (, ) ma/amp PD, PD = (, ) ma/amp PD, PD = (, ) (Shutdown State).4. ma/amp PD = Threshold.8 V PD = Threshold.8 V +Power Supply Rejection Ratio db VOS, DM (RTI)/ VCC, VCC = ± V Power Supply Rejection Ratio db VOS, DM (RTI)/ VEE, VEE = ± V AD839 Rev. A Page 3 of 6

4 VS = ± V or + V, RL = Ω, G = +, PD = (, ), T = C, unless otherwise noted. Table. Parameter Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE 3 db Small Signal Bandwidth 3 4 MHz VOUT =. V p-p, RF = kω 3 db Large signal Bandwidth MHz VOUT = 4 V p-p, RF = kω Peaking. db VOUT =. V p-p, RF = kω Slew Rate (Rise) 3 3 V/µs VOUT = 7 V p-p, RF = kω Slew Rate (Fall) 4 4 V/µs VOUT = 7 V p-p, RF = kω NOISE/DISTORTION PERFORMANCE Second Harmonic Distortion 7 dbc fc = MHz, VOUT = V p-p Third Harmonic Distortion 8 dbc fc = MHz, VOUT = V p-p Voltage Noise (RTI) 4.3 nv/ Hz f = khz +Input Current Noise pa/ Hz f = khz Input Current Noise 3 pa/ Hz f = khz INPUT CHARACTERISTICS RTI Offset Voltage. ±3. +. mv V+IN V IN +Input Bias Current.. µa Input Bias Current.. µa Input Resistance 4 kω Input Capacitance. pf Common-Mode Rejection Ratio 6 66 db ( VOS, DM (RTI))/( VIN, CM) OUTPUT CHARACTERISTICS Differential Output Voltage Swing V VOUT Single-Ended Output Voltage Swing V VOUT Linear Output Current 4 ma RL = Ω, fc = khz POWER SUPPLY Operating Range (Dual Supply) ± ± V Operating Range (Single Supply) + +4 V Total Quiescent Current PD, PD = (, ).4 6. ma/amp PD, PD = (, ) ma/amp PD, PD = (, ).6 3. ma/amp PD, PD = (, ) (Shutdown State).4. ma/amp PD = Threshold.8 V PD = Threshold.8 V +Power Supply Rejection Ratio 7 76 db VOS, DM (RTI)/ VCC, VCC = ± V Power Supply Rejection Ratio db VOS, DM (RTI)/ VEE, VEE = ± V Rev. A Page 4 of 6

5 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Supply Voltage ±3 V (+6 V) Power Dissipation See Figure 3 Storage Temperature 6 C to + C Operating Temperature Range 4 C to +8 C Lead Temperature Range (Soldering sec) 3 C Junction Temperature C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θja is specified for the worst-case conditions, i.e., θja is specified for device soldered in circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type θja Unit LFCSP-3 (CP) 7.7 C/W TSSOP-8/EP (RE) 3.33 C/W Maximum Power Dissipation The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming that the load (RL) is midsupply, the total drive power is VS/ IOUT, some of which is dissipated in the package and some in the load (VOUT IOUT). RMS output voltages should be considered. If RL is referenced to VS as in single-supply operation, the total power is VS IOUT. In single supply with RL to VS, worst case is VOUT = VS/. Airflow increases heat dissipation, effectively reducing θja. Also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the θja. Figure 3 shows the maximum safe power dissipation in the package versus the ambient temperature for the LFCSP-3 and TSSOP-8/EP packages on a JEDEC standard 4-layer board. θja values are approximations. MAXIMUM POWER DISSIPATION (W) TSSOP-8/EP LFCSP TEMPERATURE ( C) T J = C Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board See the Thermal Considerations section for additional thermal design guidance. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality Rev. A Page of 6

6 TYPICAL PERFORMANCE CHARACTERISTICS MULTITONE POWER RATIO (dbc) HARMONIC DISTORTION (dbc) HARMONIC DISTORTION (dbc) PD (, ) PD (, ) PD (, ) CREST FACTOR = OUTPUT POWER (dbm) Figure 4. MTPR vs. Output Power (.7 MHz Empty Bin) ADSL/ADSL+ Circuit (Figure 3) VS = ± V, RLOAD = Ω, CF =.4 HD PD (, ) HD3 PD (, ) HD PD (, ) HD PD (, ) HD3 PD (, ) HD3 PD (, ) Figure. Harmonic Distortion vs. Frequency Dual Differential Driver Circuit (Figure 3) VS = ± V, RLOAD = Ω, G = +, VOUT = V p-p HD PD (, ) HD3 PD (, ) HD PD (, ) HD PD (, ) HD3 PD (, ) HD3 PD (, ) POWER CONSUMPTION (mw) HARMONIC DISTORTION (dbc) HARMONIC DISTORTION (dbc) CREST FACTOR =.4 PD (, ) PD (, ) PD (, ) OUTPUT POWER (dbm) Figure 7. Power Consumption vs. Output Power (6 khz to. MHz) ADSL/ADSL+ Circuit (Figure 3) VS = ± V, RLOAD = Ω, CF = HD PD (, ) HD3 PD (, ) HD PD (, ) HD PD (, ) HD3 PD (, ) HD3 PD (, ) Figure 8. Harmonic Distortion vs. Frequency Dual Differential Driver Circuit (Figure 3) VS = ± V, RLOAD = Ω, G = +, VOUT = V p-p 9 HD3 PD (, ) HD PD (, ) HD PD (, ) HD PD (, ) HD3 PD (, ) HD3 PD (, ) Figure 6. Harmonic Distortion vs. Frequency VS = ± V, RLOAD = Ω, G = +, VOUT = V p-p Figure 9. Harmonic Distortion vs. Frequency VS = ± V, RLOAD = Ω, G = +, VOUT = V p-p Rev. A Page 6 of 6

7 PD (, ) PD (, ) GAIN (db) PD (, ) GAIN (db) PD (, ) GAIN (db) GAIN (db) PD (, ). Figure. Small Signal Frequency Response VS = ± V, RLOAD = Ω, G = +, VOUT = mv p-p Ω 4.7Ω Ω 7Ω Ω Ω Ω. Figure. Small Signal Frequency Response vs. Load VS = ± V, G = +, VOUT = mv p-p PD (, ) PD (, ) SIGNAL FEEDTHROUGH (db) PD (, ) Figure 3. Small Signal Frequency Response VS = ± V, RLOAD = Ω, G = +, VOUT = mv p-p. Figure 4. Signal Feedthrough vs. Frequency VS = ± V, G = +, VIN = 8 mv p-p, PD (, ) GAIN (db) PD (, ) PD (, ) PD (, ) PD (, ) Figure. Large Signal Frequency Response VS = ± V, RLOAD = Ω, G = +, VOUT = 4 V p-p Figure. Large Signal Frequency Response VS = ± V, RLOAD = Ω, G = +, VOUT = 4 V p-p Rev. A Page 7 of 6

8 OUTPUT VOLTAGE (V) TIME (µs) Figure 6. Small Signal Pulse Response VS = ± V, RLOAD = Ω, G = +, mv Step OUTPUT PD PINS B B CH mvω W CH.mVΩ W M.ns A CH.38V Figure 7. Power-Up Time: PD (, ) to PD (, ) VS = ± V, RLOAD = Ω, G = +, VOUT = V p-p INPUT OUTPUT : C p-p 7.V C p-p.4v CH.VΩ CH.VΩ M.µs CH 7mV OUTPUT VOLTAGE (V) TIME (µs) Figure 9. Large Signal Pulse Response VS = ± V, RLOAD = Ω, G = +, 4 V Step PD PINS OUTPUT CH mvω B W CH.VΩ B W M 4ns CH.38V Figure. Power-Down Time: PD (, ) to PD (, ) VS = ± V, RLOAD = Ω, G = +, VOUT = V p-p INPUT OUTPUT : C p-p 6.V C p-p.8v CH.VΩ CH.VΩ M.µs CH 8mV Figure 8. Input Overdrive Recovery VS = ± V, RLOAD = Ω, G = +, VIN = 7 V p-p Figure. Output Overdrive Recovery VS = ± V, RLOAD = Ω, G = +, VIN = 6 V p-p Rev. A Page 8 of 6

9 CROSSTALK (db) CROSSTALK (db) VOLTAGE NOISE (nv/ Hz) ADSL CHANNEL 3, 4 ADSL CHANNEL, Figure. Crosstalk vs. Frequency ADSL/ADSL+ Circuit (Figure 3) VS = ± V, G = +, RLOAD = Ω, VIN = mv p-p CHANNEL CHANNEL CHANNEL 3 CHANNEL 4 Figure 3. Crosstalk vs. Frequency VS = ± V, G = +, RLOAD = Ω, VIN = mv p-p CROSSTALK (db) DIFFERENTIAL OUTPUT SWING (V) DIFF CHANNEL 3, 4 DIFF CHANNEL, Figure. Crosstalk vs. Frequency Dual Differential Driver Circuit (Figure 3) VS = ± V, G = +, RLOAD = Ω, VIN = mv p-p RESISTIVE LOAD (Ω) V S = ±V V S = ±V Figure 6. Differential Output Swing vs. RLOAD ADSL/ADSL+ Circuit (Figure 3) G = + CURRENT NOISE (pa/ Hz) +I NOISE I NOISE FREQUENCY (khz) FREQUENCY (khz) Figure 4. Voltage Noise vs. Frequency Figure 7. Current Noise vs. Frequency Rev. A Page 9 of 6

10 TRANSIMPEDANCE (Ω) G M PHASE M M TRANSIMPEDANCE k k k k k k M M M G FREQUENCY (Hz) Figure 8. Open-Loop Transimpedance and Phase nf 49.9Ω 499Ω Ω kω Figure 9. Quad Op Amp Circuit nf 49.9Ω kω nf 49.9Ω kω kω Ω Figure 3. Dual Differential Driver Circuit PHASE (Degrees) OUTPUT IMPEDANCE (Ω).... nf V CM nf PD (, ) PD (, ) PD (, ) Figure 3. Output Impedance vs. Frequency VS = ± V, G = +, PD (, ) 866Ω 6Ω 6Ω 866Ω 6Ω kω nf kω 8kΩ 8kΩ 6.9Ω 6.9Ω Figure 3. ADSL/ADSL+ Circuit Ω Rev. A Page of 6

11 THEORY OF OPERATION The AD839 is a current feedback amplifier with high (4 ma) output current capability. With a current feedback amplifier, the current into the inverting input is the feedback signal, and the open-loop behavior is that of a transimpedance, dvo/diin or TZ. The open-loop transimpedance is analogous to the open-loop voltage gain of a voltage feedback amplifier. Figure 33 shows a simplified model of a current feedback amplifier. Since RIN is proportional to /gm, the equivalent voltage gain is just TZ gm, where gm is the transconductance of the input stage. Basic analysis of the follower with gain circuit yields V V where: O IN G = + R TZ ( S) = G T ( S) + G RIN + RF R R F G IN = m Z Ω g Since G RIN << RF for low gains, a current feedback amplifier has relatively constant bandwidth versus gain, the 3 db point being set when TZ = RF. AD839 Of course, for a real amplifier there are additional poles that contribute excess phase, and there is a value for RF below which the amplifier is unstable. Tolerance for peaking and desired flatness determines the optimum RF in each application. V IN R G R N R IN I IN R F T Z Figure 33. Simplified Block Diagram V OUT The AD839 is capable of delivering 4 ma of output current while swinging to within V of either power supply rail. The AD839 also has a power management system included on-chip. It features four user-programmable power levels (three active power modes as well as the provision for complete shutdown) Rev. A Page of 6

12 APPLICATIONS SUPPLIES, GROUNDING, AND LAYOUT The AD839 can be powered from either single or dual supplies, with the total supply voltage ranging from V to 4 V. For optimum performance, a well regulated low ripple supply should be used. As with all high speed amplifiers, close attention should be paid to supply decoupling, grounding, and overall board layout. Low frequency supply decoupling should be provided with µf tantalum capacitors from each supply to ground. In addition, all supply pins should be decoupled with. µf quality ceramic chip capacitors placed as close as possible to the driver. An internal low impedance ground plane should be used to provide a common ground point for all driver and decoupling capacitor ground requirements. Whenever possible, separate ground planes should be used for analog and digital circuitry. High speed layout techniques should be followed to minimize parasitic capacitance around the inverting inputs. Some practical examples of these techniques are keeping feedback traces as short as possible and clearing away ground plane in the area of the inverting inputs. Input and output traces should be kept short and as far apart from each other as practical to avoid crosstalk. When used as a differential driver, all differential signal traces should be kept as symmetrical as possible. RESISTOR SELECTION In current feedback amplifiers, selection of feedback and gain resistors can impact harmonic distortion performance, bandwidth, and gain flatness. Care should be exercised in the selection of these resistors so that optimum performance is achieved. Table shows some suggested resistor values for use in a variety of gain settings. These values are suggested as a good starting point when designing for any application. Table. Resistor Selection Guide Gain RF RG.k Open.k.k.k POWER MANAGEMENT The AD839 can be configured in any of three active bias states as well as a shutdown state via the use of two sets of digitally programmable logic pins. Pins PD(, ), control Amplifiers and, while PD(, ) 3, 4 control Amplifiers 3 and 4. These pins can be controlled directly with either 3.3 V or V CMOS logic by using the GND pins as a reference. If left unconnected, the PD pins float low, placing the amplifier in the full bias mode. Refer to the Specifications for the per amplifier quiescent current for each of the available bias states. The AD839 exhibits low output impedance for the three active states. However, the output impedance in the shutdown state (PD, =, ) is undefined. DRIVING CAPACITIVE LOADS When driving a capacitive load, most op amps exhibit peaking in their frequency response. In general, to minimize peaking or to ensure device stability for larger values of capacitive loads, a small series resistor can be added between the op amp output and the load capacitor. Figure 34 shows the frequency response of the AD839 for various capacitive loads without any series resistance. In this condition, the maximum recommended capacitive load is around pf. As shown in Figure 3, the addition of a. Ω series resistor limits peaking to approximately 3 db when driving capacitive loads up to pf. GAIN (db) GAIN (db). V IN 499Ω Ω kω C L kω pf pf pf Figure 34. AD839 Capacitive Load Frequency Response without Series Resistance V IN 499Ω Ω kω.ω C L kω. pf 47pF pf Figure 3. AD839 Capacitive Load Frequency Response with Series Resistance Rev. A Page of 6

13 THERMAL CONSIDERATIONS When using a quad, high output current amplifier, such as the AD839, special consideration should be given to system level thermal design. In applications such as ADSL/ADSL+, the AD839 could be required to dissipate as much as.4 W or more on chip. Under these conditions, particular attention should be paid to the thermal design in order to maintain safe operating temperatures on the die. To aid in the thermal design, the thermal information in the Thermal Resistance section can be combined with what follows here. The information in Table 4 and Figure 3 is based on a standard JEDEC 4-layer board and a maximum die temperature of C. To provide additional guidance and design suggestions, a thermal study was performed under a set of conditions more closely aligned with an actual ADSL/ADSL+ application. In a typical ADSL/ADSL+ line card, component density usually dictates that most of the copper plane used for thermal dissipation be internal. Additionally, each ADSL/ADSL+ port may be allotted only square inch, or even less, of board space. For these reasons, a special thermal test board was constructed for this study. The 4-layer board measured approximately 4 inches 4 inches and contained two internal oz copper ground planes, each measuring inches 3 inches. The top layer contained signal traces and an exposed copper strip ¼ inch 3 inches to accommodate heat sinking, with no other copper on the top or bottom of the board. Three 8-lead TSSOPs were placed on the board representing six ADSL channels, or one channel per square inch of copper, with each channel dissipating 7 mw on-chip (.4 W per package). The die temperature is then measured in still air and in a wind tunnel with calibrated airflow of LFM, LFM, and 4 LFM. Figure 36 shows the power dissipation versus the ambient temperature for each airflow condition. The figure assumes a maximum die temperature of 3 C. No heat sink was used. POWER DISSIPATION (W) STILL AIR LFM 4LFM LFM AMBIENT TEMPERATURE ( C) T J = 3 C Figure 36. Power Dissipation vs. Ambient Temperature and Air Flow 8-Lead TSSOP/EP Rev. A Page 3 of 6 AD839 This data is only provided as guidance to assist in the thermal design process. Due diligence should be performed with regards to power dissipation because there are many factors that can affect thermal performance. TYPICAL ADSL/ADSL+ APPLICATION In a typical ADSL/ADSL+ application, a differential line driver is used to take the signal from the analog front end (AFE) and drive it onto the twisted pair telephone line. Referring to the typical circuit representation in Figure 37, the differential input appears at VIN+ and VIN from the AFE, while the differential output is transformer coupled to the telephone line at tip and ring. The common-mode operating point, generally midway between the supplies, is set through VCOM. V IN+ R IN V IN R4 R BIAS V COM :N R R R BIAS R4 V P V P R R3 V OA V OA R3 R m R m Figure 37. Typical ADSL/ADSL+ Application Circuit TIP RING R OUT In ADSL/ADSL+ applications, it is common practice to conserve power by using positive feedback to synthesize the output resistance, thereby lowering the required ohmic value of the line matching resistors, Rm. The circuit in Figure 37 is somewhat unique in that the positive feedback introduced via R3 has the effect of synthesizing the input resistance as well. The following definitions and equations can be used to calculate the resistor values necessary to obtain the desired gain, input resistance, and output resistance for a given application. For simplicity the following calculations assume a lossless transformer. The following values are used in the design equations and are assumed already known or chosen by the designer. VIN RIN N VLINE Rm R VP RL Differential input voltage Desired differential input resistance Transformer turns ratio Differential output voltage at tip and ring Each is typically % to % of the transformer reflected line impedance Recommended in the amplifier data sheet Voltage at the + inputs to the amplifier, approximately ½ VIN (must be less than VIN for positive input resistance) Transformer reflected line impedance

14 Additional definitions for calculating resistor values include: VOA Voltage at the amplifier outputs k Matching resistance reduction factor AV Gain from VIN to transformer primary β Negative feedback factor α Positive feedback factor Note: R must be calculated before β and α. V β OA V = LINE ( + k) N R R+ R R k = R L m V A V = N V LINE = α = β( k) With the above known quantities and definitions, the remaining resistors can readily be calculated. VP R R = V V R R4 = A R3 = OA IN V P ( V V ) IN V R4 IN P ( RRm + RRL α RRL α RRL ) α R ( R+ R) R α R3R4 BIAS = R4 α( R3 + R4) L After building the circuit with the closest % resistor values, the actual gain, input resistance, and output resistance can be verified with the following equations. N GAIN( V IN to LINE) = R4 R4 β( k + ) + + R3 R R R IN OUT = A R4 = V Rm + R β R4RL R4 R R BIAS L R ( R4 + R ) BIAS m N BIAS R+ R R4 R R3 + R4 + R R4 R3 BIAS BIAS IN MULTITONE POWER RATIO The DMT signal used in ADSL/ADSL+ systems carries data in discrete tones or bins, which appear in the frequency domain in evenly spaced 4.3 khz intervals. In applications using this type of waveform, multitone power ratio (MTPR) is a commonly used measure of linearity. Generally, there are two types of MTPR that designers are typically concerned with: in-band and out-of-band MTPR. In-band MTPR is defined as the measured difference from the peak of one tone that is loaded with data to the peak of an adjacent tone that is intentionally left empty. Out-of-band MTPR is more loosely defined as the spurious emissions that occur in the receive band located between.87 khz and the first downstream tone at 38 khz. Figure 38 and Figure 39 show the AD839 in-band MTPR for a. crest factor waveform for empty bins in the ADSL and extended ADSL+ bandwidths. Figure 4 shows the AD839 out-of-band MTPR for the same waveform CENTER 647kHz CENTER.7MHz 7.dB khz/ Figure 38. In-Band MTPR at 647 khz SPAN khz 64.4dB khz/ Figure 39. In-Band MTPR at.7 MHz SPAN khz Rev. A Page 4 of 6

15 START 3kHz 4.kHz/ Figure 4. Out-of-Band MTPR STOP 4kHz LIGHTNING AND AC POWER FAULT The AD839 can be used is as an ADSL/ADSL+ line driver. In this application, the line driver is transformer-coupled to the twisted pair telephone line and could be subjected to large line transients resulting from events such as lightning strikes or downed power lines. In this type of environment, additional circuitry may be required to protect the AD839 from damage that may occur as a result of these events. Using a minimal amount of external protection, the AD839 has successfully passed overvoltage and overcurrent compliance testing per the ITU K- specification. For details on the external protection circuitry, contact the high current driver product line at high_current_drivers.com@analog.com. Rev. A Page of 6

16 OUTLINE DIMENSIONS BOTTOM VIEW 8. MAX PIN...6 BSC SEATING PLANE BSC..9 8 COMPLIANT TO JEDEC STANDARDS MO-3AET EXPOSED PAD (Pins Down) Figure 4. 8-Lead Thin Shrink Small Outline with Exposed Pad [TSSOP/EP], (RE-8-), Dimensions shown in millimeters PIN INDICATOR..8.8 MAX SEATING PLANE. BSC SQ TOP VIEW.8 MAX.6 TYP BSC SQ. REF. MAX. NOM.6 MAX. BSC COPLANARITY.8.6 MAX COMPLIANT TO JEDEC STANDARDS MO--VHHD- 3. BSC EXPOSED PAD (BOTTOM VIEW) SQ 3.. MIN 3. REF 3. BSC PIN INDICATOR Figure 4. 3-Lead Lead Frame Chip Scale Package [LFCSP_VQ], mm mm Body, Very Thin Quad (CP-3-3) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Outline AD839ARE 4 C to +8 C 8-Lead Thin Shrink Small Outline Package (TSSOP/EP) RE-8- AD839ARE-REEL 4 C to +8 C 8-Lead Thin Shrink Small Outline Package (TSSOP/EP) RE-8- AD839ARE-REEL7 4 C to +8 C 8-Lead Thin Shrink Small Outline Package (TSSOP/EP) RE-8- AD839AREZ 4 C to +8 C 8-Lead Thin Shrink Small Outline Package (TSSOP/EP) RE-8- AD839AREZ-REEL 4 C to +8 C 8-Lead Thin Shrink Small Outline Package (TSSOP/EP) RE-8- AD839AREZ-REEL7 4 C to +8 C 8-Lead Thin Shrink Small Outline Package (TSSOP/EP) RE-8- AD839ACP-R 4 C to +8 C 3-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-3-3 AD839ACP-REEL 4 C to +8 C 3-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-3-3 AD839ACP-REEL7 4 C to +8 C 3-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-3-3 Z = Pb-free part. Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D48 3/(A) Rev. A Page 6 of 6