Lecture 22. Circuit Design Techniques for Wireless Communications

Transcription

1 ecture ircuit Desig Techiques for Wireless ommuicatios this lecture you will lear: ircuits for wireless commuicatios Sigal multipliers ad mixers Sigle-balaced ad double-balaced mixers MOS F Oscillators Aalog to digital coverters Digital to aalog coverters EE 35 Sprig 5 Farha aa orell Uiversity E&M adiatio Sigal Trasmissio i Wireless ommuicatios Atea Soud waves ostellatio size: M Power amplifier (PA) Electrical aalog sigal ow oise Amplifier (NA) Filter Filter Mixer or modulator Electrical aalog sigal AD X X X Digital oder Digital Output N bits N DSP QAM sigal costellatio formatio i bits per poit i the costellatio: M X EE 35 Sprig 5 Farha aa orell Uiversity

2 Sigal eceptio i Wireless ommuicatios Soud waves Electrical aalog sigal DA Digital iput N bits PA Filter N E&M adiatio Atea NA Filter Electrical aalog sigal Mixer or demodulator X X X Digital decoder DSP QAM sigal costellatio X EE 35 Sprig 5 Farha aa orell Uiversity X t QAM F sigals X t cos si F Mixer or Modulator/Demodulator O t O t XtcosOt XtsiOt At cos tt Mixer or modulator O Atea X t X t PF PF cos O t si O t Mixer or demodulator NA EE 35 Sprig 5 Farha aa orell Uiversity cos si X t Ot X t Ot o BPF o Atea cos cos cos Ot Ot Ot Ot Ot Ot t t t si si cos cos O si O si O

3 Mixer Fuctio: X t v cos t F F Sigal Mixers cos AvFvO cos Ft Ot vo cosot A cos O F t v F v O coso F t O F F O Mixer oversio Gai: A v F v O A oversio gai = G = v O vf Need a strog O sigal to obtai a good coversio gai Need oliear compoets to realize voltage mixers ad/or multipliers O O F O F Sidebads EE 35 Sprig 5 Farha aa orell Uiversity O FET Sigal Mixer: Square aw Mixer F DD At resoace the impedace of the tak is ideally ifiite F short i D v OUT v F cos t F F short BAS BAS v cos t O O Forget the output coductace for a momet, the: k i D cos cos B vf Ft vo Ot TN k k B TN vf cos Ft vocos Ot k B TN vf cosftvo cosot EE 35 Sprig 5 Farha aa orell Uiversity 3

4 O FET Sigal Mixer: Square aw Mixer F DD At resoace the impedace of the tak is ideally ifiite F short i D v OUT v F cos t F F short BAS BAS v cos t O O Forget the output coductace for a momet, the: k k k i D B TN F O F cos F O cos O v v v t v t 4 4 kv v cos t t cos cos cos F O F O k B TN vf Ft vo Ot EE 35 Sprig 5 Farha aa orell Uiversity O FET Sigal Mixer: Square aw Mixer F DD At resoace the impedace of the tak is ideally ifiite F short i D v OUT v F cos t F F short BAS BAS v cos t O O Forget the output coductace for a momet, the: k i D cos cos B vf Ft vo Ot TN D A k k B TN vf cos Ft vocos Ot k B TN vf cosftvo cosot A EE 35 Sprig 5 Farha aa orell Uiversity 4

5 v F Gate cos t F v GS - FET Sigal Mixer: Square aw Mixer g v m GS Source vo cosot k Drai vgs r o vout O F t The domiat sigal compoets at the outout ear the frequecy O are: k j Domiat term jt vout t vfvo e e j ro O F oversio gai = G k j jt k v F v O e e v j FvOro ro O F vf j jt k gmvoe e v j Oro Not good ro O EE 35 Sprig 5 Farha aa orell Uiversity DD FET Sigal Mixer/Multiplier: eview of a Diff Amp DD Od O O D D BAS k BAS BAS k d BAS BAS Provided: BAS k D Od D D D k k O k BAS GS GS O TN TN k 4 k BAS BAS BAS k k 4 4 k d 4 d BAS 4 k BAS 4 k BAS d d Assume small EE 35 Sprig 5 Farha aa orell Uiversity 5

6 DD FET Sigal Mixer/Multiplier: Sigle-Balaced Mixer DD A sigle-balaced mixer: BAS Od O O k 4 k Ma O O Mb k k K BAS U TN K Product terms Mc U K Od O O k U TN k But still ot quite what oe would wat.. i) The iput voltage U is ot differetial. ii) The two iput voltages beig multiplied do t appear symmetrically i the fial aswer iii) There is a additioal term proportioal oly to - i the output EE 35 Sprig 5 Farha aa orell Uiversity FET Sigal Mixer/Multiplier: Sigle-Balaced Mixer DD DD D D Ma D Mb d BAS k 4 r r k OUT o op k K BAS U TN U K Mc kk U r r OUT d TN o op EE 35 Sprig 5 Farha aa orell Uiversity 6

7 FET Sigal Mixer/Multiplier: Sigle-Balaced Mixer DD DD v O cos t O kk vout t ro rop vovf cos Ft Ot cos o op BAS TN O coso kk r r U v t F short BAS k Ma Mb BAS F short Not good v F F short cos t F K U BAS Mc oversio gai = G kk v FvO ro rop vf kk vo ro rop EE 35 Sprig 5 Farha aa orell Uiversity DD FET Sigal Mixer/Multiplier: A Double-Balaced Mixer A cross-coupled double-balaced differetial pair DD O O Da Db Dd Dc O Ma O Mb Md Mc k U Me U Mf K K Da Db Dc Dd BAS BAS EE 35 Sprig 5 Farha aa orell Uiversity 7

8 FET Sigal Mixer/Multiplier: A Double-Balaced Mixer A cross-coupled double-balaced differetial pair Da Db Dc Dd BAS k d Da GSa TN k 4 k d Db GSb TN k 4 k d Dc GSc TN k 4 k d Dd GSd TN k 4 4 k 4 k 4 k 4 k d U U Ud U U Od U U U d d Exactly what oe would wat! Od EE 35 Sprig 5 Farha aa orell Uiversity O O Da Dd Dc Db 4 4 k k k K k U U k kk U U Product terms Oscillators: Electroic, Photoic, ad Spitroic Photoic Oscillators (asers) ( THz THz) Electro Spi Oscillators (orell) ( MHz GHz) MOS THz Oscillators (orell) ( GHz 5 GHz) ~ m Plasmoic Naopatch Spasers (orell, UB) Metal Fiber lasers (orell) m Semicoductor lasers (orell) Semicoductor layers m EE 35 Sprig 5 Farha aa orell Uiversity 8

9 Electrical Oscillators: A Pheomeological troductio osider the followig circuit with positive feedback: vi t vout t A oop gai: A K K vout Oe ca have a o-zero output at frequecy, with o iput, if at that frequecy: KAv out KA A K AK ad AK,,... For steady state oscillatio, the loop gai must equal uity steady state operatio (whe oe ca use phasors): A vi KA KA vout A vi EE 35 Sprig 5 Farha aa orell Uiversity Electrical Oscillators: A Pheomeological troductio osider the followig circuit with positive feedback: A vout t The uity loop gai coditio A K differet frequecies at the same time! K Add a badwidth limitig elemet i the loop a arrow badpass filter: A K could be met (or almost met) at may F o vout t Now the coditio for steady state oscillatio at the frequecy becomes: A F K Will favor oscillatio at frequecy o EE 35 Sprig 5 Farha aa orell Uiversity 9

10 Electrical Oscillators: A Pheomeological troductio A F vout t o K A o F o K Now the coditio for steady state oscillatio at the frequecy o is: But is the oscillatio goig to be stable? Q: What if the loop gai is slightly larger tha uity: A F K o The oscillatios will build up to ifiity (phasor aalysis ot valid aymore because there is o steady state) o Q: What if the loop gai is slightly smaller tha uity: A F K o The oscillatios might ever build up o EE 35 Sprig 5 Farha aa orell Uiversity Electrical Oscillators: A Pheomeological troductio A F vout t o K What if the gai A() is a o-liear decreasig fuctio of the iput sigal power: A A a a A ui uout ui ui The the coditio for stable steady state oscillatio becomes: AoFoK Stable provided: a o F o K aofok ui o The sigal loopig aroud i the oscillator will adjust its magitude automatically such that the uity gai coditio is met..!!! EE 35 Sprig 5 Farha aa orell Uiversity

11 Electrical Oscillators: A Pheomeological troductio A F vout t o K oditios ecessary (but ot sufficiet) for stable steady state oscillatios: ) The complex loop gai must equal uity ) There must be a badwidth limitig elemet (or a filter) i the loop 3) The magitude of the loop gai must be a decreasig fuctio of the loop sigal power (this is called gai saturatio) EE 35 Sprig 5 Farha aa orell Uiversity FET Electrical Oscillators: olpitts Oscillator DD Parasitic resistor v BAS BAS A commo gate FET stage coected i a positive feedback loop used ca be used to realize a oscillator EE 35 Sprig 5 Farha aa orell Uiversity

12 Gai Saturatio i FETs DD OUT OUT vout DD v BAS Bias poit N v i BAS TN N As the iput small sigal icrease icreases i stregth, the gai experieced by it will decrease EE 35 Sprig 5 Farha aa orell Uiversity olpitts Oscillator DD Filter Gai v BAS Gai BAS Filter Feedback path A commo gate FET stage coected i a positive feedback loop used ca be used to realize a oscillator EE 35 Sprig 5 Farha aa orell Uiversity

13 olpitts Oscillator: Small Sigal Model Assume the capacitors iteral to the FET, gs ad gd, are ope at the frequecies of iterest () vout Gate gmvgs Drai v gs r o - Source v s () K at (): v v v EE 35 Sprig 5 Farha aa orell Uiversity out out s gmvs j vout vs o j r K at (): j v g v v v j v v These give: out s s m s out s r o vout jv j s Gate v gs - vs olpitts Oscillator: Small Sigal Model v g v m gs Source r o Drai out small small gm j v out j jro ro Note: The igored quatities eed ot be small ompare with: KA v out EE 35 Sprig 5 Farha aa orell Uiversity 3

14 olpitts Oscillator: Small Sigal Model This implies: j j eq eq j j g m ad: m g m EE 35 Sprig 5 Farha aa orell Uiversity g The above implies that the FET gai must balace the dissipatio due to the resistor Electrical Oscillators: Aother iewpoit osider the followig circuit: () vout G A egative resistace elemet (A gai elemet) Doig K at ode () gives: small G j G vout j j This implies: ad: j G j The above implies that the gai must balace the dissipatio due to the resistor EE 35 Sprig 5 Farha aa orell Uiversity 4

15 A Differetial Pair Negative esistace Elemet osider the followig cross-coected differetial pair: DD A B BAS Suppose we fid the differetial resistace lookig ito the termials A ad B.. EE 35 Sprig 5 Farha aa orell Uiversity F short i t Small sigal groud BAS A Differetial Pair Negative esistace Elemet DD vo v o () () id i d M M F short i t We have: vo vo vt v v v v gs gs t id Therefore: vt id gm vt id gm Ad K gives at () ad (): vo id it vo id it Subtractig the above two gives: _ v t Forget the output coductace of the FETs for ow vt i g g g t m m m Negative!! EE 35 Sprig 5 Farha aa orell Uiversity 5

16 A Differetial Pair Negative esistace Elemet i t v t _ i t v gs - i t gmvgs r o vo v o i id i t d r gmv o gs gs v - v v v v v v v gs gs t id o o t r oc K gives: v gmvgsgovovsit v gmvgs govo vsit Subtractig the two gives: vt gmvt govt it o o v s vt gmvt govt it vt i g g t m o g m g o ro gm EE 35 Sprig 5 Farha aa orell Uiversity A Differetial Pair Negative esistace Elemet DD Equivalet small sigal model F short F short F short F short M M Small sigal esistace = g m BAS i t i t v t vt i g g g t m m m EE 35 Sprig 5 Farha aa orell Uiversity v t 6

17 A Differetial Pair Negative esistace Elemet DD Equivalet small sigal model F short F short F short F short M M Small sigal esistace = g m r o r o BAS i t i t v t vt ro i g g t m m EE 35 Sprig 5 Farha aa orell Uiversity v t Now with FET output coductace icluded A Differetial Pair Oscillator osider the followig cross-coected differetial pair: DD Parasitic BAS EE 35 Sprig 5 Farha aa orell Uiversity 7

18 A Differetial Pair Oscillator osider the followig cross-coected differetial pair: DD Parasitic r o g m r o vout gmro BAS small gm gm j vout j j j gm j EE 35 Sprig 5 Farha aa orell Uiversity DD A Higher Gai Differetial Pair Oscillator r op g mp r op vout r o g m r o BAS j j gm gmp EE 35 Sprig 5 Farha aa orell Uiversity 8

19 Aalog-to-Digital overters(ads) ad Digital-to-Aalog overters (DAs) Aalog iput N AD Digital Output N bits MN N MAX esolutio: MAX MN N Dyamic age: MAX log MN Digital put N bits DA Aalog output EE 35 Sprig 5 Farha aa orell Uiversity Aalog-to-Digital overters (ADs) N t AD Aalog iput Digital Output N bits ogical OW ogical HGH B N B B B Most sigificat bit (MSB) east sigificat bit (SB) Aalog value, correspodig to a digital value, is: MN MAX N MN N B N N B N... B B B EE 35 Sprig 5 Farha aa orell Uiversity 9

20 N t Aalog iput Sample ad Hold i Aalog-to-Digital overters (ADs) Ati-aliasig filter Sample ad hold K S t AD Digital Output N bits N t K time time Samplig times Sample the iput waveform periodically ad hold the sampled value i place till the ext samplig evet EE 35 Sprig 5 Farha aa orell Uiversity N t Aalog iput Ati-Aliasig Filter i Aalog-to-Digital overters (ADs) Ati-aliasig filter N Sigal Sample ad hold K Samplig rate = S t s AD S Digital Output N bits oise oise Frequecy () W Noise outside the sigal bad gets aliased ito the sigal bad upo samplig oise N s s Ati-aliasig filter oise W s s EE 35 Sprig 5 Farha aa orell Uiversity

21 N t Aalog iput Sample ad Hold i Aalog-to-Digital overters (ADs) N t Ati-aliasig filter Sample ad hold K S t K AD Digital Output N bits Samplig times time ) put impedace ot large eough ) Output could have a offset 3) apacitor ca take a log time to charge/discharge K time N t - S t EE 35 Sprig 5 Farha aa orell Uiversity A arge iput impedace Output offset problem solved A Better Sample ad Hold ircuit S N K N t - A t ~ A t D K This FET keeps ode grouded whe ot samplig - t S Suppose whe the K is HGH the curret through the FET is (assumig liear regio): DS D k GS TN DS k K TN small The: d S A S N D dt d S A A S N dt S is pulled to N ad A A t t is pulled to ~ withi a S t S e N e very short time after K goes HGH EE 35 Sprig 5 Farha aa orell Uiversity

22 S Flash Aalog-to-Digital overters (ADs) 3-bit Flash AD oltage resolutio: MAX MAX MN N oltage Equivalet digital output Digital Output 3 bits Aalog iput Time MN Pros: ery high speed architecture os: ompoet itesive (requires N - comparators) oltage comparators oltage comparators are essetially diff amps that have very low voltage offset errors; the iput voltage offset error eeds to be much less tha the resolutio of the AD EE 35 Sprig 5 Farha aa orell Uiversity Successive Approximatio egister (SA) Aalog-to-Digital overters (ADs) Stored digital value teral register keeps updatig the stored digital value, compares the resultig aalog value obtaied from this digital value to the iput aalog value, util the stored value matches the iput value Ad the the stored value is placed i the output register Error S Diff amp (omparator) Output Digital Output EE 35 Sprig 5 Farha aa orell Uiversity

23 Successive Approximatio egister (SA) Aalog-to-Digital overters (ADs) osider a 4-bit SA-AD with a -3 iput rage => olts => 3 olts esolutio =. olt Suppose the iput is.7 olts Start SA = DA =.6 Error = Stored value is smaller SA = DA = 3. Error = - Stored value is larger SA = DA =.4 Error = Stored value is larger SA = DA =. Error = Stored value is larger SA = DA =.8 Error = Stored value is larger Produce output Pros: Scalable to high resolutios os: Slower tha flash EE 35 Sprig 5 Farha aa orell Uiversity Pipelied Aalog-to-Digital overters (ADs) Mai dea: Use features of the flash architecture but scale to higher resolutios Example: Build a 6-bit pipelied AD from two 3-bit Flash ADs S t 3-bit AD 3-bit DA A t - E t 3-bit AD MSB SB Output register S (t) 6-bit digital output S (t) A (t) A (t) t E (t) t EE 35 Sprig 5 Farha aa orell Uiversity 3

24 a easily geeralize: Pipelied Aalog-to-Digital overters (ADs) S t 3 MSB Next-3 MSB Output register N-bit digital output Pros: Scalable to high resolutios Fast os: arge power dissipatio EE 35 Sprig 5 Farha aa orell Uiversity Aalog-to-Digital overters (ADs): State of the Art Walt Kester, Aalog devices (5) William Klei, Texas strumets (7) EE 35 Sprig 5 Farha aa orell Uiversity 4

25 / adder Digital-to-Aalog overters (DAs) HGH B HGH B HGH B HGH B N eed ot be precise Oly ad eed to be i the ratio of : MN - A OUT f: A HGH BN B N 4 MAX N MN B N 8 N HGH 3 B... N The the output will be the desired aalog output: OUT MN MAX N MN N B N N B N EE 35 Sprig 5 Farha aa orell Uiversity B N B N... B B B Thermometer ode Digital-to-Aalog overters (DAs) N bits (B) oder N - bits (D) MN N k D k N HGH D N HGH D N HGH D - A OUT EF EF D N D N EF... D D N N BN BN... B B B OUT MN MAX N MN N BN EE 35 Sprig 5 Farha aa orell Uiversity N BN A... B MAX N B MN B 5

26 Wireless ommuicatios Soud waves Electrical aalog sigal DA Digital iput N bits PA Filter N E&M adiatio Atea NA Filter Electrical aalog sigal Mixer or demodulator X X X Digital decoder DSP QAM sigal costellatio X EE 35 Sprig 5 Farha aa orell Uiversity EE 35 Sprig 5 Farha aa orell Uiversity 6

27 Switchig Mixers Slides for EE 35 By Zach Boyto

28 Switchig Mixers: Why? Silico developmet is drive by digital With better digital comes smaller faster devices These treds are bad for may aalog desigs ower headroom, worse chael legth modulatio, velocity saturatio, etc What does get better are switches!

29 Switchig Mixer: Basics Say the switch opes ad closes with O We kow that whe the switch is ope: Whe the switch is closed: We ca therefore write the overall curret as: F = F S O Where O is a square wave with amplitude ad frequecy f O

30 Switchig Mixer: Basics ot. Writig the overall curret as: Doig a Fourier series expasio o O gives us: O(t)= π[ si (ω O t) si(3 ω O t) 3 f we take: si(5 ω t ) O 5...] F = A cos(ω F t) The we ca see that the overall curret is: F (t)= A cos(ω F t ) ( S ) A π( S )[ cos(ω t)si(ω t) cos(ω t)si (3ω t) F O F O 3 cos(ω t)si (5ω t) F O 5...]

31 Switchig Mixer: Basics ot. We have just see that the curret through the switch is: f we were to look at the voltage across we would see our multiplied toes ad may harmoics! Due to this we typically apply filterig to the the voltage across as follows: bb forms a short for ay high frequecies so oly low frequecy voltages appear across

32 Switchig Mixer: ssues additio to doig dow ad up coversio aroud the fudametal toe we also get coversio ear our harmoics. The dow coversio of harmoics ca be very detrimetal to mixer performace Harmoic Dow coversio ca be thought of as aliasig ad causes more oise to be dow coverted. Harmoics ca be rejected if we switch to a multiphase topology. For those iterested i multiphase mixers more iformatio ca be foud i the paper: "mplicatios of Passive Mixer Trasparecy for mpedace Matchig ad Noise Figure i Passive Mixer-First eceivers," O Professor Molar's Website mage from:. Adrews ad A.. Molar, "mplicatios of Passive Mixer Trasparecy for mpedace Matchig ad Noise Figure i Passive Mixer-First eceivers," i EEE Trasactios o ircuits ad Systems : egular Papers, vol. 57, o., pp , Dec..S