Serial Controlled, 8-Channel SPST Switch

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1 General Description The analog switch with serial digital interface offers eight separately controlled single-pole-single-throw (SPST) switches. ll switches conduct equally in either direction, and on-resistance (100Ω) is constant over the analog signal range. These MOS switches can operate continuously with power supplies ranging from ±4.5V to ±20V and handle rail-to-rail analog signals. Upon power-up, all switches are off, and the internal serial and parallel shift registers are reset to zero. The is equivalent to two DG211 quad switches but controlled by a serial interface. The interface is compatible with the Motorola SPI interface standard. Functioning as a shift register, this serial interface allows data (at ) to be locked in synchronous with the rising edge of clock (). The shift register s output () enables several s to be daisy chained. pplications Serial Data cquisition and Process ontrol vionics Signal Routing Networking Features 8 Separately ontrolled SPST Switches SPI-ompatible Serial Interface ccepts ±15V nalog Swings Multiple Devices an e Daisy-hained Ordering Information PRT TEMP RNGE PIN-PKGE NG 0 to Narrow Plastic DIP WG 0 to Wide SO /D 0 to +70 Dice* ENG -40 to Narrow Plastic DIP EUG -40 to TSSOP EWG -40 to Wide SO MRG -55 to Narrow ERDIP** *ontact factory for dice specifications. **ontact factory for availability and processing to MIL-STD-883. Pin onfiguration NO0 NO7 TOP VIEW OM0 OM7 V VL 3 22 PRLLEL REGISTER ND TRNSLTOR GND NO V- NO7 D IN 8-IT SHIFT REGISTER OM0 NO OM7 NO6 OM OM6 V L +5V TRNSLTOR LOK TRNSLTOR NO2 OM2 NO3 OM NO5 OM5 NO4 OM4 TRNSLTOR LTH DIP/SO ; Rev 4; 7/17

2 bsolute Maximum Ratings Voltages Referenced to V- V+...44V GND...25V V L... (GND - 0.3V) to (V V),,,, NO_, OM_...V- -2V to V+ +2V or 30m, whichever occurs first ontinuous urrent (any terminal)...30m Peak urrent, NO or OM (pulsed at 1ms, 10% duty cycle MX)...00m Note 1: ll leads are soldered or welded to P boards. ontinuous Power Dissipation (T = +70 ) (Note 1) Narrow Plastic DIP (derate 13.33mW/ above +70 ) mW Wide SO (derate 11.76mW/ above +70 )...941mW Narrow ERDIP (derate 12.50mW/ above +70 ) mW TSSOP (derate 12.2mW/ above +70 )...30m Operating Temperature Ranges...0 to +70 E to +85 MRG to +125 Storage Temperature Range to +160 Lead Temperature (soldering, 10sec) Stresses beyond those listed under bsolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Electrical haracteristics (V L = +5V ±10%, V+ = 15V, V- = -15V, T = T MIN to T MX, unless otherwise noted. Typical values are at T = +25.) SWITH PRMETER SYMOL ONDITIONS MIN TYP MX UNITS nalog Signal Range V NLOG T = T MIN to T MX V On-Resistance R ON V OM = ±10V, I NO = 1m NO Off-Leakage urrent OM Off-Leakage urrent I NO(OFF) I OM(OFF) V OM = -14V, V NO = +14V V OM = -14V, V NO = +14V V OM = -14V, V NO = +14V V OM = -14V, V NO = +14V OM On-Leakage urrent I OM(ON) V OM = V NO = +14V DIGITL I/O,, Input Logic Threshold High,, Input Logic Threshold Low,, Input urrent Threshold High,, Input urrent Threshold Low Output Voltage Logic High V OM = V NO = -14V T = T = T = T = T = T = T = V L = +5V 2.4 V IH V L = +15V V L = +5V 0.8 V IL V L = +15V 3 V, V, V = 2.4V I INH V L = +15V, V, V, V = 11V V, V, V = 0.8V I INL V L = +15V, V, V, V = 3V V I = 0.8m 3.5 V L V Ω n n n V V µ µ Maxim Integrated 2

3 Electrical haracteristics (continued) (V L = +5V ±10%, V+ = 15V, V- = -15V, T = T MIN to T MX, unless otherwise noted. Typical values are at T = +25.) PRMETER SYMOL ONDITIONS MIN TYP MX UNITS DIGITL I/O Output Voltage Logic Low V I = -1.6m 0.4 V V L RESET Voltage V LL (Note 2) 0.8 V V L RESET Voltage V LH T = V Input Hysteresis HYST T = mv SWITH DYNMI HRTERISTI Turn-On Time t ON From rising-edge of T = ns Turn-Off Time t OFF From rising-edge of T = ns NO Off-apacitance NO(OFF) V S = GND, f = 1MHz T = pf OM Off-apacitance OM(OFF) V S = GND, f = 1MHz T = pf hannel On-apacitance OM(ON) V D = V S = GND, f = 1MHz T = pf Off Isolation OIRR R L = 100Ω, L = 15pF, V S = 1V RMS, f = 100kHz T = d hannel-to-hannel rosstalk RR R L = 50Ω, L = 15pF, V S = 1V RMS, f = 100kHz T = d reak-efore-make Delay T M ns lock Feedthrough at S, D (Note 3) E D LOD = S LOD = 75Ω, measured at S and D T = nv-sec POWER SUPPLIES Power-Supply Voltage Range V+/V- ±4.5 ±20 V V L Power-Supply Voltage Range V L 4.5 V+ V V+ Supply urrent I+ V- Supply urrent I- = = = 0V/5V = = = 0V/5V V L Supply urrent I L = = = 0V/5V T = Note 2: When V L falls below this voltage, all switches are set off and the internal shift register is cleared (all zero). Note 3: Guaranteed, not production tested. 500 T = T = µ µ µ Maxim Integrated 3

4 Timing haracteristics of Serial Digital Interface (Figure 1) (V L = +5V ±10%, V+ = 15V, V- = -15V, T = T MIN to T MX, unless otherwise noted.) PRMETER SYMOL ONDITIONS MIN TYP MX UNITS Maximum Frequency f 2.1 MHz ycle Time t H + t L 480 ns Lead Time t S 240 ns Lag Time t H2 240 ns High Time t H 190 ns Low Time t L 190 ns Data-Setup Time t DS 200 ns Data-Hold Time t DH 0 ns Data Valid fter Falling Data-Hold Time fter Rising (Note 4) t DO 50% of to 10% of L = 10pF T = L = 10pF 0 ns Rise Time of (Note 3) 20% V L to 70% V L, L = 10pF 100 ns 400 ns llowable Rise Time at,, (Note 3) 20% V L to 70% V L, L = 10pF 2 µs Fall Time of (Note 3) 70% V L to 20% V L, L = 10pF 100 ns llowable Fall Time at,, (Note 3) 70% V L to 20% V L, L = 10pF 2 µs Note 4: This specification guarantees that data at D OUT never appears before s falling edge. Maxim Integrated 4

5 Typical Operating haracteristics (V+ = +15V, V- = -15V, V L = 5V, T = +25, unless otherwise noted.) RON (Ω) : 5V : 10V : 15V D: 20V R ON vs. V OM ND POWER-SUPPLY VOLTGE D toc01 RON (Ω) : T = +25 : T = +85 : T = +125 R ON vs. V OM ND TEMPERTURE toc02 ton, toff (ns) t ON, t OFF vs. V OM t ON toc t OFF V OM (V) V OM (V) V OM (V) DT-HOLD TIME vs. POWER-SUPPLY VOLTGE toc DT-SETUP TIME vs. POWER SUPPLY toc LEKGE URRENT vs. TEMPERTURE toc06 DT-HOLD TIME (ns) DT-SETUP TIME (ns) ON-LEKGE (p) ±5 ±10 ±15 SUPPLY VOLTGE (V) ±20 0 ±5 ±10 ±15 SUPPLY VOLTGE (V) ± TEMPERTURE ( ) HRGE INJETION vs. V OM toc SUPPLY vs. TEMPERTURE I+ toc MINIMUM PULSE WIDTH vs. POWER SUPPLY toc09 Q (p) 35 0 I+, I-, IL (µ) 10 1 I L (ns) : ±5V : ±15V V OM (V) I TEMPERTURE ( ) ±5 ±10 ±15 SUPPLY VOLTGE (V) ±20 Maxim Integrated 5

6 Pin Description PIN NME FUNTION 1 Serial lock Input 2 V+ Positive Supply Voltage 3 Serial Data Input 4 GND Ground 5 NOØ Switch 0 6 OMØ Switch 0 7 NO1 Switch 1 8 OM1 Switch 1 9 NO2 Switch 2 10 OM2 Switch 2 11 NO3 Switch 3 12 OM3 Switch 3 13 OM4 Switch 4 14 NO4 Switch 4 15 OM5 Switch 5 16 NO5 Switch 5 17 OM6 Switch 6 18 NO6 Switch 6 19 OM7 Switch 7 20 NO7 Switch 7 21 V- Negative Supply Voltage 22 Serial Data Output 23 V L Logic Supply/Reset 24 hip Select Detailed Description Serial Digital Interface asic Operation Refer to Figure 2. The interface can be thought of as an 8-bit shift register controlled by. While is low, input data appearing at is clocked into the shift register synchronous with s rising edge. The data is an 8-bit word, each bit controlling one of eight switches in the (Table 1). is the output of the shift register, with data appearing synchronous with s falling edge. Data at is simply the input data delayed by eight clock cycles. When shifting the input data, D7 is the first bit in and out of the shift register. While shifting data, the switches remain in their original configuration. When the 8 bits of data have been shifted in, is brought high. This updates the new switch configuration and inhibits further data from entering the shift register. Transitions at and have no effect when is high, and holds the last bit in the shift register. The three-wire serial interface is compatible with the SPI and Microwire standards. If interfacing with a Motorola processor serial interface, set POL = 0. The is considered a slave device (Figures 2 and 3). Upon power-up, the shift register contains all zeros, and all switches are off. The latch that drives the analog switch is only updated on the rising edge of when is low. If is high when rises, the latch will not be updated until goes low. The POL = 1, PH = 1 SPI configuration does not update the latch correctly. Daisy haining For a simple interface using several s, daisy chain the shift registers as shown in Figure 5. The pins of all devices are connected together, and a stream of data is shifted through the s in series. When is brought high, all switches are updated simultaneously. dditional shift registers may be included anywhere in series with the data chain. ddressable Serial Interface When several serial devices are configured as slaves, addressable by the processor, pins of each are connected together (Figure 6). ddress decode logic individually controls of each slave device. When a slave is selected, its is brought low, data is shifted in, and is brought high to latch the data. Typically, only one slave is addressed at a time. is not used. Digital Feedthrough Digital feedthrough energy measures 100nV-sec, which means that with no filtering at the signal channel, feedthrough from a sharply rising clock edge into an unfiltered switch channel can be measured at 1Vp-p for 100ns. However, even 100pF capacitance in the switch channel, when combined with the switch resistance, yields a filter that reduces this transient to 10mVp-p typical. To reduce digital feedthrough, hysteresis (150mV typ) was added to the input so triangle or sine waves may be used. Maxim Integrated 6

7 t LL t H2 t H0 t S th t OFF t DS t L t H1 t DH t DO Figure 1. Timing Diagram SWITHES UPDTED DT LOKED IN D7 D6 D5 D4 D3 D2 D1 D0 MS LS DT LOKED OUT INPUT DT ITS D7 D6 D5 D4 D3 D2 D1 D0 D7 DT ITS FROM PREVIOUS DT INPUT POWER-UP DEFULT: D7 D0 = 0 Figure 2. Three-Wire Interface Timing Maxim Integrated 7

8 Table 1. Serial-Interface Switch Programming DT ITS FUNTION D7 D6 D5 D4 D3 D2 D1 D0 0 X X X X X X X Switch 7 open (off) 1 X X X X X X X Switch 7 closed (on) X 0 X X X X X X Switch 6 open X 1 X X X X X X Switch 6 closed X X 0 X X X X X Switch 5 open X X 1 X X X X X Switch 5 closed X X X 0 X X X X Switch 4 open X X X 1 X X X X Switch 4 closed X X X X 0 X X X Switch 3 open X X X X 1 X X X Switch 3 closed X X X X X 0 X X Switch 2 open X X X X X 1 X X Switch 2 closed X X X X X X 0 X Switch 1 open X X X X X X 1 X Switch 1 closed X X X X X X X 0 Switch 0 open X X X X X X X 1 Switch 0 closed X = Don t care SK MISO SO SI SPI PORT MOSI SK SPI PORT I/O I/O THE -SI ONNETION IS NOT REQURIED FOR WRITING TO THE, UT MY E USED FOR DT-EHO PURPOSES. THE -MISO ONNETION IS NOT REQURIED FOR WRITING TO THE, UT MY E USED FOR DT-EHO PURPOSES. Figure 3. onnections for Microwire Figure 4. onnections for SPI Maxim Integrated 8

9 TO OTHER SERIL DEVIES Figure 5. Daisy-hained onnection TO OTHER SERIL DEVIES Figure 6. ddressable Serial Interface Maxim Integrated 9

pplications Information 8 x 1 Multiplexer To use the as an 8 x 1 multiplexer, tie all drains together (OM0 to OM7); the mux inputs now source each switch (NO0 to NO7).

10 pplications Information 8 x 1 Multiplexer To use the as an 8 x 1 multiplexer, tie all drains together (OM0 to OM7); the mux inputs now source each switch (NO0 to NO7). Input a single 0V to +3V pulse at. s this is clocked through the register by, each switch will sequence on one at a time. 4-2 Differential Multiplexer To use the as a 4-2 differential multiplexer, tie OM0 through OM3 together and OM4 through OM7 together. Differential inputs will be the source inputs as follows: (NO0, NO4), (NO1, NO5), (NO2, NO6), (NO3, NO7). Figure 7 shows the serial input control at required to turn on two switches making a differential multiplexer. Reset Function Pulsing V L below +0.8V initiates the power-up reset function. The switches are set to the off position, and the serial shift register is reset to all zeros. Power-Supply Operation The operates with V = ±4.5V to ±20V and V L = +5V. With V- tied to ground, the part operates with V+ = +10V to +30V. The V L supply sets TTL input compatibility at a 1.6V switching threshold. s V L is raised, the switching threshold is raised, so the part is no longer TTL compatible. The also operates with a single power supply: V L = V+ and V- = 0V. With V L tied to V+, the V L supply cannot be used as a reset function. D4 D0 hip Topography SW4 SW0 V+ VL 4 LOK PULSES Figure 7. Differential Multiplexer Input ontrol GND V- is held low for four clock pulses; the first pulse is clocked into the fifth switch position as the second pulse is clocked into the first switch position. is pulled high to update switches; then is pulled low, and advances pulses to S1 and S5 positions, where is pulled high to update, etc. SPDT Switches Tie OM0 to NO1 so that NO0 and OM1 are now inputs and OM0/NO1 is the common output. SP is common output. Up to four SPDT switches can be made from each. Multiples of four or more can be made by daisy chaining devices. In Figure 8, is a pulse train. gain, is held low to clock in pulses and is pulled high to update; is held low to shift pulses, then pulled high to update, etc. NO0 OM0 NO1 OM1 NO2 OM2 NO3 OM " (2.51mm) OM4 NO4 NO7 OM7 NO " (3.96mm) OM6 NO5 OM5 1 LOK PULSE TRNSISTOR OUNT: 387 SUSTRTE ONNETED TO V+. Figure 8. Serial-Input ontrol for SPDT Switch Maxim Integrated 10

11 Package Information L 2 1 D1 e D 1 3 α E E1 e e DIM D D1 E E1 e e e L α MIN INHES MX S S MILLIMETERS MIN MX S 7.62 S PIN PLSTI DUL-IN-LINE (NRROW) PKGE E H DIM 1 D E e H h L α MIN INHES MX S MILLIMETERS MIN MX S D h x 45 α e mm 0.004in. L 24-PIN PLSTI SMLL-OUTLINE PKGE Maxim Integrated 11

12 Package Information (continued) E H DIM 1 D E e H h L α MIN INHES MX S MILLIMETERS MIN MX S D h x 45 α e mm 0.004in. L 24-PIN PLSTI SMLL-OUTLINE PKGE Maxim Integrated 12

13 Package Information (continued) Maxim Integrated 13

14 Revision History REVISION NUMER REVISION DTE 4 7/17 DESRIPTION Updated Min and Typ values of reak-efore-make Delay in Electrical haracteristics table PGES HNGED 3 For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim Integrated s website at Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical haracteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc Maxim Integrated Products, Inc. 14

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Precision, Quad, SPDT, CMOS Analog Switch

Precision, Quad, SPDT, CMOS Analog Switch 19-0189; Rev 1; 6/99 Precision, Quad, SPDT, MOS Analog Switch General Description The is a precision, quad, single-pole doublethrow (SPDT) analog switch. The four independent switches operate with bipolar