+3.3V/+5V, 8-Channel, Cascadable Relay Drivers with Serial/Parallel Interface

Transcription

1 AVAILABLE General Description The MAX482/MAX channel relay drivers offer built-in kickback protection and drive +3.3V/+5V nonlatching or dual-coil-latching relays. These devices are especially useful when driving +3V relays. Each independent open-drain output features a 2Ω on-resistance and is guaranteed to sink 7mA (min) of load current. Both devices consume less than 5µA (max) quiescent current and have 1µA output off-leakage current. The MAX482 features an SPI -/QSPI -/MICROWIRE compatible serial interface. Input data is shifted into an 8- bit shift register and latched to the outputs when transitions from low to high. Each data bit in the shift register corresponds to a specific output, allowing independent control of all outputs. The MAX4821 features a 4-bit (A, A1, A2, LVL) parallel-input interface. The first three bits (A, A1, A2) determine the output address, and the fourth bit (LVL) determines whether the selected output is switched on or off. Data is latched to the outputs when transitions from low to high. Both devices feature separate set and reset functions that allow the user to turn on or turn off all outputs simultaneously with a single control line. Built-in hysteresis (Schmidt trigger) on all digital inputs allows this device to be used with slow rising and falling signals, such as those from optocouplers or RC power-up initialization circuits. The MAX482/MAX4821 are available in 2-pin TSSOP and space-saving 2-pin Thin QFN packages. Central Office ATE DSL, ADSL Line Cards Industrial Equipment E1/T1 Redundancy Applications Pin Configurations continued at end of data sheet. Typical Application Circuits and Functional Diagrams appear at end of data sheet. MAX482/MAX4821 Features 8 Independent Output Channels Built-In Inductive Kickback Protection Drive +3V and +5V Relays Guaranteed 7mA (min) Coil Drive Current Function to Turn On All Outputs Simultaneously RE Function to Turn Off All Outputs Simultaneously SPI-/QSPI-/MICROWIRE-Compatible Serial Interface (MAX482) Serial Digital Output for Daisy Chaining (MAX482) Parallel Interface (MAX4821) Low 5µA (max) Quiescent Supply Current Space-Saving 2-Pin Thin QFN Package TOP VIEW RE Ordering Information PART TEMP RANGE PIN-PACKAGE MAX482ETP+ -4 C to +85 C 2 Thin QFN-EP* MAX482EUP+ -4 C to +85 C 2 TSSOP-EP* MAX4821ETP+ -4 C to +85 C 2 Thin QFN-EP* MAX4821EUP+ -4 C to +85 C 2 TSSOP-EP* +Denotes a lead(pb)-free/rohs-compliant package. *EP = Exposed pad *EP VCC Pin Configurations OUT MAX OUT3 OUT4 OUT5 OUT6 N.C. OUT SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. *CONNECT EP TO. THIN QFN For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at ; Rev 2; 1/1

2 MAX482/MAX4821 ABSOLUTE MAXIMUM RATINGS (All voltages referenced to.),...-.3v to +6.V OUT_...-.3V to (V +.3V),,,, RE, A, A1, A2, LVL...-.3V to +6.V...-.3V to ( +.3V) Continuous OUT_ Current (all outputs turned on)...15ma Continuous OUT_ Current (single output turned on)...3ma Continuous Power Dissipation (T A = +7 C) 2-Lead Thin QFN (derate 16.9mW/ C above +7 C)..135mW θ JA (Note 1) C/W 2-Pin TSSOP (derate 21.7mW/ C above +7 C) mW θ JA (Note 1)...46 C/W Operating Temperature Range...-4 C to +85 C Junction Temperature C Storage Temperature Range C to +15 C Soldering Temperature (1s)...+3 C Reflow Temperature C Note 1: Package thermal resistances were obtained using the method described in JEDEC specifications. For detailed information on package thermal considerations, refer to Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTI ( = +3V to +5.5V, V =, T A = -4 C to +85 C, unless otherwise noted. Typical values are at T A = +25 C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Operating Voltage V I = 3.6V 15 5 Quiescent Current I OUT _ = µa, Q logic inputs = V or VCC = 5.5V 2 7 Thermal Shutdown 16 C Power-On Reset V Power-On Reset Hysteresis 14 mv DIGITAL INPUTS (,,, LVL, A, A1, A2, RE, ) = 3.3V 2. Input Logic-High Voltage V IH = 5V 2.4 µa V = 3.3V.6 Input Logic-Low Voltage V IL = 5V.8 V Input Logic Hysteresis V HYST 15 mv Input Leakage Currents I LEAK Input voltages = V or 5.5V µa C IN Input Capacitance C IN 5 pf DIGITAL OUTPUT () Low Voltage V OL I SINK = 6mA.4 V High Voltage V OH I SOURCE =.5mA -.5 V RELAY OUTPUT DRIVERS ( ) OUT_ Drive Current = 2.7V 7 = 4.5V 7 ma OUT_ On-Resistance R ON = 2.7V 2 6 Ω OUT_ Voltage V OUT _ = 3.V, I OUT _ = 7mA.4 V I OUT Off-Leakage Current I LEAK V OUT _ =, all outputs off µa Kickback Diode Forward Voltage V FORW I OUT _ = 15mA (Note 3) 1.5 V 2 Maxim Integrated

3 3.3V/+5V, 8-Channel, Cascadable Relay Drivers ELECTRICAL CHARACTERISTI (continued) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SPI TIMING (MAX482) Turn-On Time (OUT_) t ON From rising edge of, R L = 5Ω, C L = 5pF MAX482/MAX4821 ( = +3V to +5.5V, V =, T A = -4 C to +85 C, unless otherwise noted. Typical values are at T A = +25 C.) (Note 2) 1. µs Turn-Off Time (OUT_) t OFF From rising edge of, R L = 5Ω, C L = 5pF 1. µs Frequency f 2.1 MHz Cycle Time t CH + t CL 48 ns Fall to Rise Setup t S 24 ns Rise to Hold t H 24 ns High Time t CH 19 ns Low Time t CL 19 ns Data Setup Time t DS 1 ns Data Hold Time t DH ns Fall to Valid t DO 5% of to 1% of, C L = 5pF ns Rise Time (,,,, RE) Fall Time (,,, RE, ) t SCR 2% of to 7% of, C L = 5pF 2 µs t SCF 2% of to 7% of, C L = 5pF 2 µs RE Min Pulse Width t RW 7 ns Min Pulse Width t SW 7 ns PARALLEL TIMING (MAX4821) Turn-On Time t ON From rising edge of, R L = 5Ω, C L = 5pF 1 µs Turn-Off Time t OFF From rising edge of, R L = 5Ω, C L = 5pF 1 µs LVL Setup Time t LS 1 ns LVL Hold Time t LH ns Address to Setup Time t AH 1 ns Address to Hold Time t AS ns Rise Time (A2, A1, A, LVL) t SCR 2% of to 7% of, C L = 5pF 2 µs Fall Time (A2, A1, A, LVL) t SCF 2% of to 7% of, C L = 5pF 2 µs RE Pulse Width t RW 7 ns Pulse Width t SW 7 ns Note 2: Specifications at -4 C are guaranteed by design and not production tested. Note 3: After relay turn-off, inductive kickback may momentarily cause the voltage at OUT_ to exceed V. This is considered part of normal operation and will not damage the device. Maxim Integrated 3

4 MAX482/MAX4821 Typical Operating Characteristics (V =, T A = -4 C to +85 C, unless otherwise noted. Typical values are at T A = +25 C.) 25 2 SUPPLY CURRENT vs. SUPPLY VOLTAGE ALL LOGIC INPUTS = MAX482 toc = 5V SUPPLY CURRENT vs. TEMPERATURE = 5.5V MAX482 toc SUPPLY CURRENT vs. INPUT LOGIC VOLTAGE ALL LOGIC INPUTS CONNECTED MAX482 toc3 SUPPLY CURRENT (μa) SUPPLY CURRENT (μa) = 2.3V = 3.3V SUPPLY CURRENT (μa) = 5V = 3.3V SUPPLY VOLTAGE (V) TEMPERATURE ( C) INPUT LOGIC VOLTAGE (V) RON (Ω) ON-RESISTANCE vs. SUPPLY VOLTAGE I OUT_SINK = 7mA MAX482 toc4 RON (Ω) I OUT_SINK = 7mA = 2.3V ON-RESISTANCE vs. TEMPERATURE = 5.5V = 3.3V = 5V MAX482 toc5 POWER-ON RE VOLTAGE (V) POWER-ON RE VOLTAGE vs. TEMPERATURE MAX482 toc SUPPLY VOLTAGE (V) TEMPERATURE ( C) TEMPERATURE ( C) OUTPUT OFF-LEAKAGE (na) OUTPUT OFF-LEAKAGE CURRENT vs. SUPPLY VOLTAGE SUPPLY VOLTAGE (V) MAX482 toc7 OUTPUT OFF-LEAKAGE (na) OUTPUT OFF-LEAKAGE CURRENT vs. TEMPERATURE = 5V = 5.5V.25 = 3.3V TEMPERATURE ( C) = 2.3V MAX482 toc8 ton/toff DELAY TIME (ns) OUT_ TURN-ON/TURN-OFF DELAY TIMES vs. SUPPLY VOLTAGE t OFF t ON SUPPLY VOLTAGE (V) R L = 5Ω C L = 5pF MAX482 toc9 4 Maxim Integrated

5 3.3V/+5V, 8-Channel, Cascadable Relay Drivers (V =, T A = -4 C to +85 C, unless otherwise noted. Typical values are at T A = +25 C.) INPUT LOGIC THRESHOLD BACK EMF CLAMPING vs. SUPPLY VOLTAGE WITH STANDARD 3V RELAY 2.5 THIN QFN INPUT LOGIC THRESHOLD (V) MAX TSSOP PIN SUPPLY VOLTAGE (V) THIN QFN MAX4821 TSSOP MAX482 toc1 NAME MAX482/MAX4821 Typical Operating Characteristics (continued) OUT_ TURNS OFF FUNCTION 2μs/div MAX482 toc11 = 3.3V V 5V/div OUT_ 1V/div Pin Description RE Reset Input. Drive RE low to clear all latches and registers (all outputs are turned off). RE overrides all other inputs. If RE and are pulled low at the same time, then RE takes precedence. Chip-Select Input. MAX482: Drive low to select the device. When is low, data at is clocked into the 8-bit shift register on s rising edge. Drive from low to high to latch the data to the registers and activate the appropriate relays. MAX4821: Drive low to select the device and set level on LVL. Drive from low to high to latch the address and level data to the output. 3 5 Serial-Data Input 4 6 Serial-Clock Input N.C. No Connection Ground OUT7 1, 16 12, 18 1, 16 12, OUT6 Serial-Data Output. is the output of the 8-bit shift register. This output can be used to daisy chain multiple MAX482s. The data at appears synchronous to s falling edge. Open-Drain Output 8. Connect to the low side of a relay coil. This output is pulled to when activated, but otherwise is high impedance. Open-Drain Output 7. Connect OUT7 to the low side of a relay coil. This output is pulled to when activated, but otherwise is high impedance. Power Ground. is a return for the output sinks. Connect pins together and to. Open-Drain Output 6. Connect OUT6 to the low side of a relay coil. This output is pulled to when activated, but otherwise is high impedance. Maxim Integrated 5

6 MAX482/MAX4821 Pin Description (continued) THIN QFN MAX482 TSSOP PIN THIN QFN MAX4821 TSSOP NAME FUNCTION OUT OUT OUT OUT2 Open-Drain Output 5. Connect OUT5 to the low side of a relay coil. This output is pulled to when activated, but otherwise is high impedance. Common Free-Wheeling Diodes. Connect to. can also be connected to a separate supply that is higher than. In that case, bypass to with a.1µf capacitor. Open-Drain Output 4. Connect OUT4 to the low side of a relay coil. This output is pulled to when activated, but otherwise is high impedance. Open-Drain Output 3. Connect OUT3 to the low side of a relay coil. This output is pulled to when activated, but otherwise is high impedance. Open-Drain Output 2. Connect OUT2 to the low side of a relay coil. This output is pulled to when activated, but otherwise is high impedance Open-Drain Output 1. Connect to the low side of a relay coil. This output is pulled to when activated, but otherwise is high impedance Input Supply Voltage. Bypass to with a.1µf capacitor LVL Set Input. Drive low to set all latches and registers high (all outputs are turned on). overrides all parallel and serial control inputs. RE overrides under all conditions. Level Input. LVL determines whether the selected address is switched on or off. A logic high on LVL switches on the addressed output. A logic low on LVL switches off the addressed output. 4 6 A Digital Address Input. (See Table 2 for address mapping.) 5 7 A1 Digital Address 1 Input. (See Table 2 for address mapping.) 6 8 A2 Digital Address 2 Input. (See Table 2 for address mapping.) EP Exposed Pad. Connect exposed pad to. Detailed Description The MAX482/MAX channel relay drivers offer built-in kickback protection and drive +3.3V/+5V nonlatching or dual-coil-latching relays. These devices are especially useful when driving +3V relays. Each independent open-drain output features a 2Ω on-resistance and is guaranteed to sink 7mA (min) load current. Both devices consume less than 5µA (max) quiescent current and feature 1µA (min) output off-leakage current. The MAX482 features an SPI/QSPI/MICROWIRE-compatible serial interface. Input data is shifted into an 8-bit shift register and latched to the outputs when transitions from low to high. Each data bit in the shift register corresponds to a specific output, allowing independent control of all outputs. The MAX4821 features a 4-bit (A, A1, A2, LVL) parallel input interface. The three bits (A, A1, A2) determine the output address, and LVL determines whether the selected output is switched on or off. Data is latched to the outputs when transitions from low to high. Both devices feature separate set and reset functions that allow the user to turn on or turn off all outputs simultaneously with a single control line. Built-in hysteresis (Schmidt trigger) on all digital inputs allows this device to be used with slow rising and falling signals, such as those from optocouplers or RC power-up initialization circuits. The MAX482/MAX4821 are available in 2-pin TSSOP and space-saving 2-pin Thin QFN packages. 6 Maxim Integrated

7 MAX482/MAX V/+5V, 8-Channel, Cascadable Relay Drivers t W t S t CL t CH t H t O t DS t DH D7 D6 D1 D t DO t ON, t OFF OUT_ Figure 1. 3-Wire Serial-Interface Timing Diagram (MAX482 only) Table 1. Serial Input Address Map (MAX482 Only) D D1 D2 D3 D4 D5 D6 D7 OUT_ OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 Digital Interface Serial Interface (MAX482) The serial interface consists of an 8-bit shift register and parallel latch controlled by and. The input to the shift register is an 8-bit word. Each data bit controls one of the eight outputs, with the most significant bit (D7) corresponding to and the least significant bit (D) corresponding to (see Table 1). When is low (device is selected), data at is clocked into the shift register synchronously with s rising edge. Driving from low to high latches the data in the shift register to the parallel latch. is the output of the shift register. Data appears on synchronously with s falling edge and is identical to the data at delayed by eight clock cycles. When shifting the input data, D7 is the first bit in and out of the shift register. While is low, the switches always remain in their previous state. Drive high after 8 bits of data have been shifted in to update the output state and inhibit further data from entering the shift register. When is high, transitions at and have no effect on the output, and the first input bit (D7) is present at. If the number of data bits entered while is low is greater or less than 8, the shift register contains only the last 8 data bits, regardless of when they were entered. The 3-wire serial interface is compatible with SPI, QSPI, and MICROWIRE standards. The latch that drives the analog switch is updated on the rising edge of, regardless of s state. Parallel Interface (MAX4821) The parallel interface consists of three address bits (A, A1, A2) and one level selector bit (LVL). The address bits determine which output is updated, and the level bit determines whether the addressed output is switched on (LVL = high) or off (LVL = low). When is high, the address and level bits have no effect on the state of the outputs. Driving from low to high latches the address and level data to the parallel register and updates the state of the outputs. Address data entered after is pulled low is not reflected in the state of the outputs following the next low-to-high transition on (Figure 2). Maxim Integrated 7

8 MAX482/MAX4821 A_ LVL V OUT t AS t LS t AH t LH t ON, t OFF Figure 2. Parallel Interface Timing Diagram (MAX4821 only) Table 2. Parallel Interface Address Map (MAX4821 Only) A2 A1 A OUTPUT Low Low Low Low Low High OUT2 Low High Low OUT3 Low High High OUT4 High Low Low OUT5 High Low High OUT6 High High Low OUT7 High High High /RE Functions The MAX482/MAX4821 feature set and reset inputs that allow the user to simultaneously turn all outputs on or off using a single control line. Drive low to set all latches and registers to 1 and turn all outputs on. overrides all serial/parallel control inputs. Drive RE low to clear all latches and registers and turn all outputs off. RE overrides all other inputs, including. Applications Information Daisy Chaining The MAX482 features a digital output,, that provides a simple way to daisy chain multiple devices. This feature allows the user to drive large banks of relays using only a single serial interface. To daisy chain multiple devices, connect all pins together, and connect the of one device to the of another device (see Figure 3). During operation, a stream of serial data.1μf.1μf.1μf MAX482 MAX482 MAX482 Figure 3. Daisy-Chain Configuration 8 Maxim Integrated

9 MAX482/MAX V/+5V, 8-Channel, Cascadable Relay Drivers is shifted through all the MAX482s in series. When goes high, all outputs update simultaneously. The MAX482 can also be used in a slave configuration that allows the user to address individual devices. Connect all the pins together, and use the input to address one device at a time. Drive low to select a slave and input the data into the shift register. Drive high to latch the data and turn on the appropriate outputs. Typically, in this configuration only one slave is addressed at a time. Inductive Kickback Protection The MAX482/MAX4821 feature built-in inductive kickback protection to reduce the voltage spike on OUT_ generated by a relay s coil inductance when the output is suddenly switched off. Internal diodes connected from each output to allow the inductor current to flow back to the supply. Connect the common cathode () of the internal protection diodes to. also can be connected to a higher voltage than (+6V max) for faster kickback recovery. In this configuration, bypass to with a.1µf capacitor. Relay Manufacturers PANY PHONE WEBSITE Aromat Corp CP Clare Corp Coto Techonology Deustch Relays, Inc Fujitsu Takamisawa Hella KG Hueck PANY PHONE WEBSITE NEC Electronics, Inc. Omron Electronics, Inc. Rockwell/Allen- Bradley Siemens Electromechanical Component, Inc Teledyne Relays Typical Application Circuits.1μF.1μF RE RELAY COIL 1 RE RELAY COIL 1 CLK MAX482 RELAY COIL 8 A A1 A2 MAX4821 RELAY COIL 8 LVL Maxim Integrated 9

10 MAX482/MAX4821 Functional Diagrams MAX482 RE OUT2 OUT3 OUT4 8-BIT SHIFT REGISTER PARALLEL REGISTER OUT5 OUT6 OUT7 MAX4821 RE OUT2 OUT3 OUT4 LVL A2 A1 4-TO-8 DECODER PARALLEL LATCH OUT5 OUT6 OUT7 A 1 Maxim Integrated

11 MAX482/MAX V/+5V, 8-Channel, Cascadable Relay Drivers Pin Configurations (continued) TOP VIEW RE LVL A A VCC OUT MAX4821 *EP OUT3 OUT4 OUT5 OUT6 RE N.C MAX OUT2 OUT3 OUT4 OUT5 OUT6 RE LVL A A1 A MAX OUT2 OUT3 OUT4 OUT5 OUT6 6 A OUT *EP OUT7 9 1 *EP OUT7 THIN QFN TSSOP TSSOP *CONNECT EP TO. PROCESS: BiCMOS Chip Information Package Information For the latest package outline information and land patterns, go to Note that a +, #, or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 2 TQFN-EP T TSSOP-EP U2E Maxim Integrated 11

12 MAX482/MAX4821 REVISION NUMBER REVISION DATE DESCRIPTION Revision History PAGES CHANGED 1/3 Initial release. 1 4/9 Corrected error in the Electrical Characteristics table. 2 1/1 Added exposed pad to TSSOP package in the Ordering Information, Pin Description, and Pin Configurations. 1, 2, 3, 5, 11, 12, 13 Added Reflow Temperature to the Absolute Maximum Ratings section. 2 1, 6, 11 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. 12 Maxim Integrated 16 Rio Robles, San Jose, CA USA Maxim Integrated The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.

13 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Maxim Integrated: MAX482EUP+ MAX4821EUP+ MAX482ETP+ MAX482EUP+T MAX4821ETP+ MAX4821ETP+T MAX4821EUP+T MAX482ETP+T