The ultimate lock-in performance: sub-ppm resolution

Transcription

1 Electrical characterisation o nanoscale samples & biochemical interaces: methods and electronic instrumentation The ultimate lock-in perormance: sub-ppm resolution Giorgio Ferrari Dipartimento di elettronica, inormazione e bioingegneria Politecnico di Milano Milano, November 3 06 OUTLOOK o the LESSON Limits o standard LIA and o dierential approach Ratiometric technique ELIA: Enhanced Lock-In Ampliier

2 Resolution limits o LIAs out in LIA = MHz LIA Output Spectral analysis (see previous lesson) Zurich Instruments, HFLI Resolution = Noise / Signal Output spectral density [V/Hz] 00µ 0µ µ 00n = 0 V Eq. input noise o the input channel 0 00 k 0k 00k Frequency [Hz] Resolution [ppm] k m khz BW (ideal) 0 Hz BW (ideal) m 0m 00m Signal amplitude [V] 3 Resolution limits o LIAs out in LIA = MHz LIA Output Spectral analysis (see previous lesson) Zurich Instruments, HFLI Resolution = Noise / Signal Output spectral density [V/Hz] 00µ 0µ µ 00n = V = 300 mv = 00 mv = 30 mv = 0 V 0 00 k 0k 00k Frequency [Hz] Resolution [ppm] k m khz BW (ideal) khz BW 0 Hz BW (ideal) 0 Hz BW m 0m 00m Signal amplitude [V] 40 4

3 A common limit or high-speed LIA Model Maximum requency [MHz] Signal amplitude [V] Measurement requency [MHz] Relative resolution [ppm] Custom LIA [46] 0. 0., 0.3, 0.0, 0.05 SR , 0.3, 0.0, 0.05 MCL SR Custom LIA [4] , 0., 0.3, 0., 9 HFLI , 0., 0.3, 0.,, Drawbacks o the dierential approach Generation o the reerence path Well-matched dierential sensor Circuit with a reerence component Calibration Spectroscopy (requency, temperature, bias, ) is diicult Custom solutions are commonly required: no plug & measure 6 3

4 How to improve the resolution? The limiting actor is the gain luctuations given by: stimulus source, ampliiers, Dierential approach: Δ I S << S (Re S) Out noise,di << Out noise Ratiometric approach: independent o G+G(t)! Additional bonus: no matching constraint! i Re = (cable connecting the output to the input): 7 Analog implementation cosω A s cos(ω s t) C F M A s cos(ω s t) C x A s cos(ω s t) M + G Independent o A s! Integrator stage or ampliication and iltering 8 4

5 Analog implementation: problems sin(ω s t) In-phase & in-quadrature components: A A Analog multiplier noise C F A s cos(ω s t) cos(ω s t) en 9 / noise o the multiplier is important! Digital implementation A STIM, A = A STIM T V OUT LIA STIM G DAC [ + n DAC (t)] DAC G [ + n (t)] G [ + n (t)] F P G A Two digital LIAs to calculate A, A STIM 0 5

6 Digital implementation: single A STIM, A = A STIM T V OUT LIA STIM G DAC [ + n DAC (t)] DAC G [ + n (t)] SW F P G A Reconstruction o the s and LIAs to calculate A, A STIM Single Fast selection o the input (SW) Digital implementation: single A STIM, A = A STIM T V OUT LIA STIM G DAC [ + n DAC (t)] DA C G [ + n (t)] AD C SW F P G A Reconstruction o the s and LIAs to calculate A, A STIM gain time 6

7 Digital implementation: single A STIM, A = A STIM T V OUT LIA STIM s =/T sw G DAC [ + n DAC (t)] DA C G [ + n (t)] AD C SW F P G A Reconstruction o the s and LIAs to calculate A, A STIM gain digital reconstruction gain gain time STIM digital reconstruction 3 T sw time time Digital implementation: single A STIM, A = A STIM T V OUT LIA STIM =/T sw G DAC [ + n DAC (t)] DA C G [ + n (t)] AD C SW F P G A Reconstruction o the s and LIAs to calculate A, A STIM gain T sw<< T luctuations digital reconstruction gain gain time STIM digital reconstruction 4 T sw time time 7

8 From a single to two s Disadvantages o the single solution: sw has to be high in order to avoid aliasing eects! Ex.: max =0MHz, sampling =50MS/s = sw = 00MS/s ppm switching transients in less than 0ns! Can we reduce the switching requency? Gain luctuations are important in the s ms time scale Slow switching o TWO s or continuous acquisition 5 Enhanced-LIA (ELIA) V OUT ELIA DAC cos DDS Digital processing D U T STIM SW t t Reconstructed s Amplitude extraction OUT SW t Amplitude extraction Digital ratiometric approach khz switching requency Reconstruction and demodulation 6 8

9 ELIA: time domain analysis Gain o the acquired s.05 Gain o the reconstructed s Time 0.95 Same mean gain! Time Enhanced Time Lock-in Ampliier - G. Ferrari Time ELIA: detailed analysis reconstructed in the digital domain s s time T sw / Analytical expression: 0 0 s 8 9

10 ELIA: requency domain s cos j π 0 0 sw 3 sw -3 sw - sw -3 sw - sw 0 0 sw 3 sw j 3π j π j 3π j 3π j π j π j 3π - c* 0 c* - c* 0 c* 9 ELIA: requency domain s cos j π 0 0 sw 3 sw -3 sw - sw -3 sw - sw 0 0 sw 3 sw : j 3π j π j 3π 4 j 3π j π j π j 3π sw 0 + sw 0

11 ELIA: demodulated s : sw, - sw 0 +sw : 4 - sw 0 + sw ELIA: demodulated s : ± sw, - sw 0 +sw and STIM have the same luctuations i: SW > c* +BW avoid harmonics: : ( + k) SW 0 (k=0,,, ) 4 - sw 0 + sw

12 ELIA: HW implementation OUT 50 Ω 0.85 pf kω - + THS300 3 kω 300 Ω SWITCH 3 kω - OPA kω kω kω 50 Ω 50 Ω 30 pf 30 pf 0 kω DAC THS567A kω SWITCH THS700 - Preamp PGA + SWITCH 374 Ω 5 pf 47 pf ŌPA Ω 540 nh 5 Ω 3 Ω 540 nh 58 pf - AD Ω ADG75 V REF ADS554 IN 3 THS700 - Preamp PGA + SWITCH 374 Ω 5 pf 47 pf ŌPA Ω 3 Ω 540 nh 540 nh 58 pf - AD Ω 5 Ω V REF ADS554 ELIA: irmware implementation Switches network DAC Adder m 8 STIM T SW cos m 7 m 6 m 5 DDS sin Delay 0 n 8 n 7 n 6 n 5 m 4 m 3 STIM Digital architecture Switches control n 4 n 3 m m n n -sin cos cos x jy jy x Amp. OUT Amp. STIM 4

13 ELIA prototype FPGA: Xilinx Spartan 6 (Opal Kelly module) &DAC: 80MS/s Maximum AC requency: 0MHz Output: 50V 0V Input range: ±00mV - ±0V 5 Operating modes: Two channels LIA ELIA Switching transients 500m 400m Amplitude [V] 300m 00m 00m 0-00m reconstructed reconstructed STIM -00m n 00.0n 300.0n 400.0n T s =.5 ns Time [s] 6 3

14 Experimental validation 7 Switching requency Output noise (ppm) single channel mode ELIA resolution vs sw (BW = Hz) Noise spectral density [ppm/hz] 0 0. ELIA single channel * c 0 00 k 0k Frequency [Hz] Resolution [ppm] 0 ELIA 0 00 k 0k Switching requency [Hz] sw must be > c * ( no gain luctuation during T Sw ) 8 4

15 Assessment o the resol. capabilities kω 48 MΩ T=0 s V OUT LIA 5 ppm modulation o the input voltage 0. V OUT Normalized resistance [0 ppm/div] Detection o tiny 5 ppm variations Zurich HFLI (39 ppm) ELIA single channel (9 ppm) ELIA (0.6 ppm) ilter BW = Hz Time [s] Noise spectral density [ppmz] Zurich HFLI ELIA single channel ELIA 0m 00m 0 00 k Frequency [Hz] 9 High resolution spectroscopy Resolution [ppm] 30 kω 400 pf k 00 0 V OUT LIA module [db] -6 - Zurich Inst. HFLI ELIA single Channel ELIA 0 TF module TF phase 00 k 0k 00k M 0M Frequency [Hz] Antialiasing 00 k 0k 00k M 0M ilter? Frequency [Hz] phase [Degree] Resolution is insensitive to phase and module o V in! 5

16 Comparison Model Maximum requency [MHz] Signal amplitude [V] Measurement requency [MHz] Relative resolution [ppm] Custom LIA [7] 0. 0., 0.3, 0.0, 0.05 SR830 (Stanord Research Systems) MCL-540 (SynkTek) SR865 (Stanord Research Systems) 0. 0., 0.3, 0.0, Custom LIA [] , 0., 0.3, 0., 9 HFLI (Zurich Instruments) Enhanced-LIA (Section 5) , 0., 0.3, 0.,, , 0.3, Summary Gain luctuations reduced by a ratiometric approach Two s or continuous acquisition Inputs switched every ms Sub-ppm resolution up to 6MHz No external components Plug & measure No calibration Acknowledgements: G. Gervasoni Patent pending G. Gervasoni, M. Carminati, G. Ferrari, Lock-In Amplier Architectures or Sub-Ppm Resolution Measurements, in Advanced Interacing Techniques or Sensors, Springer, in press 3 6