Y. Tsiatouhas. VLSI Systems and Computer Architecture Lab. Low Power Design Techniques II 2

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CMOS INTEGRATED CIRCUIT DESIGN TECHNIQUES University of Ioannina

1 CMOS INTEGRATED CIRCUIT DESIGN TECHNIQUES University of Ioannina Low Power Design Techniques II Dept. of Computer Science and Engineering Y. Tsiatouhas CMOS Integrated Circuit Design Techniques Overview. Dynamic power consumption reduction. Architecture level power reduction 3. Short circuit powerconsumption reduction VLSI Systems and Computer Architecture Lab Low Power Design Techniques II

2 Dynamic Power Consumption I V i (t) V V o (t) V t r t f t V V o I D (t) t t V i C L I Dn I Dp Low Power Design Techniques II 3 Dynamic Power Consumption II V The mean dynamic power consumption for an input pulse with frequency f p = /t p is provided by: t p V i V o C L P d t p t / 0 t p p in(t)vo (t)dt ip(t)(v p t t / p V (t))dt o Given that: dv(t) i(t) C dt C V 0 L L d VodVo t 0 V p t p P C (V V )d(v o p CL V Vo ) t p L f C V Low Power Design Techniques II 4

3 Dynamic Power Consumption Reduction Low Power Design Techniques II 5 Technology Scaling A new CMOS technology every 3 years. Technology scales down by a factor κ=/α0.7 W= κw, L=κL V = κv, V th =κv th t ox = κt ox C ox = ε ox / t ox = C ox / κ I D = μ n C ox W/L(V V th ) = (/κ)(κ/κ)(κ) Ι D = κi D C gate = C ox WL = (/κ)(κ)(κ)c gate = κc gate C wire ( L) = κc wire Delay = CV / I D = (κ. κ /κ)delay = κdelay Energy =CV = κ 3 Energy Power=Energy/ Delay = κ Power EnergyDelay = κ 4 (Energy Delay) Low Power Design Techniques II 6 3

4 P d f p C L V Power Supply V Reduction Since: the reduction of V will result in significant power consumption reduction (square low). However, the power supply reduction will result in the increment of the circuit signal propagation delays. To confront with this drawback, the following techniques are proposed : Threshold voltage V th reduction (but static power is increased). Use of reduced threshold voltage V th only for the gates at time (performance) critical signal paths in the circuit. Use of multi power supplies or an adaptive power supply V. Exploitation of pipeline design techniques or other parallelism design schemes for the reduction of the signal propagation delay. Low Power Design Techniques II 7 V V t Scaling Scenarios V V V V t V t V t Low Power Design Techniques II 8 4

5 Scaling Strategies V Reduction and Performance Constant Voltage Scaling Generalized Scaling α is the scaling factor while α/ε is the reduced scaling factor Influence of V on the current I D and propagation delay t d : D I k V V s th where s is the velocity saturation index ( < s < ). C V td k V s Vth Low Power Design Techniques II 9 Power Supply V Scaling (I) For s = Metric Propagation Deley Energy Energy Delay 3 C V td E C V C V E td I D k V V th h I D k V Vth 3 V C V E td γ td V Vth k V V th 3 td V Vth 3 V V V Vth γ 4 dv V V d E Metric Minimization td VV 3Vth γ dv V V 3 d E th th The derivative is vanished for V =3V th Low Power Design Techniques II 0 5

6 Power Supply V Scaling (II) Low Power Design Techniques II Low Voltage Oriented Design (I) Bootstrapped Driver.5V.5V.5V 0.56V 0V.5V 0V 0V.5V 0V 0.56V.5V 9V.9V.9V 5V.5V 0V Typical V : 5V Technology: 0.8μm TW V tp = 0.9V V tn = 0.75V C bp = 0.35pF C bn = 0.5pF J. Lou, J. Kuo, IEEE J. Solid State Circuits, 3() 997 Low Power Design Techniques II 6

7 Low Voltage Oriented Design (II) Low Power Design Techniques II 3 C L Transistor Size Scaling (Ι) 3 I NC ref. C g =NC ref. Let us consider a reference design with transistor sizes W/L so that the input (transistor gate related) capacitance is C ref. Initially, the power supply is V ref. ' I κ (NC ref C p =C wire + C junct ) (V ref V ) t Vref td (Cp NCref) I (Cp NCref) V td κ (NC ) (V V ) ref ref V td κ( α Ν) (V ref t ref ref V t) Aiming to reduce the dynamic power consumption, we reduce the power supply voltage to V N. This will result in the increment of the propagation delay time of the circuit. In order to recover the operating speed, we decide to increase (scale up) the transistor sizes in the design by a factor N (our target is to reduce the propagation t d ). Is this approach applicable and if yes which is the proper N factor? α C C p ref Chandrakasan et.al., IEEE J. Solid State Circuits, 7(4) 99 Low Power Design Techniques II 4 7

8 E ( E N) I NC ref. () Transistor Size Scaling (ΙΙ) For each N value, there is a proper power supply C g =NC ref. voltage V N where both designs (the reference & the scaled one) exhibit the same speed performance. Given that the propagation p delay t d increases with C p =C wire + C junct. /V ref (V th <<)*, the V N voltage for which the t d of the scaled design is equal to this of the reference design (Ν=), is provided by: α = C p C ref ( α N) VN V α d ref t κ (N) V V ref α κ α N Consequently, for every N, the energy consumption at the first stage is given by: ref * V N Ν E(N) (C NC p ref )V N 3 NCref( α N) V α ref Low Power Design Techniques II 5 4 Multiple Power Supplies Selective use of a lower than V power supply voltage in order to reduce the dynamic power consumption. Maximum Propagation Delay Voltage Recovery Flip Flops Use of a single threshold voltage V th for the transistors in the design The shaded logic gates are fed with a lower voltage V L. The shaded Flip Flops recover the signal voltage level V H V at the output. Note that when a logic block is fed with a lower than V voltage, then every subsequent block up to the recovery Flip Flops must be fed with the same voltage level. Low Power Design Techniques II 6 8

9 Voltage Level Recovery Flip Flop Flop Slave Latch Level Conversion Flip Flop Zhang et.al., IEEE ISLPED, 998 Low Power Design Techniques II 7 Implementation of a Multi V Scheme V,high (shared) V,high cells (shared) V,low cells V,low (shared) V,low cells (shared) (a) V,high V,high cells (shared) (b) Low Power Design Techniques II 8 9

10 The Power Saving Capability Case of an inverter driving 0fF load. Width reduction Voltage reduction T Circuits with the distribution () can be the result of a timing driven place and route tool with power optimization. These tools reduce the transistors widths to gain in power. However, which is the best strategy? To reduce the transistors widths in the sub critical paths using a single power supply in the whole design or to reduce the power supply for the gates of the sub critical paths leaving the transistors widths unaltered? The second approach seems to provide better results! Low Power Design Techniques II 9 Multiple Threshold Voltage Technologies 5 Global use of a lower than V power supply voltage in the design in order to reduce the dynamic energy consumption. Maximum Propagation Delay The shaded logic blocks have been designed using transistors with lower threshold voltage than the nominal technology threshold voltage, in order to retain the speed performance of the design. Low Power Design Techniques II 0 0

11 Threshold Voltage Impact on Energy Threshold voltage reduction Fixed 0MHz Static energy consumption reduction Dynamic energy consumption reduction Threshold voltage reduction Chandrakasan et.al., Proceedings of IEEE, 83(4) 995 Low Power Design Techniques II V th Reduction Issues Static power consumption increment of the weak inversion (subthreshold) leakage current. Circuit operation susceptibility on the V th variations. Demand for: increased threshold voltage V th at the idle (stand by) state adaptable threshold voltage V th at the normal mode of operation by adjusting the substrate bias. Dynamic & static power consumption reduction techniques Active Stand by Multiple V th Dual V th MTCMOS Variable V th V th hopping VTCMOS Multiple V Dual V Reverse V GS switch Variable V V hopping Low Power Design Techniques II

12 Impact of V & V th in Propagation Delay For s = V th = constant t d k C V V V th V = constant t V d C k V V V 3 V th th t V d th C k V V 3 V th The susceptibility of the propagation delay on V and V th variations is increased as V th is increased and V is decreased. The propagation delay variations is significantly increased for high V th and low V levels. This effect must be seriously considered in designs where multi threshold voltage and/or multi power supply techniques are used. Low Power Design Techniques II 3 Dynamic Voltage Frequency Scaling DVFS 6 High load & high performance operation f max and V max Low load operation f min and V max Low dynamic power operation f min and V min Power Down Mode Low static power operation f max and V max Low Power Design Techniques II 4

13 The Pair of Sources Concept Local power supply adjustment Each circuit block can operate either with the high V for high performance or with the low V for low power. Yield improvement option: the whole circuit may work in the low power mode (low V ) except possibly this circuit block(s) where the performance is affected by local variations (slow block(s)). In that case the circuit block is fed by the high V while the overall power consumption remains low. Low Power Design Techniques II 5 Signal Swing Reduction 7 Transmitter V V Receiver Channel In A In C L B Out The signal driver (transmitter) generates signals with swing between [V thn,v V thn ]. The sense amplifier (receiver) recovers the signal swing between [0, V ]. P f C L V V thn Zhang et.al., IEEE ISLPED, 998 Low Power Design Techniques II 6 3

Logic Family Selection 8 A B F Α Β F 0 0 0 0 0 0 0 CLK Α V Β F NOR Dynamic Gate C EFF =3/4C L In case that: p(a=)=/ &

14 Logic Family Selection 8 A B F Α Β F CLK Α V Β F NOR Dynamic Gate C EFF =3/4C L In case that: p(a=)=/ & p(b=)=/ p(f=)=/4 & p 0 = p(f=0)=3/4 Low Power Design Techniques II 7 9 Energy Recovery Low Power Design Techniques II 8 4

15 Energy Consumption (Ι) V F The required charge Q in order to charge the output node F (x=, Φ= 0 ) is given by the next equation : Q = CV () The required energy from the power supply is : x Φ NAND C Ε = QV =CV () Considering that the conducting pmos transistor and the capacitance C form an RC network, the charging current as a function of time is: t dq V RC i(t) e (3) dt R Low Power Design Techniques II 9 Energy Consumption (ΙI) The instantaneous power dissipation in the pmos transistor is: V P( (t) i (t)r e R t RC (4) The energy dissipation within a time duration Τ in order to charge the output node, is given by: E dissp T 0 P(t)dt T 0 V R e t RC dt CV e T RC CV T Consequently, the energy stored on C is provided by the following difference: (5) E bit E E dissp CV CV CV (6) Low Power Design Techniques II 30 5

16 Energy Consumption (ΙII) In the next transition of the clock signal Φ (x=, Φ= ) the stored energy on C will change frome bit to 0 and the difference between the initial and the final energy is dissipated on the equivalent resistances of the nmos transistors that discharge the output node. Thus, the total energy dissipation in a clock cycle is: E cycle E dissp E dissn CV CV CV E bit E (7) Consequently, the energy that is recovered back to the power supply within a clock cycle is zero (0): E rtn 0 Low Power Design Techniques II 3 Energy Recovery Principle (I) The previous discussion shows that during the charging of a node, the current asymptotically approaches 0 and the energy dissipation asymptotically approaches CV /. After a time duration of 3RC the output voltage isatthe 95% of its final voltage, the current is less than 5% of its initial value and the energy dissipation is at the 97.5% of its final value. Thus, after another 3RC time duration the circuit has almost reached its final state, so that for a total time interval of 6RC the transition is considered completed. Let us replace the power supply with a step voltage, where for the time interval from 0 to 3RC the voltage level is V / and from 3RC to 6RC the voltage levelis V. Then, theenergydissipation i ti will be: E dissp 3RC 0 P(t)dt 6RC 3RC V P(t)dt C V C CV 4 (8) Low Power Design Techniques II 3 6

17 Energy Recovery Principle (II) According to the previous analysis, stepwise voltage power supplies with more than two steps can be used in order to reduce further the energy dissipation. The next idea, is to consider a power supply that continuously varies (from 0V ) so that the charging current remains constant throughout the entire process: Then, the charging energy dissipation will be: Q CV i(t) (9) T T E dissp T i 0 (t)rdt R CV T T 0 RC dt CV T (0) Low Power Design Techniques II 33 Energy Recovery Principle (III) The same situation can take place during the discharging phase by continuously varying the power supply from V 0, so that the current remains constant. Thus, again the energy dissipation on the nmos transistor will be: RC Edissn CV T Consequently, the total energy dissipation turns to be : RC Ediss Ediss p Ediss n CV T By selecting a proper p T, the total energy dissipation can be less than the energy delivered within a cycle when constant power supplies are used : Ε=Ε bit =CV. The difference in the energy is: () () RC ΔE CV CV 0 (3) TRC T Low Power Design Techniques II 34 7

18 Energy Recovery Principle (IV) V F V F Standard CMOS C V F Energy Dissipation Optimized CMOS t x Φ Adiabatic Charge t Low Power Design Techniques II 35 The Adiabatic CMOS Technique Φ Adiabatic ΝΟΤ gate x F C x A possible solution in order to exploit the energy recovery principle p is to replace the power supply V with the clock signal Φ. This is a power clock. Provided that the power clock is dynamically adjusted to the constant current requirement an adiabatic charging is achieved and the energy dissipation follows equation (0). Low Power Design Techniques II 36 8

General Low Power Techniques 0 Clock Enable Α Β Clock Gating CLK Functional Block Flip Flop A B A B C D C D F Balanced signal paths F Data Gating Low Power Design Techniques II 37 The Adder Example

19 General Low Power Techniques 0 Clock Enable Α Β Clock Gating CLK Functional Block Flip Flop A B A B C D C D F Balanced signal paths F Data Gating Low Power Design Techniques II 37 The Adder Example Glitches or dynamic hazards highly contribute in the dynamic power consumption. The carry look ahead design technique for an adder, drastically reduces the presence of glitches with respect to a ripple carry design and consequently the energy dissipation but also improves the speed performance! Balanced signal paths Low Power Design Techniques II 38 9

20 FSM State Assignment The target is to reduce the signal transitions (3,4) (,4) (3,4) States duplication (cost = memory element) Single signal transitions Equivalent States Skias et.al., IEEE ICECS, 000 Low Power Design Techniques II 39 Charge Recycling in Signal Drivers ΙΝ and ΙΝ complementary signals. V OUT C IN IN CTRL V OUT C Bitzaros et.al., IEEE ISCAS, 997 Low Power Design Techniques II 40 0

21 Charge Recycling in NORA Logic V V CLKΜ M CLK M3 r=c p /C n MP M6 M5 IN MN Switch OUT CLK C n M CLK CLKΜ M4 CLΚ C p Recycle Phase r CLKM Evaluation Phase Precharge Phase Limniotis et.al., IEEE TCAS I, 53(), 006 Period Low Power Design Techniques II 4 3 Architecture Level Low Power Design Low Power Design Techniques II 4

Architecture Level Options f ref = T Critical path

Total switched capacitance = C ref V = V ref = 5V

V ref Low Power Design Techniques II 43 Parallel

5C ref V par = V ref /.7 Power: P=f ref /..5C ref. (V ref /.

22 Architecture Level Options f ref = T Critical path delay: Τ= T adder +T comp = 5ns f ref =/T=40MHz Total switched capacitance = C ref V = V ref = 5V Power: P=f ref. C ref. V ref Low Power Design Techniques II 43 Parallel Architectures f par T f par =/T=f ref / C par =.5C ref V par = V ref /.7 Power: P=f ref /..5C ref. (V ref /.7) =0.36P ref keeping the throughput constant! Low Power Design Techniques II 44

Solid State Circuits, 7(4) 99 Low Power Design Techniques II 45 Algorithm Selection Video Compression

23 Pipeline Architectures f par =/T=f ref C par =.C ref V par = V ref /.7 Power: P=f ref..c ref. (V ref /.7) =0.37P ref keeping the throughput constant! Chandrakasan et.al., IEEE J. Solid State Circuits, 7(4) 99 Low Power Design Techniques II 45 Algorithm Selection Video Compression Algorithm complexity By reducing the number of tasks (circuit activity) the energy dissipation is reduced. Low Power Design Techniques II 46 3

24 Short Circuit Power Consumption Low Power Design Techniques II 47 Short Circuit Power Consumption V V i V o C L During the transition time from to V and vice versa and as input voltage V i is within the interval V tn <V i <V V tp a direct current from V to the exists. Low Power Design Techniques II 48 4

25 Short Circuit Power Consumption Reduction Low Power Design Techniques II 49 Short Circuit Consumption Reduction High load drivers Split Path Pth CMOS Buffer General principle: Signal rise and fall times must be equal! Low Power Design Techniques II 50 5

26 References Low Power Design Methodologies, J. Rabaey and M. Pedram, Springer, 997. Power Management of Digital Circuits in Deep Sub Micron CMOS Technologies, S. Henzler, Springer, 006. Low Power Digital VLSI Design, A. Bellaouar and M. Elmasry, Kluwer Academic Publishers, 996. A.5VFull Swing Bootstrapped CMOS Large Capacitive Load Driver Circuit Suitable for Low Voltage CMOS VLSI, J. Lou and J. Kuo, IEEE Journal of Solid State Circuits, vol. 3, no., pp.9, 997. A0.9 V, 50 MHz, 0 mw, 4mm, D Discrete Cosine Transform Core Processor with Variable Threshold Voltage (VT) Scheme, T. Kuroda et.al., IEEE Journal of Solid State Circuits, vol. 3, no., pp , Low Power CMOS Digital Design, A. Chandrakasan, S. Sheng and R. Brodersen, IEEE Journal of Solid State Circuits, vol. 7, no. 4, pp , 99. Minimazing Power Consumption in Digital CMOS Circuits, A. Chandrakasan, R. Brodersen, Proceedings of the IEEE, vol. 83, no. 4, pp , 995. Low Power Design Techniques II 5 6

Energy-Recovery CMOS Design

Energy-Recovery CMOS Design Jay Moon, Bill Athas * Univ of Southern California * Apple Computer, Inc. jsmoon@usc.edu / athas@apple.com March 05, 2001 UCLA EE215B jsmoon@usc.edu / athas@apple.com 1 Outline