High Speed Electronics and Photonics Group

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Jäckel Electronics Laboratory, IfE Swiss Federal Institute of

1 Electronics Laboratory, IfE Overview High Speed Electronics and Photonics Group Prof. Dr. H. Jäckel Electronics Laboratory, IfE Swiss Federal Institute of Technology ETHZ

2 Overview: High Speed Electronics and Photonics Group Electronics Laboratory, ETH Zürich Prof. H. Jäckel / Electronics Laboratory / ETH Zürich jaeckel@ife.ee.ethz.ch

5um @ 250nm Ø InP-based Tb/s Photonics sub-ps mode-locked diode lasers sub-ps all-optical switches 0.

3 Research Activities at the Electronics Laboratory InP Photonic Crystals for ultra dense Optical ICs Hole depth 3530nm 2μm Hole depth 2420nm 65-80nm CMOS for mm-wave RF and 40 Gb/s Electronics (ETH-IBM CASE Collaboration) Holes depth: 1μm 250nm Ø InP-based Tb/s Photonics sub-ps mode-locked diode lasers sub-ps all-optical switches GHz TWA in 80nm CMOS +200 Gb/s ICs with InP/GaAsSb Heterojunction Bipolar Transistors (in-house InP technology) 200mV /div, 2. 5ps /div Prof. H. Jäckel / Electronics Laboratory / ETH Zürich jaeckel@ife.ee.ethz.ch

4 High Speed Electronics: +200 Gb/s InP/GaAsSb DHBTs 40 Gb/s, 60 GHz CMOS Prof. H. Jäckel / Electronics Laboratory / ETH Zürich jaeckel@ife.ee.ethz.ch

Limits of Transistor Electronics: InP/GaAsSb DHBTs for 80

scaling into the 200nm range, 2) GaAsSb-type II base

Hydrodynamic Device Simulator Performance benchmarking with

Ring-oscillators, Frequency Dividers E w e,eff =0.

2 μm Current DHBT Data: 200 nm thick Collector, w e =0,7μm,

25V f max = 240 248 GHz @ j C =500 ka/cm 2 / U CE =1.

5 Limits of Transistor Electronics: InP/GaAsSb DHBTs for Gb/s Electronics 1) Vertical and lateral device scaling into the 200nm range, 2) GaAsSb-type II base Quantitative comparison to advanced 2-D nonstationary Hydrodynamic Device Simulator Performance benchmarking with simple demonstrators, eg. Ring-oscillators, Frequency Dividers E w e,eff =0.7μm B C w C =1.2 μm Current DHBT Data: 200 nm thick Collector, w e =0,7μm, l e =4-8μm f T = j C =500 ka/cm 2 / U CE =1.25V f max = j C =500 ka/cm 2 / U CE =1.25V U CE0 >2.5V β > Gb/s MUX 56 GHz Frequency-Phase Locked Loop VCO DRLM DRLM Prof. H. Jäckel / Electronics Laboratory / ETH Zürich jaeckel@ife.ee.ethz.ch 5

InP/GaAsSb DHBTs: towards 200-300 Gb/s ICs 1) 2-D hydrodynamic Type-I and II DHBT- and Circuit Simulations: Type I: InP/InGaAs/InP

77 ps t g B = 215 Gb/s (RO, MUX) Emitter Mesa Base Mesa Collector Mesa Base Undercut Sub Collector Emitter S E S gap Collector w e

6 InP/GaAsSb DHBTs: towards Gb/s ICs 1) 2-D hydrodynamic Type-I and II DHBT- and Circuit Simulations: Type I: InP/InGaAs/InP (graded) w e = 200nm ; w C =600nm ; d B =25nm ; d C =100nm f T = 570 GHz f max = 445 GHz = 1.77 ps t g B = 215 Gb/s (RO, MUX) Emitter Mesa Base Mesa Collector Mesa Base Undercut Sub Collector Emitter S E S gap Collector w e Contact Metal S BS S gap Undercut W E d C W C W B d B Type II: InP/GaAsSb/InP w e = 200nm ; w C =600nm ; d B =15nm ; d C =100nm (50) f T = 750 GHz f max = 600 GHz t g = 1.58 ps B = 245 (300) Gb/s (RO, MUX) S cut S w C C S cut 2) Scaling InP/GaAsSb technology toward submicron emitters w e 200nm: Base Emitter w e =200nm Air-bridge Width ~0.6μm 6 Collector 200nm Prof. H. Jäckel / Electronics Laboratory / ETH Zürich jaeckel@ife.ee.ethz.ch

4x10 Gb/s Transceiver Array in 90nm CMOS for

60 80nm CMOS for fiber-opics 27.07.2006 Prof.

7 4x10 Gb/s Transceiver Array in 90nm CMOS for short distance MMfiber links using AlGaAs VCSELs at 850nm (2.5mW/GHz) 50um multimode fiber / PCB waveguide Opt. Electrical In progress: 40 Gb/s receiver IC in 60 80nm CMOS for fiber-opics Prof. H. Jäckel / Electronics Laboratory / ETH Zürich jaeckel@ife.ee.ethz.ch

nm-scale CMOS for digital multi-10 Gb/s ICs mm-wave-applications from GHz to ~60 GHz

Wide Band (UWB) RF-Communication for LANs, WANs, 3-10 GHz CASE Center for Advanced

interconnects: Bypass Capacitors C OMP Capacitors TIA Bypass Capacitors 6 LAs Bypass

Buffer Bypass Capacitors Reference Input Clock Buffer I-Q Generator Clock Buffer and

Digital Loopfilter Analog Filter Bypass Caps Data Synchronization Bypass Caps Output

8 nm-scale CMOS for digital multi-10 Gb/s ICs mm-wave-applications from GHz to ~60 GHz for Mobile Com 10 and 40 Gb/s ICs for Fiberoptics (Transmitter / Receivers) Ultra Wide Band (UWB) RF-Communication for LANs, WANs, 3-10 GHz CASE Center for Advanced Silicon Electronics 40Gb/s 90nm CMOS TIA + LA, 26Gb/s Half-Rate CDR for Tb/s interconnects: Bypass Capacitors C OMP Capacitors TIA Bypass Capacitors 6 LAs Bypass Capacitors C OMP Capacitors 140μm High Resistive Substrate Bypass Capacitors Output Buffer Bypass Capacitors Reference Input Clock Buffer I-Q Generator Clock Buffer and Frequency Divider by 32 Bypass Caps Phase Interpolator Half-Rate Phase Detector Digital Loopfilter Analog Filter Bypass Caps Data Synchronization Bypass Caps Output Buffers 320 μm Prof. H. Jäckel / Electronics Laboratory / ETH Zürich jaeckel@ife.ee.ethz.ch

85 x 0.35 mm 2 26-42 GHz SOI CMOS Low Noise (4dB) Amplifier: Low power 4.

9 90nm CMOS for mm-wave RF-ICs Research Examples: 1-56 GHz CMOS 4-stage Travelling Wave Amplifier with 8 db Gain: In Out S 21 > 8dB from close to DC-59GHz S 21 = 9.7dB ± 1.7dB from 10-59GHz P -1dB,out = 20GHz V dc = 2V I dc = 66mA Size: 0.85 x 0.35 mm GHz SOI CMOS Low Noise (4dB) Amplifier: Low power 4.5 GHz UWB-Wavelet Generator: CASE Center for Advanced Silicon Electronics Prof. H. Jäckel / Electronics Laboratory / ETH Zürich jaeckel@ife.ee.ethz.ch

10 Photonic Integration for High Density, Multi-Functionality and Ultrahigh Speed in the InP-Material System Prof. H. Jäckel / Electronics Laboratory / ETH Zürich jaeckel@ife.ee.ethz.ch

11 Trends in Photonic Integration: Density Progress in Monolithic Photonic Integration: Status and Projections courtesy M.Smit, COBRA- TU Eindhoven Q-dot? PhC-resonator Quantum-Photonic Devices λ- and nano scale Nano-Photonics Photonic Crystals (bandgap WG) Photon Wire Circuits (high contrast WG) Micro-Photonics (low contrast WG) (Hybrid Integration) optical and electronic confinement Future optical / electronic Confinement Concepts for λ-scaled photonic devices: - strong guiding (photon wires) and periodic dielectrics (1-3D Photonic Crystals) current integration level modest typ. ~100 devices /cm - dispersion engineering (slow light) -2 device complexity high - Quantum Dots, nm-scaled optoelectronic materials Prof. H. H. Jäckel / / Electronics Laboratory / / ETH Zürich jaeckel@ife.ee.ethz.ch

12 Ultrafast Tb/s Photonics: Beyond the Speed of Transistor Electronics I Monolithically integrated 600fs mode-locked Diode Laser Prof. H. Jäckel / Electronics Laboratory / ETH Zürich jaeckel@ife.ee.ethz.ch

13 fs Mode-Locked Lasers Diodes Objectives for monolithic integration: MLLD for Tb/s-OTDM-systems require sub-ps optical pulses e.g. τ pulse 1000Gb/s size reduction, mechanical and temperature stability and high optical data rates State-of-the-Art: pulse width t pulse ~2ps at low f rep limited by slow saturable absorbers! ultra fast absorbers Functional Integration: SOA + passive WG + Interfaces + Absorber/Modulator conventional MLLD (with slow SOA-type absorber) Novel MLLD with UTC (Uni Travelling Carrier) absorber Passive Waveguide, SOA avoiding slow hole drift! [ for photodiodes T.Ishibashi et al., 2001] integration of a 3 rd device section! UTC Absorber Mode-locking conditions: E sat, absorber τ sat, absorber <E sat, SOA < τ sat, SOA Prof. H. H. Jäckel // Electronics Laboratory // ETH Zürich jaeckel@ife.ee.ethz.ch

Lateral MOCVD-Regrowth Process-Flow Technology choice: MOCVD

additional regrowth steps for UTC and passive WG Regrowth

gas pressure - MOCVD growth temperature - total growth thickness

SiO 2 -mask regrowth SiO 2 -mask passive WG UTC mask overhang, μm

regrowth: residual roughness SOA WG 1.5μm 25.01.2006 27.07.

14 Lateral MOCVD-Regrowth Process-Flow Technology choice: MOCVD lateral regrowth for freedom in layer composition 2 SiO 2 -masked additional regrowth steps for UTC and passive WG Regrowth challenges: optimization between - SiO 2 -mask under-etch - MOCVD gas pressure - MOCVD growth temperature - total growth thickness height of growth artefact layer etch SiO 2 -mask mask-underetch SiO 2 -mask regrowth SiO 2 -mask passive WG UTC mask overhang, μm Solution: 2-step growth of WG-core and top-cladding optimized regrowth: residual roughness SOA WG 1.5μm Prof. H. H. Jäckel / / Electronics Laboratory / / ETH Zürich jaeckel@ife.ee.ethz.ch

UTC-MLLD Fabrication Sequence I Top View: Schematic Cross-Section: UTC P-contact A SOA P-contact Waveguide UTC WG SOA B B' 5 4 5 P-InGaAs N-contact A' Bond pad N-contact Polyimide P-metallisation

Number of masks: 16 Number of growth: 5 MOCVD pressure: 30mb thick upper cladding 160mb thin lower waveguide Growth temperature: 630 0 C Total temperature cycle: 3h Completed UTC-MLLD for f rep = 40

15 UTC-MLLD Fabrication Sequence I Top View: Schematic Cross-Section: UTC P-contact A SOA P-contact Waveguide UTC WG SOA B B' P-InGaAs N-contact A' Bond pad N-contact Polyimide P-metallisation Polyimide Bond pad SEM-Cross-Section of 3-Section MLLD: InGaAsP active layer InGaAs contact layer InGaAsP waveguide p-inp InGaAsP etch stop UTC WG SOA UTC WG SOA 300nm Basic Process Data: Number of masks: 16 Number of growth: 5 MOCVD pressure: 30mb thick upper cladding 160mb thin lower waveguide Growth temperature: C Total temperature cycle: 3h Completed UTC-MLLD for f rep = 40 GHz: Fig.9a: SEM of butt-coupling UTC-WG Fig.9b: SEM of butt-coupling SOA-WG 1 = SOA growth 2 = UTC growth 4 = Waveguide cladding regrowth (undoped) 1a = Etch buffer 3 = Waveguide core (proposed, i.e. not grown on this sample) 1b = Etch stop regrowth 5 = P-Contact regrowth (doped) SOA-QW-bandgap shift: growth biasing ~ 0.8nm/growth-hour Growth mask: SiO 2 UTC WG SOA Prof. H. H. Jäckel / / Electronics Laboratory / / ETH Zürich jaeckel@ife.ee.ethz.ch

16 fs-pulse measurement and Simulation of UTC-MLLD Distributed time-domain model of hybrid mode-locked, 2-section UTC-MLLD with internal reflections (R=5%, L SOA =930mm, L UTC =70mm): multiple pulses temporal separation 1.6ps 2-L UTCr =140μm ps 2-photon absorption autocorrelation: UTC-MLLD: FFT of autocorr.: conventional MLLD: Autocorrelation (a.u.) 600fs Δf 3.2ps time, ps Δf=0.6THz=Mf rep M=L SOA /L UTC +1=14 Results: pulse width reduction ~4-5x to 600fs, small residual reflections are still present Prof. H. H. Jäckel // Electronics Laboratory // ETH Zürich jaeckel@ife.ee.ethz.ch time, ps

17 Densification of Optoelectronic Devices and OICs to the Wavelength scale InP-based Photonic Crystals Prof. H. H. Jäckel // Electronics Laboratory // ETH Zürich

Densification of optoelectronic InP-devices and OICs Solution: mm - cm-sized high devices contrast for OICs based WG, on low

bend Crystals reduce device size and interconnect area to a few 10λ 2 increase photon density and nonlinearities dispersion

~200n) air holes a~λ/2 planar WG (InP/InGaAsP/InP) dielectric Ref Substrate (InP) 5μm ETH, D. Erni M.K.Chin et al.

completeness - engineering CAD platforms - interconnection to fiber-world - active PhCs, contacting and current-injection Norm.

18 Densification of optoelectronic InP-devices and OICs Solution: mm - cm-sized high devices contrast for OICs based WG, on low contrast Photon waveguides Wires are or mainly Photonic interconnect-limited!bend Crystals reduce device size and interconnect area to a few 10λ 2 increase photon density and nonlinearities dispersion engineering slow light new device functions manipulation of electronic transitions 1μm air-holes (lattice constant a ~400nm, ~200n) air holes a~λ/2 planar WG (InP/InGaAsP/InP) dielectric Ref Substrate (InP) 5μm ETH, D. Erni M.K.Chin et al., 1999 Challenges: (High contrast PhC-membrane:) - nano-scale technology - competition against existing solutions - functional completeness - engineering CAD platforms - interconnection to fiber-world - active PhCs, contacting and current-injection Norm. frequency Photonic Bandgap Norm. propagation constant Low contrast PhC on substrate: current, voltage Prof. H. H. Jäckel // Electronics Laboratory // ETH Zürich jaeckel@ife.ee.ethz.ch

2D- and 3D-Simulation of planar, substrate-type PhCs - PhC functions are not very

(out-of-plane scattering neglected) - 3D-model are a reference but are too time consuming

constant ε Hole depth and out-of plane scattering: hole depth: 1.5um ETH, K.

5um air holes substrate air InP cladding (200nm) InGaAsP core (430nm) InP cladding (600nm)

InP/InGaAsP/InP WG high losses for W1-WG α~500 db/cm by 3D-FDTD 3D-(FDTD, SEMCAD TM ) vs.

19 2D- and 3D-Simulation of planar, substrate-type PhCs - PhC functions are not very intuitive need for fast engineering models - fast 2D-models not accurate enough (out-of-plane scattering neglected) - 3D-model are a reference but are too time consuming phenomenological 2D-model with hole scattering loss represented by complex dielectric constant ε Hole depth and out-of plane scattering: hole depth: 1.5um ETH, K. Rauscher hole depth: 2.5um air holes substrate air InP cladding (200nm) InGaAsP core (430nm) InP cladding (600nm) InP-Substrate hole etch depth ~3μm for passive, ~4μm for active PhCs for low contrast InP/InGaAsP/InP WG high losses for W1-WG α~500 db/cm by 3D-FDTD 3D-(FDTD, SEMCAD TM ) vs. 2D-(MMP)-simulation: the role of scattering losses Example: optimized power splitter: Prof. H. H. Jäckel / / Electronics Laboratory / /ETH Zürich jaeckel@ife.ee.ethz.ch

InP/InGaAsP-Photonic Crystals: Process Flow I 1

4 ICP-RIE of GaInAsP deposition PMMA patterning PMMA 3a

5μm Major Process Characteristics: - proximity corrected

PMMA thickness <300nm - SiN x /Ti hard-mask, max.

RIE etching of hard-mask - optimized Ar/Cl 2 /N 2 ICP

etching Cl 2 : chemical etching N 2 : hole sidewall

wall roughness and scattering losses - carrier lifetime

20 InP/InGaAsP-Photonic Crystals: Process Flow I 1 SiN/Ti-hard mask, EBL-resist 2 EBL+PEC 3 RIE of hardmask 4 ICP-RIE of GaInAsP deposition PMMA patterning PMMA 3a 3b 4 3.5μm Major Process Characteristics: - proximity corrected e-beam litho (30kV) - max. PMMA thickness <300nm - SiN x /Ti hard-mask, max. reliable etched thickness 400nm - SF 6 -, CHF 3 -based RIE etching of hard-mask - optimized Ar/Cl 2 /N 2 ICP cyclic etch chemistry for deep holes: Ar: physical etching Cl 2 : chemical etching N 2 : hole sidewall passivation, shape control Open Issues: - hole wall roughness and scattering losses - carrier lifetime reduction due to surface damage - hole etch tolerances Prof. H. H. Jäckel / / Electronics Laboratory / / ETH Zürich jaeckel@ife.ee.ethz.ch

k(ω)-, α-measurements - loss ~900dB/cm are state-of-the-art, but high compared to membranes (III-V, SOI) - 3D-FDTD-simulation:

21 Photonic Crystal Standing Wavemeter Scanning Nearfield Optical Microscope (SNOM)-Measurement of standing wave pattern in W1 PhC WG α: dispersion relation k(ω): attenuation SNOM set-up: Courtesy: Nano-Optics Group, ETH Results: - SNOM-wavemeter: precise k(ω)-, α-measurements - loss ~900dB/cm are state-of-the-art, but high compared to membranes (III-V, SOI) - 3D-FDTD-simulation: loss ~500dB/cm Prof. H. H. Jäckel // Electronics Laboratory // ETH Zürich jaeckel@ife.ee.ethz.ch

Interfacing Photonic Crystal: Power Splitter

interface to fibers-phcs shallow ridge (width=1.

5μm / h=3μm) WG PhC WG Optical EBL ridge WG

Alignment tolerance: optical - EBL Transmission

22 Interfacing Photonic Crystal: Power Splitter Mix&Match-lithography (optical and e-beam litho) interface to fibers-phcs shallow ridge (width=1.5μm / height=300nm) deep trench (w=0.5μm / h=3μm) WG PhC WG Optical EBL ridge WG trench ridge WG Optimized PhC-splitter: 2μm 10μm Alignment tolerance: optical - EBL Transmission measurement: 350nm alignment tolerance Out 1, Prof. H. H. Jäckel // Electronics Laboratory // ETH Zürich jaeckel@ife.ee.ethz.ch

23 Ultra fast Tb/s Photonics: Beyond the Speed of Transistor Electronics II All Optical Switches for Tb/s fiberoptic data communication Prof. H. Jäckel / Electronics Laboratory / ETH Zürich jaeckel@ife.ee.ethz.ch

24 P C PS ISB T QW -stack PS Concepts of All Optical Switches In-line all-optical gain switch: fast ISBT absortpion recovery P τ C recovery ~1/B data typ.< 1ps P S τ recovery >>1/B data Gain-pumped ISBT-AOS passive WG ISBT QW-stack ISBT active WG data out MZ-Interferometric SOA switch: slow IBT absoption recovery P s data in P c1,2 delayed control P S Interband and Intersubband transitions in QWs: Sub-ps Switching Performance: E(k) E C2 (k) E C1 (k) TPA IBT Conduction band ISBT k 500 fs Switching Window AND-Function Valence band E V (k) drawback of ISBT: only active for TM-polarization! Prof. H. Jäckel / Electronics Laboratory / ETH Zürich jaeckel@ife.ee.ethz.ch + fast, low saturation energy - complicated structure and control

Challenges of ultrathin Quantum Wells The InGaAs/AlAsSb system:

Destroyed interfaces Non square-like potential Reduced separation

In-interdiffusion: AlAs layer improves the interface quality 27.07.

25 Challenges of ultrathin Quantum Wells The InGaAs/AlAsSb system: intersubband transition energy decrease: Sb and In interdiffusion Destroyed interfaces Non square-like potential Reduced separation energy between states AlAs-Monolyer interfaces for stopping Sb- and In-interdiffusion: AlAs layer improves the interface quality Prof. H. Jäckel / Electronics Laboratory / ETH Zürich jaeckel@ife.ee.ethz.ch

Honeycomb TM-mode PhCs for ISBT-AOS 2D band diagram of honey comb

24a Honeycomb PhCs provide an interesting compromise Honeycomb PhC

4) largest TM-PBG for manufacturable PhC structures up to 12% bandgap

22-ratio: r/a=0.24 of a =530nm Connection Material Collapse r/a=0.

26 Honeycomb TM-mode PhCs for ISBT-AOS 2D band diagram of honey comb PhCs (substate type): n=3.24, r=0.24a Honeycomb PhCs provide an interesting compromise Honeycomb PhC require a large r/a-ratio Honeycomb lattice: (n=3.24, h=0.45a, r/a=02.4) largest TM-PBG for manufacturable PhC structures up to 12% bandgap (200nm 1550nm) Processing challenges for high r/a<0.22-ratio: r/a=0.24 of a =530nm Connection Material Collapse r/a=0.22 of a =530nm Prof. H. Jäckel / Electronics Laboratory / ETH Zürich jaeckel@ife.ee.ethz.ch

27 Honeycomb Photonic Crystal TM-mode waveguides Requirements: - large TM-bandgap at 1550nm - small group velocity v gr for high nonlinearity - acceptable a/r-ratio for reliable fabrication Type I: W1 PhC waveguide in Γ K' direction and its 2D band diagram 0.5 Introducing one row of holes f Γ Wave vector kx K' Type II: W2 PhC waveguide in Γ K' direction and its 2D band diagram Removing two rows of holes f Γ Wave vector kx K' Prof. H. Jäckel / Electronics Laboratory / ETH Zürich jaeckel@ife.ee.ethz.ch

28 FIRST-LAB: Example of Technology-Sequence of an InP/InGaAs-Heterojunction Bipolartransistor-IC InP-Wafer 12 Mask-Prozess, 4-5 week processing in the clean-room Emitter wet etching Metal Evaporation Dry-Etching RIE Basis / Emitter Metal Contacts Wet Processing Collector Dry-Etching Epitaxy Resistors Capacitors Elektron-Beam Lithography Circuits and IC Optical Lithography

29 Thanks for your attention! Collaborations: Project funding: NSF NCCR Quantum Photonics-, ETH-TH-, ETH-INIT-Grants, epixnet EU-Grant: Prof. H. H. Jäckel / / Electronics Laboratory / / ETH Zürich jaeckel@ife.ee.ethz.ch

Lecture: Integration of silicon photonics with electronics. Prepared by Jean-Marc FEDELI CEA-LETI

Lecture: Integration of silicon photonics with electronics Prepared by Jean-Marc FEDELI CEA-LETI Context The goal is to give optical functionalities to electronics integrated circuit (EIC) The objectives