Logic Circuits with Complementary Transistors

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1 SO d I 2 Danish Atomic Energy Commission Research Establishment Riso Riso Report No. 126 Logic Circuits with Complementary Transistors by K. B. Hansen May, 1966 Sales distributors: Jul. Gjellerup, 87, Sblvgade, Copenhagen K, Denmark Available on exchange from: Ubrary, Danish Atomic Energy Commiiaion, Ri»o, Roikilde, Denmark

2 May, 1966 Ris6 Report No. 126 Logic Circuits with Complementary Transistors by K. B. Hansen The Danish Atomic Energy Commission Research Establishment RisO Electronics Department Abstract This report presents circuits with complementary transistors intended for the realization of logical functions. The advantage of these circuits is shown to be the simple dimensioning, leading to great flexibility in the realization of logical functions and efficient utilization of the components. This is paid for by a lower transmission speed than that ultimately possible with the same active components. The basic circuits are interpreted as representing single logical functions (AND, OR and NOT) in double-polarity logic, while the singlepolarity logic circuits normally used represent combined logical functions (NOR and NAND).

3 2 Contents Page 1. Introduction Logic Circuits with pnp and npn Transistors 3 Acknowledgement 5 Appendix 6 A. 1. Dimensioning of Logic Circuits with pnp and npn Transistors 6 A. 2. Calculation of Standard Component Values 9 A. 3. The Load Conditions of the NOT Circuit H References H Figures 12

3 1. Introduction The present report is intended to give a brief description of the circuits used by the data-processing section of the Electronics Department for the realization of logical functions.

4 3 1. Introduction The present report is intended to give a brief description of the circuits used by the data-processing section of the Electronics Department for the realization of logical functions. These circuits must not be regarded as standard circuits for use in all digital systems to be designed. However, they have proved very useful for experimental work in enabling us to design data-recording equipment with the fewest possible components, simple dimensioning and a high degree of reliability. In some measure these advantages have been obtained at the expense of speed, but in most equipment in current use the reaction time of the logic circuits is unimportant as compared with that of other components such as relays, recording units and motors. 2. Logic Circuits with pnp and npn Transistors Even if we confine ourselves to the realization of logical functions by means of semiconductor components, there are many possibilities. The most frequently used circuits are based on resistance-transistor or diodetransistor logic circuits, in which the logical function is realized by means of resistances and diodes respectively, while the transistor serves as an amplifier. The circuits described 12 * 3) ' are all based on the use of mainly one type of transistor, either pnp or npn. This means that the logical truth value ("1") is represented by either a negative or a positive voltage (singlepolarity logic). In consequence, a circuit usually satisfies a combined logical function, either NOT-OR (NOR) or NOT-AND (NAND). In its work with digital technique, the data-processing section has employed another circuit type, based on the utilization of the complementary properties of pnp and npn transistors; the two kinds of transistor are used alternately, i. e., the outputs of pnp transistors activate the inputs of npn transistors. One advantage of this combination is the possibility of dimensioning with a wider safety margin (the "efficiency" is greater) as the collector current of a transistor is utilized to a higher degree for the control of the following stages. At the same tims the basis of the dimensioning (see the appendix) is simpler and provides a better possibility of individual dimensioning. Thus one is allowed more liberty in the choice of fan-in and fan-out numbers and hence a better possibility of realizing a given logical function by means of the fewest possible components. It is natural to inter-

$This means that a single circuit does not perform logical inversion (NOT); it is therefore necessary to use special circuits to realize \ : OT functions.$

5 4 pret these circuits 3s being based on double-polarity logic, i. e., "1" is represented now by a positive, now by a negative voltage according as the function is realized by a pnp or an npn circuit. This means that a single circuit does not perform logical inversion (NOT); it is therefore necessary to use special circuits to realize \ : OT functions. Figure 1 shows the circuits it has proved expedient to use, together with the block symbols representing 'hem in the double-polarity logic. As signal voltages corresponding to "1 ' are used 0 and -8 volts. Thus the polarity signs of the block symbols indicate the voltage, + for 0 volts and - for -8 volts, that corresponds to the logical truth value of the wire concerned. In block combinations the connections must accordingly have the same polarity sign at both ends. Where this is not the case, polarity changers must be inserted. These stages are AND circuits whose emitter has a fixed potential corresponding to the logical truth value of the circuit in question. With a view to the practical work, however, it is expedient to give these circuits a block symbol of their own (fig. 2). The NOT function is here realized by a diode-transistor circuit in which the transistor has the same polarity as has that activating the circuit. A variant of the NOT circuit, the inhibitor circuit, is shown in fig. 2. The work connected with the realization of a compound logical function naturally falls in three phases, namely working out of a descriptive logic block diagram, the logic block diagram used, and the circuit diagram. By way of example the design of an equalizer is shown in fig. 3. The disadvantages of the use of complementary circuits are in the first place that, for the desired possibilities to be available, one must have several circuits, namely for both the AND and/or OR and the NOT functions, and of the pnp as well as the npn type. In the second place these circuits are slower than single-polarity ones because less power is available to counteract the storage effect in the transistors. Where transistors of recent design are used, the difference is, however, only a fraction of a microsecond and usually of no importance in data-processing equipment. The use of complementary transistors in memory circuits (bistable circuits) has been investigated by Bossart (ref. 4); the paper contains calculations of the storage time and rise time of these circuits, but combinatory circuits are not dealt with in detail. As seen in fig. 4, a bistable circuit with DC set and reset is built up by means of the elementary logic circuits. In literature such a circuit is

6 5 often referred to as "latch" to distinguish it from the flip-flop, which requires a shift pulse to be brought into a state corresponding to the conditions indicated on it. The flip-flop or triggered bistable circuit is used with advantage for instance in shift registers because the memory required during the shift may be realized by means of passive components. Figure 5 shows the realization of a triggered bistable circuit with complementary transistors. The set-reset function is here performed by a symmetrical transistor; if A is 0 volts ( +.rue value, "1"), the symmetrical transistor will work as an emitter follower and, by a pulse at its base, set the bistable circuit; if A is not 0 volts (false value, "0"), the transistor will work as a collector follower and, by a pulse at its base, reset the circuit. Acknowledgement The author is indebted to Flemming Steenbuch for the translation of this report into English.

7 6 A. 1. Dimensioning of Logic Circuits with pnp and npn Transistors Figure 6 shows a section of a circuit from a logic system in which the complementary properties of pnp and npn transistors are utilized. If the block diagram is realized by means of the circuits shown in fig. 1, an AND block will result in a chain of transistors (p and q), while the OR blocks will be realized by diode matrices (m, n and m', n*). If we consider a transistor in the chain q, we may determine the collector current that the transistor must be capable of supplying to the n 1 following stages, and thus the base current required by the transistor. In the absence of this base current, the transistor must be securely cut off by means of the resistance R A and the voltage V«. When all the n chains loading a chain p have been determined in this way, the conditions for the chain p have been fixed. The following symbols are used in addition to those indicated in the figure: I, : diode reverse current Q Vp : voltage drop of the collector emitter in the case of conducting transistor V_ V n : voltage drop of the base emitter in the case of conducting transistor : voltage drop of the diode I rro : collector cut-off current, The maximum value of the collector current that the chain q must be able to supply to the row k» will be ffiaxl c" n 1 v /m' n' n' v Z *k-j T^+ I 1 a ij j=l j=l i=l 3*1 r a kt r VjjW 1 * s where a.. 1 when a diode is inserted between the wires i and j; in the absence of a diode, a.. = 0.

8 7 The first term of eq. (I) is the total base current to be supplied by the chain q, the last term is the maximum total diode reverse current to be given off. This happens when only one cf the rows in the matrix network m'n 1 is activated (represents logical "1"). From eq. (1) we have n' y n'.m'. maxl c = I a kij ^ + I U Z a - 1 ] l d. (2) 3=1 " 3=1 Vl The minimum base current available to a transistor in the chain q is J V 2 -(p+ q -l)v c -V B -V D V 3 +tq-l)v c +V B B R B R A On insertion of the current amplification p = -y we derive from l B eqs. (2) and (3) the following inequality, which must be fulfilled to ensure that a transistor is conducting, that is, that the voltage drop of the collector emitter is smaller than the knee voltage: JV 2 -(l* q -l)vv B -V D V(q-1)VV B X n ' V 2 *, X be satisfied: To ensure the cut-off of the transistor the following inequality must (4) v m m n m A TTr "u^bo+f 1 a I il a E ij - a il) J d + i=l M=l j=l i=l / X CBO ; (5) the first term is the collector cut-off currents from all transistors that can activate the transistor considered, the second term is the diode reverse currents in those rows of the matrix network which are connected to the column 1, and the last term is the cut-off current of the transistor itself. Eq. (5) may be rewritten as

9 8 m ni n ^ >( I a. i+ xj ICBO + I a u ( I ^ - l) I d. (6) A V i=l ' i=l V 7 j=l It should be noted that the quantities on both sides of the inequality sign in (4) should in fact be corrected for the position of the transistor in the chain q since a transistor at the bottom of the chain must also supply the base current of the other transistors in the chain. This is compensated for by the fact that the bottom transistor is itself supplied with a stronger base current, and we find that if the inequality R B R A ( V C + V C \ is satisfied, (4) holds. This is the case, to a sufficient approximation, with the circuits used in practice. If we compare (4) and (6) with the corresponding inequalities for single-polarity logic circuits (ref. 1), we see that the advantage of calculating the double-polarity circuits is that from (6) we may determine R. independently of the other stages (and R,,) and then, by means of (4), may determine R R from our kno^ ledge of the preceding and the following stage. From (3) and pi B = I c we obtain for R fi the expression R W B V, - (k+ 1-1) V c - V B - V D i c. p v 3 +(i-i>v c+ v B R A This expression has the form R B*TTTT7" l C + v 3 where V 2 and V«are corrected for the transistor and diode voltage drops.

10 9 A. 2. Calculation of Slandard Component Values By a circuit with standard component values is understood a circuit with fixed transistors, diodes and resistance values. If a logic system is realized with such circuits, the load must be kept within the permissible values of these. For circuits of >.his kind we must have n' m' m n I a kij I &ij = I a n I j=l i=l i=l j=l and R B, = R B. By means of (6), expression (4) may then be rewritten n', T ^ p [ *i ~ J" "** V*I ' (7) Putting we have 2. a,,. K J 3-1 a N (fan-out number), V 2 (l-f)-(p+q-l)v c -V B -V D R B Vg(l + J.)+(q-DV c +V B *Z Example: The nominal voltages used are V 2» -8.5 volts V^ «-4.5 volts.

11 10 For the transistors, OC47 and OC141, and the diode, OA85, we have V c ~ 0.20 volt (OC 47 and OC 141; I c * 10 ma; T «25 C) V fi ~ volt ( " " " " " ) P ~ 30 (min OC 47:50; OC ; I c = 15 ma) V D ~ 0.5 volt (OA85; I D 2 ma; T = 25 C). If we assume tolerances of +10% for V and -10% for V, +5% for R R and -5% for R«(worst-case design) and nominal values of R R and R A of R B * 3.9k fi R A * 4.7kQ, we obtain the following inequality that must be fulfilled: N p q < 10. p q» 1; N < 8 p q» 2; N < 5 p»q«3; N < 3. The condition (6) sets a limit to the number of diodes. With the values.o. I CB, " 100 ua (max OC47 and OC141; 35 ua; V c 5 volts; T = 60"C) I d 50 ua (max OA 85:40 ua; -V D = 10 volts; T» 60 C) and the earlier used values of Vq and R., with the most unfavourable tolerances, we obtain the condition m 1 a il ( I a ij i-1 j*l + *)* 14 '

12 11 We put m n 1 a n I a ij= IN, i«l j=l which is the sum of the fan-out numbers of all transistors activating the transistor considered. Further we put m L a,, * M (fan-in number) i-1 and obtain M + IN 14. A. 3. The Load Conditions of the NOT Circuit The NOT circuit employed, and the variants NOR and INHIBITOR, are dimensioned on the basis of the formulae given by Masher '. Figure 7 shows the permissible load conditions, the symbols being the same as above. The values of voltages, currents, tolerances, etc., are likewise the same as those used in the foregoing. References 1) D. P. Masher, The Design of Diode-Transistor NOR Circuits. I. R.E. Transactions on Electronic Computers EC-9 (1960) ) W. J. Wray, DC Design of Resistance Coupled Transistor Logic Circuits. I. R. E. Transactions on Circuit Theory CT-6 (1959) ) W.B. Cagle and W.H. Chen, A New Method of Designing Low Level, High Speed Semiconductor Logic Circui s. Wescon Convention Record, Pt. 2 (1957) ) Lee M. Bossart, Complementary Transistor Memory Circuit and Logic Applications. SCTM (72) (1962).

13 12 =D- =&- H)- AND OR NOT 3.9 h OCH1 3> Logic circuit and corresponding symbols for double-polarity logic H 3.9li h a.5 "II OC47 3> The signs indicate the signal polarity of the logical truth value I 5 0CH1 V T Jt J 0C*7 ^O 0*85 $ * # * Fig. 1. Logic block symbols.

14 13 OCKl + I \ - Polarity changsr I J logical identity , X 2.7 U 3> OCKl Inhibitor ». 0CH1 L/ OR-NOT(NOR) -13 -».5 Fig, 2. Variants of circuits in :*ig. 1,

15 14 B - D js- A-B+A-B Ocscriptiv«Mock diagram V 3> H^ FM> Bloch diagram ui«d A.5 0 c 1 ^ ^ 0 < -13 Circuil SO é 13 -M Fig. 3. Equalizer.

16 15 t/b. if *5 o e ZSS I -i h x Bo \m i i Circuit 13 -as Fig. 4. Bistable circuit (RS flip-flop, "latch").

17 O f 4-^B A+± 1-t- Symbol R i t Fig. 5. Triggered bistable circuit (RST flip-ilop).

18 17 Block diagram I i ^ ^ fr ^ ^ - *é',.,-* ) 1 2 ±_± & $ -S - * k' 1 2 I" ^ " Circuit -v, Fig. 6. Calculation of component values.

19 13 P s 1 O- M*IN<K <*1 rtk 0CH1 N <a Fig. 7. Load conditions of the NOR inhibitor.

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