Subsampling CMOS Frontends for Multistandard Reconfigurable RF Radios

Transcription

1 Subsampling CMOS Frontends for Multistandard Reconfigurable RF Radios Thesis submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electronics and Communication Engineering by AJINKYA UMESH KALE International Institute of Information Technology (Deemed to be University) Hyderabad , INDIA December 2018

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3 Copyright c Ajinkya Umesh Kale, 2018 All Rights Reserved

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5 International Institute of Information Technology Hyderabad India CERTIFICATE It is certified that the work contained in this thesis, titled Subsampling CMOS Frontends for Multistandard Reconfigurable RF Radios by Ajinkya Umesh Kale, has been carried out under my supervision and is not submitted elsewhere for a degree. Date Advisor: Dr. Vijaya Sankara Rao Pasupureddi

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7 To my family and friends

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9 Acknowledgments Everyone, who was directly or indirectly involved in my journey, helped me to complete this work. I appreciate all contributions to this thesis. First of all, I would like to thank my supervisor Dr. Vijaya Sankara Rao Pasupureddi for his continuous guidance, support and motivation without which this work would not have been possible. I would also like to thank Dr. Suresh Purini for supporting with the administrative formalities as my Administrative Supervisor. I would also like to express my gratitude to the Advanced Systems Laboratory (ASL), Defence Research and Development Organization (DRDO), Hyderabad for the financial and technical support provided for the work on Electronic Attack System. Specially, I would like to acknowledge Dr. J. Chattopadhyay and Mr. M. H. Rahaman for the technical discussions, valuable suggestions and feedback provided by them during the project. I would also like to thank Mr. Sachin Jain, Ms. Pummy Ratna and Mr. Bhamidi Subrahmanya Teza from ASL, Hyderabad for their valuable suggestions and feedback. My special thanks to Mr. Ramakrishna Thirumuru for our long technical discussions in course of the Electronic Attack System design. The dual-band WLAN receiver research work was done in course of the Josef Ressel Center for Integrated CMOS RF Systems and Circuits Design Interact at the Carinthia University of Applied Sciences. I would like to thank Prof. Dr. Johannes Sturm for providing me with the opportunity to work on the project. Also, I would like to thank Prof. Erwin Ofner for our discussions and Dr. Michael Koeberle for his continuous support, discussions and feedback. I would also like to thank Mr. Suchendranath Popuri for his support and feedback during the course of the project. The LNA design presented in the WLAN part of this work was designed and implemented by him. The financial support by the Austrian Federal Ministry of Science, Research and Economy and the National Foundation for Research, Technology and Development is gratefully acknowledged. I also wish to thank Intel Austria GmbH for their v

10 financial contribution and technical support and special thanks to the INTEL CHD team in Villach for their co-operation. I would like to acknowledge Mr. Peter Pessl, Mr. Alexandar Kahl, Mr. Steffen Trautmann and Mr. Denis Matveev from Intel for their valuable inputs and technical discussions and support for lab measurements. I would also like to acknowledge Mr. Vedran Sesic, Mr. Hermann Sterner, Mr. Ingmar Bihlo and Mr. Filipitsch Bernd for their support during design, implementation and testing phase of this work. I am grateful to Dr. Syed Azeemuddin, Dr. Srivatsava Jandhyala, Dr. Shubhajit Roy Chowdhury and Dr. Prasad Krishnan, Dr. Anubha Gupta under whom I took graduate courses. I am also thankful to the staff at CVEST, specially Mr. Satish Kumar Gatla for his support. I would like to acknowledge the institute for providing me with this opportunity to carry out research and shaping up my career. I also would like to thank the Conference and Journal reviewers for their suggestions and inputs, which allowed me to present my work to the larger community. My journey would not have been memorable without the colleagues and friends. I would like to thank Mr. Neeraj Paradkar, Ms. Lipika Agarwal, Mr. Prateek Pendyala, Mr. Bhuvanan Kaliannan, Mr. Gopi Krishnan, Mr. Mohd Anwar, Dr. Vasu Pulijala, Ms. Divya Dhuvuri, Mr. Harit Pandya, Mr. Falak Chhaya, Mr. Mihir Shekhar, Mr. Koustav Ghoshal and the list goes on and on. They were always there for me in all ups and down of this journey. Thank you all for being with me through everything and I will always cherish all the memories with you guys. The same goes for all of my colleagues and friends at Villach. I would like to thank Ms. Graciele Batistelle for her encouragement and support. Also, thanks to Dr. Sahar Sarafi, Mr. Arash Ebrahimi for our many discussions. Also thanks to Dr. Mudasir Bashir, Dr. Dongning Zhao, Mr. Ivan Sejc, Mr. Albert Suriol, Mr. Ornel Koci, Mr. Darshan Bhaskar Shetty, Mr. Pratap Renukaswamy, Mr. Vedran Sesic, Mr. Vaibhav Jagdish, Mr. Nikhil Ladhha, Ms. Bhagyashree Dhumale, Mr. Sarath Chandra Mulluvila and Dr. Saurabh Roy for their continuous support. This work would not have been possible without the constant encouragement of my friends. Finally, I would like to thank my parents, my sister Ms. Ankita and my little brother Mr. Nishant for their unconditional love, motivation and patience with me. I also acknowledge the support of my family that guided me to reach here. vi

11 Abstract With the evolution of wireless systems, more communication standards are being proposed while maintaining backward compatibility, therefore, there is an ever growing need for wideband multistandard receivers similar to software defined radio (SDR) receivers. For many years now, SDR or digitally reconfigurable radio research has been quite challenging with only a few reported practical prototypes with limited success. The basic demand of the SDR has been the need for a giant analog-to-digital converter (ADC) and a powerful enough digital signal processing (DSP) so that it serves as a universal radio platform receiving almost all radio standards and services. These demands are difficult to meet even in modern CMOS technologies leading to the necessity of highly flexible architectures compared to traditional receivers. To achieve this objective, digital intensive receiver architectures with passive structures are proposed. Radio frequency (RF) sampling receivers using time-interleaved (TI), RF sampling and discrete-time mixing also provide additional flexibility by employing discrete-time signal processing in analog domain. Owing to the oversampling ratio of up to 8 times in these receivers, high-performance complex frequency synthesizers are needed with stringent phase noise requirement. Moreover, the clocking schemes employed in TI RF sampling architectures result in additional timing jitter and mismatch offsets. These challenges are alleviated in a class of sampling receivers, called subsampling receivers, where the employed bandpass sampling principle results in less than the Nyquist sampling frequency. This leads to the less-complex and less power hungry frequency synthesizers. In this thesis, an intermediate solution to SDR receiver implementation called Mini-SDR architecture is proposed by exploiting the bandpass sampling concept. Based on the proposed Mini-SDR architecture, three CMOS radio frontends are proposed for standalone electronic attack (EA) transceiver system, dynamically reconfigurable multistandard subsampling (DRMS) radio receiver and a dual-band subsampling receiver for IEEE WLAN ac standard. vii

12 The first architecture is a single chip integrated transceiver for a standalone EA system based on digital radio frequency memory (DRFM) repeater without the need for a separate instantaneous frequency measurement (IFM) receiver. The proposed transceiver architecture employs sub-nyquist discrete-time frontend to estimate the carrier frequency and bandwidth of the incoming pulse radar signals. The system is verified for linear frequency modulated, constant carrier frequency and phase coded pulse radar signals. These signals are classified on the basis of Wigner-Ville distribution. The performance of the proposed system is validated from 1 GHz to 20 GHz with instantaneous bandwidth of 300 MHz, dynamic range from 60 dbm to 20 dbm and system gain from 30 db to 60 db. The minimum delay achieved between reception and retransmission is 13 pulse repetition intervals (PRIs). To the best of author s knowledge, this work reports the first sub-nyquist bandpass sampling based single chip architectural solution for a standalone EA system where RF frontend and digital controller are integrated into the system. The second architecture is the DRMS radio receiver. The proposed receiver has a unique capability to detect the carrier frequency of the incoming signal, estimate it s bandwidth and standard. The RF frontend is modelled in Verilog-AMS behavioural model and the digital signal processing is implemented in Simulink-Matlab. Also, the system level optimizations of the overall receiver performance are presented with the effect of receiver impairments. The complete receiver architecture has been verified to detect and process three different bands belonging to three different standards (GSM, UMTS and WLAN) with the carrier frequency ranging from 0.9 GHz to 2.5 GHz with a maximum signal bandwidth of 22 MHz and the input dynamic range from 109 dbm to 20 dbm. The last implementation is a first dual-band subsampling receiver with subsampling frequency optimization to meet ultimate receiver error vector magnitude (EVM) of 40 db over wide input power range of 19 db. Systematic system level optimization of the receiver chain with major impairments such as sampling frequency, synthesizer phase noise, IQ mismatch and unit capacitor in the SC filter is also proposed. Sampling frequency optimization proposed in this work has multi-fold advantages: a) the noise folding effect is reduced leading to smaller noise figures. b) less-complex and less-power hungry clocking scheme. c) quadrature phase readily available between consecutive samples is utilized to separate samples into in-phase (I) and quadrature-phase (Q) paths. d) the ultimate EVM performance of the receiver is significantly viii

13 better than the subsampling receivers, where the sampling frequency is not optimized. The dual-band subsampling receiver has 26 db to 40 db continuously tunable gain and 4.7 GHz to 5.7 GHz continuously tunable frequency band. The subsampling down-conversion mixer is employed to down-convert both 2.4 GHz and 5 GHz WLAN bands to a low intermediate frequency from 445 MHz to 538 MHz with clock frequency in the range from 1.78 GHz to 2.15 GHz, thanks to subsampling. Additionally, a switched capacitor decimation filter is utilized to provide dual functionality of down-conversion to baseband and band selection. The proposed IEEE ac WLAN dual-band subsampling receiver test-chip is implemented in 1.2 V 65-nm CMOS technology to prove the concepts proposed, including major system level, circuit level and layout level optimizations. The test-chip occupies a total active area of 0.72 mm 2 with a total power dissipation of 61 mw. To the best of author s knowledge, this is the first subsampling based receiver to report high-frequency band 4.5 GHz to 5.7 GHz with channel bandwidths up to 40 MHz. Also, the measured ultimate EVM floor of 40 db over a wide input power range of 19 db is demonstrated which is far superior to the published sub-sampling receivers. In this thesis, CMOS frontends were modelled, designed, simulated fabricated and measured to prove the proposed concepts for multistandard subsampling radios. ix

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15 Contents Chapter Page 1 Introduction Software Defined Radio Receivers Introduction to Subsampling Radio Receiver Classification Mixing Based Receivers Superheterodyne Receiver Architecture Homodyne Receiver Architecture Sampling Receivers RF Sampling Receivers TI Sampling Receivers Subsampling Receivers Literature Survey Research Gaps Proposed Mini-SDR Architecture Mini-SDR Based Electronic Attack (EA) System for Electronic Warfare (EW) Applications Mini-SDR Based Dynamically Reconfigurable Multistandard Subsampling (DRMS) Receiver Mini-SDR Based Dual-band Subsampling WLAN Receiver Thesis Contributions Thesis Organization Mini-SDR Based Electronic Attack System for Electronic Warfare Applications Introduction Proposed Electronic Attack System Architecture Detection Phase Storing and Processing Phase Transmission Phase Performance Results Chirp Pulse Radar Signal Single Carrier Frequency Pulse Radar Signal Phase Coded Pulse Radar Signal Summary Wideband EA System x

16 2.4.1 Selection of Bandpass Filters Co-simulation results for all five EA channels working together Conclusions Mini-SDR Based Dynamically Reconfigurable Multistandard Subsampling Receiver Introduction Proposed Receiver Architecture Dynamic Detection Phase Signal Acquisition Phase System Level Optimization Sampling Frequency Optimization System-Level EVM Performance of Multistandard Receiver Sampling Frequency Clock Jitter Block-level Performance and Receiver EVM Performance Results and Discussion Improved Performance and Verification Conclusions Mini-SDR Based Dual-band Subsampling WLAN Receiver Introduction System Architecture, Analysis and Design Noise Folding in subsampling Down-conversion Decimation Down-conversion Filtering System-Level EVM Analysis Sampling Frequency Unit Capacitor for Decimation Filter Phase Noise or Jitter IQ Gain and Phase Mismatch Block-level EVM Performance and Receiver Ultimate EVM System Level Specifications From IEEE ac Standard Maximum Receiver Noise Figure Minimum Receiver Linearity (IIP 3 ) Sampling Frequency Phase Noise and Jitter Requirements Receiver specifications from ac standard Summary Circuit Building Blocks Dual-Band Low Noise Amplifier Subsampling Mixer Decimation Filter Clocking Scheme Measurement Buffer Conclusions xi

17 5 CMOS Implementation of Dual-band subsampling WLAN Receiver Layout Implementation LNA Layout Subsampling Mixer Layout Decimation Filter Layout Complete Dual-band Receiver Layout Post-layout Performance Results CMOS Implementation CMOS Measurement Setup LNA Measured Performance Decimation Filter Performance Measurements Complete Receiver Chain Performance Measurements Noise Figure Linearity Receiver EVM Performance Comparison Conclusions Conclusions and Future work Conclusions Future work Related Publications Bibliography List of Abbreviations xii

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19 List of Figures Figure Page 1.1 Ideal SDR Practical SDR Therotically minimum normalized sampling frequency versus normalized high edge frequency (f H ) Valid sampling frequency region (shown in shaded) for subsampling Simplified receiver architectures (a) CT-mixing receiver (b) radio frequency (RF) sampling receiver (c) Ideal SDR receiver Superhetrodyne receiver Homodyne receiver RF oversampling receiver architecture Time interleaved sampling receiver architecture Sampled Spectrum based on bandpass sampling Spectrum for RF sampling down-conversion filter Proposed Mini-SDR architecture Traditional DRFM based EA system Block diagram of general DRFM system Simplified block diagram of the proposed electronic attack system Proposed multistandard receiver architecture for GSM, UMTS and WLAN standards Block diagram of the proposed dual-band subsampling receiver for 2.4 GHz and 5 GHz WLAN bands Block diagram of traditional electronic warfare application Block diagram of traditional EA system based on DRFM Simplified block diagram of the proposed electronic attack system Target system gain profile used for implementation Detection state machine Storage state machine Transmission state machine Co-simulation setup Estimated PSD and TFA for stored samples for up-chirp pulse radar signal listed in Table Estimated PSD and TFA for stored samples for constant carrier frequency pulse radar signal listed in Table xiii

20 2.11 Estimated PSD and TFA for stored samples of costas phase coded pulse radar signal listed in Table Simplified wideband EA system block diagram Wideband EA system gain profile used for implementation Subband filters responses for first EA channel Estimated power spectral density for all five EA channels EA system input and output signal for all five EA channels Proposed multistandard receiver architecture for GSM, UMTS and WLAN standards State machine explaining the detection and acquisition algorithm for the proposed multistandard receiver Detection and acquisition co-simulation results for GSM test signal of the multistandard SDR receiver Receiver EVM degradation vs sampling frequency Receiver EVM degradation vs frequency synthesizer RMS jitter Block level EVM for the multistandard receiver for WLAN detection Ultimate EVM simulation for multistandard receiver WLAN detection Detection and acquisition co-simulation results for UMTS test signal of the multistandard SDR receiver Simulation set-up for performance evaluation of the proposed multistandard receiver architecture Detection and acquisition co-simulation results for WLAN test signal of the multistandard SDR receiver Detected PSD corresponding to all filters for GSM test signal Down-converted GSM signal PSD with IF of MHz Detected PSD corresponding to all filters for UMTS test signal Detected PSD corresponding to all filters for WLAN test signal Down-converted UMTS and WLAN signal PSD Received Constellation for the Down-converted 4-QAM, 4 sub-carriers, 20 MHz moduated WLAN signal with 40 dbm RF signal power in comparison to ideal 4-QAM constellation Block diagram of the proposed dual-band subsampling receiver for 2.4 GHz and 5 GHz WLAN bands Noise power levels at the output of the subsampling mixer SNR degradation due to noise folding effect in the subsampling mixer GHz decimation filter transfer function GHz decimation filter transfer function SC core for the decimation filter Receiver EVM degradation vs sampling frequency Receiver EVM degradation vs decimation filter unit capacitor Receiver EVM degradation vs frequency synthesizer RMS jitter System level variation of receiver EVM vs IQ mismatch System level variation of receiver EVM vs IQ mismatch Block level EVM for the proposed subsampling receiver xiv

21 4.13 Ultimate EVM system level simulation BER vs E b N Minimum signal to noise ratio for various modulation schemes for WLAN standard Maximum noise figure with respect to modulation schemes Minimum IIP 3 requirement from ACR and NACR of the WLAN standard LNA circuit implementation for the 2.4GHz and 5GHz receiver Active CMOS resistor used for gain and frequency tuning in dual-band LNA Subsampling mixer down-conversion stage Switched capacitor decimation bandpass filter circuit and the layout implementation for the 5 GHz decimation filter Baseband amplifier circuit Non-overlapping clock generator with clocking divider Measurement setup for LNA and mixer characterization RF-IF measurement buffer Baseband measurement buffer Layout for low noise amplifier Layout for subsampling mixer and IFA Layout for decimation filter Top level layout of the complete test-chip with both the receiver chains Post-layout simulated clock phases for 5 GHz receiver chain Post-layout simulated BB output for 5 GHz receiver chain Characterization board photograph Test setup for dual-band receiver characterization S-parameters for 2.4 GHz LNA S-parameters for 5 GHz LNA Measured LNA gain tuning Measured LNA noise figure versus gain Measured IIP 3 versus gain for 2.4 GHz LNA Measured IIP 3 versus gain for 5 GHz LNA Measured filter transfer function for 2.4 GHz decimation filter Measured filter transfer function for 5 GHz decimation filter Power consumption contribution of the subblocks Measured BB with single tone input for 2.4 and 5 GHz receiver chains Receiver noise figure versus sampling frequency Measured third order inter-modulation point (IIP 3 ) variation with the gain of the dual-band subsampling receiver Measured EVM performance for complete 2.4 GHz receiver Measured EVM performance for complete 5 GHz receiver Measured ultimate EVM for both receiver chains Effect of jitter and sampling frequency on the receiver EVM for 2.4 and 5 GHz receiver chains xv

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23 List of Tables Table Page 1.1 Types of receiver architectures performance comparison for receiver architectures Signal Parameters for test input signals Proposed EA system specifications DRFM channels specifications Subband filter parameters for the first EA channel Signal Parameters for test input signals Summery of performance results ECCM signal specifications Comparison with previous implementations Proposed wideband EA system specifications Sub-band filter parameters for the first wideband EA channel Sub-band filter parameters for wideband EA channel filters Input signal parameters for wideband EA test case Proposed multistandard receiver specifications Test signal specifications for validation of multistandard receiver Specification for the subband filters utilized for detection Individual block-level specifications for the multistandard receiver frontend Performance summary for the proposed multistandard SDR receiver Performance Comparison with the previous sampling receivers Improved Performance Summary for The Proposed Multi-standard SDR Receiver Block-level specifications for the receiver model Sensitivity specification Date rate specification Minimum signal to noise ratio values Adjacent and non-adjacent interferer levels System level specifications for the proposed architecture Switched capacitor filter core implementation Post-layout performance summary List of measurement instruments Static power consumption contribution of individual blocks xvi

24 5.4 Signal parameters for measurements Comparison with the state-of-the-art implementations xvii

25 Chapter 1 Introduction Based on the ever growing need for connectivity, flexibility and speed of communication systems, the recent research has been focused on the multistandard, flexible, low-power implementations of these systems. Also, the demand of newer standards with higher communication bandwidths and performance lead to requirement of new receiver architectures to implement such systems. These architectures are focused to achieve more flexibility without need of explicit multiple parallel receiver chains and off-chip passive components at the same time, resulting in low-cost, low-power implementations suitable for battery operated applications. One such class of receivers called software defined radio (SDR) is a radio with complete flexibility to receiver any standard and band of communication as needed. In this chapter, firstly, the introduction to SDR concept is presented followed by an introduction to subsampling principle. Then the classification of receiver architectures is presented. Afterwards, a literature survey is presented for the existing multistandard CMOS frontends for SDR are presented. Next, the research gaps are presented based on the existing solutions and the proposed Mini-SDR architecture is presented along with the three target applications. Finally, thesis contributions are highlighted and the thesis organization is presented. 1.1 Software Defined Radio Receivers With radio functions mainly implemented in software, SDR refers to a universal radio platform being able to tune to any of the possible communication band and process the signal [1 3]. In an ideal SDR receiver shown in Figure 1.1, the flexibility and the performance are achieved by digitizing the RF signal received by the antenna after anti-aliasing low pass filter. All further 1

26 processing is done in DSP and the programmability of this digital hardware yields the desired flexibility. As software is flexible or at least replaceable, a receiver architecture where all signal processing is done in software, will yield much flexibility. The entire complexity then lies on the design of high-performance ADC which can provide good enough resolution at the RF frequency. This results in very high power dissipation, stringent dynamic range requirements for ADC DSP Anti-aliazing Filter Figure 1.1: Ideal SDR the analog to digital (ADC) implementations. These specifications are still not supported for ADC in the existing technologies. Hence, a more practical block diagram for SDR in presented in Figure 1.2 where in the minimum signal processing required in performed in RF frontend and most of the signal processing such as filtering and gain is implemented in digital domain. ADC DSP Anti-aliazing Filter RF Frontend Figure 1.2: Practical SDR The major issue in the integrated solution implementation of ideal SDR is the dynamic range required at the input of ADC and the power consumption of ADC which can support the wideband receiver at the same time providing tolerance to strong blocker signals. Here, the flexibility and reconfigurability depends on the implementation of the RF frontend. Hence, the design optimization and implementation effort is now divided between the RF frontend and the ADC. This is identified as the intermediate goal towards the ideal SDR implementation. So, this thesis focuses on the implementation of CMOS frontends for multistandard RF radios 2

27 which can process upto three standards with more flexibility than the conventional receiver implementations. 1.2 Introduction to Subsampling The subsampling principle relies on the bandpass nature of the incoming RF signal and utilizes intentional aliasing for down-conversion. Based on the subsampling principle, the sampling frequency for a bandpass signal is given by Equation (1.1) [4]. ( Here, f H = f c + BW CH 2 2 f H n f S 2 f L (n 1) (1.1) ) is the higher edge frequency of band limited RF signal with a carrier frequency (f c ) and a signal bandwidth (BW CH ) and n is an integer value. From Equation (1.1), the theoretically minimum sampling frequency that can be used for bandpass sampling is shown in Figure 1.3 [4] with respect to f H. Both the sampling frequency and f H is normalized with respect to signal bandwidth. Also, the range of valid sampling frequencies is shown in Figure 1.4. Each region corresponds to different value of n. In Figure 1.4, the sampling frequency selected 5 4 fs,min BWCH f H BB CH Figure 1.3: Therotically minimum normalized sampling frequency versus normalized high edge frequency (f H ) by Equation (1.2) [5] is shown in blue. This is a special case of second order uniform sampling called quadrature sampling. f s = ( ) 4 fc (2k 1) (1.2) 3

28 f s as per Equation (1.2) 10 fs BWCH f H BW CH Figure 1.4: Valid sampling frequency region (shown in shaded) for subsampling Where k = 1, 2, 3...k max, k max = ( ( fh BW CH ), f H = f c + BW CH 2 ) is the higher edge frequency of input RF signal with signal bandwidth BW CH. The intermediate frequency (IF) for the sampled signal is given by Equation (1.3) [5], where l is an integer. f IF = min(f c l f s ) = f s 4 (1.3) For the quadrature bandpass sampling frequency, the corresponding phase difference between two consecutive samples is given by Equation (1.4) [5]. Thus, the consecutive samples can be used to generate in-phase and quadrature streams of samples from one sampler. This is excellent in the sense that the in-phase and quadrature components can be generated from single sampler at the RF sampling stage itself. φ = 2π f c = π (2k 1) k = 1, 2, 3,... (1.4) f s 2 The main motivation of sampling mixer is to carry out discrete-time signal processing (DTSP) near to antenna so as to provide flexibility in overall operation of the system. In ( f Equation (1.2) the value of k is optimized for the high oversampling ratio s 2 BW CH ), outof-band rejection of the aliasing signal and the noise folding effect. This results in sampling frequency more than theoretical minimum of (2 BW CH ) but lesser than (2 f H ) (Nyquist rate), hence also called sub-nyquist sampling. 4

29 1.3 Radio Receiver Classification Conventional receiver architectures relies on the off-chip bulky filters for selectivity. But owing to higher integration in lower CMOS technology and reduction in size, only on-chip components are available for implementation of the receiver architecture. Moreover, based on the commercial market requirements and newer communication standards the requirement of wideband, multistandard receiver is exigent. Hence, the idea of SDR is sought after as a solution for today s communication scenario. Also, based on the ideal SDR implementations, the need to move ADC towards the antenna is imperative. But in current technology due to power dissipation and dynamic range limitations, the ADC cannot be directly placed at the antenna. Thus, a compromise is needed in terms of placement of ADC and the RF/analog preprocessing required by the receiver. This leads to the classification of receivers based on downconversion techniques in the receiver chain shown in (Table 1.1 and Figure 1.5) [6]. The two Table 1.1: Types of receiver architectures Analog CT Analog DT Digital Mixing CT Mixing a DT Mixing b Digital Mixing c Sampling CT - to - DT Sampling b DT Re-sampling b Digital Re-sampling c a CT-mixing receiver b RF-sampling receiver c Ideal SDR receiver principles of down-conversion which are mixing and sampling, constitute two rows and the input signal domain as continuous-time (CT), discrete-time (DT), continuous amplitude (analog) and discrete amplitude represent the columns of the Table 1.1. In the Figure 1.5 a, the CT-mixing Mixer LPF Sampler Quantizer (a) S Q (b) S Q (c) S Q Figure 1.5: Simplified receiver architectures (a) CT-mixing receiver (b) RF sampling receiver (c) Ideal SDR receiver 5

30 based receiver architecture suitable for zero-if and low-if receivers with down-conversion in the continuous domain is shown. Figure 1.5 c shows the ideal SDR receiver as presented in Section 1.1 with the down-conversion in the digital domain after sampling and quantization. Here, digital mixing and digital re-sampling techniques such as decimation and interpolation for down-conversion can be utilized for the frequency down-conversion. Figure 1.5 b shows the sampling based receiver architecture wherein the motivation is to push the sampler towards the antenna. Next, each of the receiver types are presented in detail Mixing Based Receivers The conventional analog CT radio receiver architectures, as shown in Figure 1.5 a, are categorized as super-heterodyne and homodyne receiver based on the placement of intermediate frequency (IF). The superheterodyne receiver uses the local oscillator (LO) frequency not equal to RF resulting in non-zero IF. In the case of Homodyne receiver, the RF and LO frequencies are same so the IF is located at dc. These architecture are presented below Superheterodyne Receiver Architecture The superheterodyne receiver architecture is one of the first architectures used for radio receivers. The basic architecture is presented in Figure 1.6. This architecture benefits from higher selectivity and image rejection due to off-chip filters used in the architecture but suffer owing to bulky and costly nature of the bandpass filters. It uses the first bandpass filter (BPF) to carry out band selection, second BPF for image rejection and the third BPF for channel selection. The selection of IF represent the trade-off between the image rejection and channel selection of the receiver architecture. Higher IF is desired for better image rejection and lower IF is coveted for improving channel selection. BPF LNA BPF Mixer BPF VGA ADC Band Selection Chip Image Rejection Channel Selection LO Figure 1.6: Superhetrodyne receiver 6

31 To break this trade-off, the receiver architecture utilize more than one down-conversion stages. Also, if the RF is very high as compared to signal bandwidth, multiple mixer stages are utilized to down-convert the signal to baseband before processing. The non-zero IF signal at the output of the first down-conversion mixer can be down-converted further to base band. These architecture are called dual-if corresponding to two intermediate frequencies and tripe IF for three intermediate frequencies. This architecture is still very popular among receiver architecture but lack the integration due to use of off-chip components Homodyne Receiver Architecture The homodyne receiver also known as zero-if or Direct conversion architecture is shown in Figure 1.7. The architecture uses LO frequency equal to RF resulting in signal downconversion directly to baseband. Thus, the design of baseband signal processing circuit is simplified. Mixer LPF VGA I ADC BPF LNA 0º 90º LO Band Selection Q ADC Chip Mixer LPF VGA Figure 1.7: Homodyne receiver As the second and third BPF are removed from superheterodyne receiver (Figure 1.6), the homodyne receiver benefits from higher integration. Also, as the IF is zero, the image of the RF signal is the signal itself. Hence, the image rejection mixer with two phases of LO frequencies shifted by 90 are utilized to carry out in-phase (I) and quadrature (Q) down-conversion. Hence, the architecture has easier image rejection, high integration and low cost owing to lack of offchip components. However, this architecture suffers from the dc offset issue due to LO leakage and the IQ mismatch impairment. 7

32 1.3.2 Sampling Receivers To meet the challenges present in the design of SDR receiver, a new class of receiver architectures and circuits are required which provide more flexibility and similar performance as compared to conventional receiver architecture and are targeted for low power battery operated applications. Sampling receiver as shown in Figure 1.5(b) sample the incoming RF signal before employing a DTSP to down-convert, filter and amplify the signal. This results in additional flexibility compared to traditional receiver as the DTSP can be scaled with respect to sampling frequency change. This is also in line with the practical SDR implementation as presented in Section 1.1. Based on the value of the sampling frequency utilized in the architecture in Figure 1.5(b), the architecture can be implemented using RF oversampling receiver, TI sampling receiver or subsampling receiver. The sampling frequency optimization plays important role on the overall receiver performance. These classifications and their implementations are presented in following sections RF Sampling Receivers In this type of receiver architectures, the sampling frequency more than or equal to Nyquist rate of the incoming RF signal is employed in the receiver. The architecture implemented in [6] uses 8 times oversampling with respect to RF frequency to ensure that the alias bands after sampling are far away from the desired signal. After the oversampling, a charge domain multiplier based mixer, a harmonic rejection LO in discrete-domain is utilized with the capacitor ratio in the SC core as shown in Figure 1.8 [6]. The discrete time mixing based down-conversion SC Core LP IIR IF Buffer B I f c RF in RFA A C ac S f s =8f c LP IIR B Q 4f c CLK in CLK Buffer CB /8 duty cycle & CLK driver Chip Figure 1.8: RF oversampling receiver architecture 8

33 ensures that the baseband I and Q phase difference is generate by the sine and co-sine LO. As the capacitors in advance technology nodes can be implemented very good accuracy, this results in an accurate phase difference in I and Q samples over wideband. The oversampling in sampler is utilized for wide band harmonic rejection in discrete mixer stage and for alleviating noise and interference folding effect. This architecture also provides wideband accurate quadrature down-conversion due to use of charge domain discrete time mixing. But the use of 8 times oversampling results in very high sampling frequency requirement for the sampling receiver. This in turn results in higher power dissipation. Thus, the next step in development is to reduce the sampling frequency requirement in the receiver architecture TI Sampling Receivers The oversampling receivers are also implemented using TI paths to sample the RF signal and then apply the DTSP. In [7], the receiver uses 8 TI paths, each operating at sampling frequency equal to center frequency of the RF signal, thus providing, overall effective 8 times oversampling (Figure 1.9a) [7]. The samplers are implemented in charge domain sampling as shown in Figure 1.9b [7]. Here, the quadrature LO signals are implemented using weighted P Unit v P 3 MI [8m+1] 1 Sampler 1 v s [8m+1] x{p I,1 p Q,1 } v MQ [8m+1] P 3 i RF v A Z in P 2 P 8 v s [8m+2] v s [8m+8] Unit Sampler 2 x{p I,2 p Q,2 } Unit Sampler 8 x{p I,8 p Q,8 } v MI [8m+2] v MQ [8m+2] v MI [8m+8] v MQ [8m+8] P 4 P 4 P 2 P 2 I Branch Q Branch i RF + i RF - P 1 P 5 P 1 P 5 P 1 P 2 Unit Sampler 1 P 3 P P 7 3 C B R B -A I Branch v BI Multiplier v s [n] p I [n] p Q [n] v MI [n] v MQ [n] P 1 P 2 P 3 P 4 P 5 P 6 P 7 P 8 P 5 P 6 P 7 P 3 P 7 C B R B -A Q Branch v BQ (a) Time interleaved sampling receiver (b) Time interleaved sampling unit Figure 1.9: Time interleaved sampling receiver architecture capacitors in the sampling unit. This results in very precise quadrature down-conversion at 9

34 the receiver output. The implementation uses harmonic rejection LO to reduce the effect of harmonic seen in the down-converted signal. This implementation uses sampling paths operating at sampling frequency equal to carrier frequency. Thus, reducing the operating frequency for the sampler compared to oversampling receiver. But, the mismatch between time interleaved paths and the timing and jitter requirement for implementing the non-overlapping clocking circuits at high RF frequencies proves challenging for the implementation Subsampling Receivers Selection of sampling frequency is a crucial step in sampling receiver design. Receiver architecture presented till now suffer from higher sampling frequency requirements or the mismatch between time interleaved paths. These challenges can be overcome utilizing lower than Nyquist sampling frequencies in these receiver architecture. These subsampling / Bandpass sampling / Sub-Nyquist sampling receivers are presented in this section [5, 8, 9]. Based on Section 1.2, this section presents down-conversion methodology of the RF signal through intentional aliasing. From Equation (1.1) and Figure 1.3, for integer positioned bandpass signal, the theoretical minimum sampling frequency of f S = 2 BW CH is suitable for sampling. The sampled signal spectrum for the even (black) and odd (red) integer positioned bandpass signal in Figure 1.10a are shown in Figure 1.10b and Figure 1.10c respectively. Figure 1.10: Sampled Spectrum based on bandpass sampling 10

35 For a non-integer positioned RF bandpass signal, the optimized sampling frequency evaluated from Equation (1.2) results in the sampled signal as shown in Figure 1.10d. The implementation in [5] uses RF sampling down-conversion (RFSD) filter to down-convert the RF bandpass signal to baseband in two steps. For this architecture, the sampling frequency selects the center frequency processed at RF. Hence, keeping value of k constant in Equation (1.2), the change in sampling frequency can be utilized to select particular center frequency at RF [9]. Hence, the carrier frequency can be selected by changing the sampling frequency for sampler stage. After subsampling based down-conversion to low-if, the RFSD filter employs discrete time decimation for the second down-conversion to baseband. The phase difference between two consecutive samples is given by Equation (1.4). Thus, these consecutive samples are separated in to even and odd streams to form in-phase and quadrature paths respectively. Figure 1.11: Spectrum for RF sampling down-conversion filter The frequency spectrum of the down-conversion in RFSD filter is shown in Figure 1.11 [5]. For the sampled IF signal located at f S 4, the closest image is present at f S 2. For this implementation, the mismatch between in-phase and quadrature paths for wideband downconversion is one of the limitations. As the sampling frequency is selected to provide phase difference of π 2 exactly at center frequency f c. As the incoming signal frequency deviates from this center frequency, the phase mismatch is observed. This phase mismatch is given by Equation (1.5). φ max = 2π f t (1.5) Here, t is the time difference between two consecutive samples i.e. 1 f S and f is the deviation of actual signal frequency from center frequency. For example, for the center frequency 11

36 of GHz, signal bandwidth of 20 MHz and sampling frequency of 1072 MHz, this results in maximum phase mismatch of 3.3. In another subsampling implementation [8], the sampler uses an 100 MHz sampling frequency with on-chip tuned LNA. Here, the implementation focuses on narrowband implementation of sampling mixer and rely on the selectivity provided by LNA itself. Also, the implementation completely ignores the importance of the sampling frequency optimization and result in very high noise figure (NF). Next, the existing implementations of multistandard wideband SDR frontends are presented. 1.4 Literature Survey This section presents the existing solutions available in the literature to cater with SDR design and implementation challenges [1 3]. These implementations mainly focus on the analog implementations for SDR with flexible receiver architectures. For many years now, software defined radio (SDR) or digitally reconfigurable radio research has been quite challenging with only a few reported practical prototypes with limited success [2]. The Mitola s architecture in [1] was one of the first implementations for SDR implementation. The architecture relies on low pass filter at the frontend to limit the out of band frequencies before digitizing the signal using ADC. Thus, the architecture is able to process all HF bands utilizing the multiple digital frontends. The receiver doesn t face the problem of 1/f noise as the down-conversion to zero IF is carried completely in digital domain. It provides good flexibility and the ease of adding multiple DSP channels to process multiple signal. The main limitation in the architecture is due to the ADC specifications as the highest received frequency is limited by half of the sampling frequency i.e. to 30 MHz. To break the link between sampling frequency and the input signal frequency, the toshiba s implementation [1], uses analog pre-select filters to tune to Personal Communication Service (PCS) and Digital Cellular Service (DCS) band as anti-aliasing filters. These are followed by complex analog down-conversion mixers using fixed LO frequency to down-convert signal to non-zero IF. Thus, losing the flexibility of variable LO in mitola s architecture. Also, it uses complex ADC one in each of the quadrature paths to digitize the signal. The architecture combines the rejection of analog down-converter and RF preselect filter to achieve the image 12

37 suppression by 70 db. Although, the architecture succeed in separating the sampling rate of ADC and RF frequency, it is limited by the fixed RF preselect filters. The TI s bluetooth receiver [10] utilizes integrate-and-dump sampling to replace the analog down-conversion mixer, followed by the programmable filtering and decimation to achieve the more flexibility than traditional receivers and support the system specifications. The architecture uses the first sampling frequency to place the aliasing channel band in stop band of RF pre-select filter. The tuning LO can select the desired channel from the standard. This is one of the first implementations where the sampler from ADC is moved towards antenna. But as the architecture focuses on tuned frontend, this is still not SDR in conventional sense. The SDR implemented at UCLA, presented in [3], utilizes direct down-conversion to zero IF receiver along with wideband tuning LO to ease the baseband signal processing. The main motivation is to support wideband down-conversion without any pre-select filter in RF. For this purpose, the architecture employs filter cascade performing decimation, down-conversion and filtering to prevent overloading of ADC due to unwanted additional channels present at the baseband. The superhetrodyne receiver architectures [11] and homodyne receiver architecture [12] present wideband operation for multistandard receiver. However, these architectures suffer from requirement of LO frequency comparable to RF and the lack of flexibility. The performance of these receiver architectures are compared in Table 1.2. Based on the literature survey, the research gaps are identified next. 1.5 Research Gaps Based on the literature presented in the previous section, it is concluded that the basic demand of the SDR has been the need for a giant ADC and a powerful enough DSP so that it serves as a universal radio platform receiving almost all radio standards and services. These demands are difficult to meet even in modern CMOS technologies. The existing implementations rely on tunable frontend filtering [1] or focus on tuned frontend [10] or use windband analog down-conversion followed by DTSP at the baseband [13]. The discrete time signal processing has the capability to provide desired flexibility in SDR receiver [3]. This demands a new generation of receiver architectures and RF frontend circuits with digitally assisted RF techniques [14]. The most promising solution to achieve this intermediate 13

38 Table 1.2: performance comparison for receiver architectures year Tech. Supply RF LO IF BW Arch Gain NF IIP3 Power Area nm V GHz GHz MHz MHz db db dbm mw mm 2 [6] JSSC RF Sampling a 0.4 [7] JSSC / NR TI RF Sampling b 5.9 [3] JSSC / <20 Homodyne c 3.8 [12] TCAS-I Homodyne d 0.25 [11] TCAS-I <100 NR Heterodyne e 0.14 a RF amplifier, Switched capacitor down-conversion core and BB buffers are included b Frequency synthesizer, DLL, LNTA, DT RF Signal Processor and BB buffers are included c LNA, Passive mixer, Frequency synthesizer, BB SC Filters are included d Gm cell amplifier, Passive mixer, Frequency synthesizer are included e LNTA, Passive mixer, SC Bandpass filters are included 14

39 goal is by realizing receivers wherein the signals are processed in the discrete-time domain. As it is widely accepted, in deep sub-micron CMOS, time-domain resolution of a digital signal edge-transition is superior to voltage resolution of analog signals [10]. This approach provides additional flexibility in signal processing and brings the ADC close to the antenna which is the intermediate objective of realizing a SDR. Also, the comparison of direct sampling receiver and heterodyne RF receivers presented in [15] suggest that the sampling receivers can be as power efficient as analog heterodyne receivers. This leads us to the sampling receivers, although here, the existing solutions rely on oversampling [6] or time interleaved sampling [7] to utilize discrete time mixing. These architectures mainly suffer from the high sampling frequency generation, phase noise requirement at the sampling frequency and high power consumption for LO generation. Also, the jitter and mismatch effects dominate the receiver performance for TI architecture. The subsampling downconversion relies on lower sampling frequency, thus alleviate the issue of complexity of frequency synthesizer design, power consumption and phase noise requirements. But the quadrature sampling results in poor IQ mismatch at the baseband [5] as they rely on the relation between sampling frequency and center frequency for IQ generation. Some of the implementations focus on tuned frontend gain and ignore the noise folding effect [8] resulting in very high noise figures. Based on the research gap presented, next section presents an architecture as in intermediate step implementation towards the ideal SDR based on the principle of subsampling. 1.6 Proposed Mini-SDR Architecture The literature survey presented in the previous section along with the highlighted research gaps lead to the motivation for subsampling based receiver architecture as an intermediate solution for ideal SDR implementation. The ideal SDR receiver is expected to process all the available communication standards simultaneously with a single receiver chain. The proposed architecture however presents an intermediate solution, hence called Mini-SDR architecture. In this section, the proposed architecture is presented followed by the proposed implementations for the targeted applications. The proposed mini-sdr architecture is shown in Figure 1.12 and is based on subsampling down-conversion to first IF followed by the discrete-time mixing based quadrature down- 15

40 conversion to baseband. The tunable LNA provides additional selectivity along with the frontend filter. The second bandpass filter after the subsampling mixer is utilized for image rejection required, as explained in Section , in subsampling down-conversion before downconversion to baseband. The subsampling results in lower sampling frequency and discrete TI Discrete-time Mixing Down-conversion RF Filter LNA Subsampling Down-conversion Subsampling BPF LP IIR BB I RF in f RF Mixer T/H f IF = f s /4 LP IIR BB Q Clk Buffer Clk Buffer f s 1/8 duty cycle & CLK driver Figure 1.12: Proposed Mini-SDR architecture time mixing provide a precise phase difference between in phase and quadrature LO resulting in very accurate quadrature down-converted signal at baseband. Although, the second stage requires time interleaved paths, as the signal is sampled at a lower sampling frequency, the second stage LO generation is much simpler as compared to time interleaved oversampling receiver (Section ). The architecture combines the benefits of subsampling down-conversion and discrete time mixing to optimize the receiver chain performance. So, in conclusion, the architecture results in simpler and less power hungry clock path design, provide additional flexibility in terms of discrete domain signal processing and provides a capability to transfer part of signal processing such as gain and filtering into the digital domain. The proposed mini-sdr architecture is adopted for three target applications and the corresponding implementations are introduced next. 16

41 1.6.1 Mini-SDR Based Electronic Attack (EA) System for Electronic Warfare (EW) Applications The electronic warfare (EW) systems are utilized to determine, exploit, reduce, or prevent the hostile use of electromagnetic spectrum and retains friendly use of electromagnetic spectrum. These systems are mainly classified as electronic support measure (ESM) and electronic countermeasure (ECM), passive EW and active EW. The ESM systems intercept the enemy electronic systems in a real-time environment and gather information about enemy systems e.g. radar warning receiver (RWR). The ECM or EA systems are actions taken to prevent or reduce the enemy s effective use of the electromagnetic spectrum. It is typically an ESM that intercepts and acts based on the enemy use of electromagnetic spectrum. Such systems rely on techniques like jamming and deception to reduce the effectiveness of the enemy EW systems. In EA systems, detection of inbound radar signals is challenging owing to unknown signal parameters. In addition, frequency agile radar systems require continuous carrier frequency coverage over wideband [16]. Pulse compression techniques are typically used in radar signal processing for enhancing the range resolution. This increases the instantaneous bandwidth requirement for these systems [17]. Thus, wideband coverage and high instantaneous bandwidth processing capability are necessary in EA receivers. In summary radar signal detection with unknown parameters, wide-band frequency operation and high instantaneous bandwidth render the design of these jammer systems challenging. ADC Memory DAC LO Figure 1.13: Traditional DRFM based EA system DRFM is a key component of deceptive jamming schemes for generating false radar targets in ECM systems [16, 18, 19]. In these systems, high-speed sampling and digital memory are utilized to receive, store and re-transmit radio frequency and microwave signals as shown in Figure 1.13 [16]. The DRFM stores the signal which is then recreated with a small delay and/or Doppler frequency shift. Thus, giving a deceptive range and speed of the aircraft. A 17

42 more detailed block diagram of general EA system based on DRFM is illustrated in Figure Here, additional signal processing can be implemented based on the capabilities of the controller and then the received signal can be re-transmitted back. In an EA system, digital instantaneous frequency measurement (DIFM) receiver is used to determine instantaneous carrier frequency which is used by DRFM subsystem to generate control signals for font-end [20]. IFM receivers are typically an acquisition receiver to identify the instantaneous carrier frequency for the incoming RF signal to set-up a slower, narrow band, high-resolution receiver. Figure 1.14: Block diagram of general DRFM system For EW application, there are very few integrated implementations [19, 21 24] and many of them focus on IF and baseband sampling signal processing. Also, none of previous implementations have the capability to detect the incoming RF signal, identify it s carrier and instantaneous bandwidth, store the samples, process and re-transmit the received signal back as a standalone system. In this thesis, a standalone electronic attack (EA) transceiver system based on DRFM for EW application is proposed based on Mini-SDR [25, 26]. The main challenge in implementation of integrated solution of active ECM system is the real time detection of the incoming radar signal needed before reception. Here, an architecture shown in Figure 1.15 is proposed for system-onchip (SoC) implementation of wideband channelized transceiver based on DRFM. The proposed integrated architecture employs wideband channelized subsampling transceiver framework [25] frontend with a series of sub-band filters and non-parametric power spectral density (PSD) estimation method to estimate the carrier frequency and bandwidth of the incoming pulse radar signals with unknown parameters. Thus, integrating the functionality of IFM receiver in the system. The RF frontend is modelled in Verilog-AMS and the digital part is implemented 18

43 Antenna RF S/H mixer FIR Filter f C f IF S f S Clock Path DLL Multiband Receiver Subband LNA Filter RF Subband Discrete RF A/D Switch Filter Time Switch Mixer Subband Pipelined Filter ADC DLL Subband LNA Filter RF Subband Discrete RF A/D Switch Filter Time Switch Mixer Subband Pipelined Filter ADC DLL To ADC MEMORY Digital Control Detection Storage Analysis System on Chip Multiband Transmitter PLL MOD Gain Compensation Buffer Amplifier D/A Analog VGA Switch Upconversion Mixer Reconstruction Gain Filter Compensation PLL MOD Digital Frequency Synthesizer Figure 1.15: Simplified block diagram of the proposed electronic attack system with Simulink-Matlab. The proposed system is verified for linear frequency modulated, constant carrier frequency and costas phase coded pulse radar signals. The system level co-simulation is conducted to validate the input dynamic range from 60 dbm to 20 dbm for continuous carrier frequency coverage from 1 GHz to 10 GHz and 300 MHz instantaneous bandwidth. The minimum delay between reception and re-transmission of 13 PRI is achieved for the system. Also, a similar EA system is implemented for continuous carrier frequency from K band to Lu band (1 GHz to 20 GHz) radar signal with up to 300 MHz instantaneous signal bandwidth. These architectures are presented in detail along with the implementation details and simulated results in Chapter Mini-SDR Based Dynamically Reconfigurable Multistandard Subsampling (DRMS) Receiver Multistandard subsampling receivers [13,27 30] are reported in the literature. The architecture in [13] utilizes two-stage subsampling based down-conversion along with the tuned filters at each stage to improve the overall performance. The architecture in [27] does not include the frontend LNA and employs the IF filtering to receive two or more standards simultaneously. The architecture proposed in [28], employs two sampling paths with tunable RF filter and signal processing algorithm to alleviate the effect of jitter and sampling frequency variations. This 19

44 RF RF Filter LNA RF Frontend (Verilog-AMS) RF Switch GSM UMTS WLAN RF Switch Subsampling Mixer IF I fs S IF Q Clock Path DLL Discrete Time Filter ADC Digital Signal Processing (Matlab/ Simulink) Figure 1.16: Proposed multistandard receiver architecture for GSM, UMTS and WLAN standards implementation lacks the effect of the complete RF frontend as the LNA is not included. None of the above implementations provides the capability to sense the standard of the incoming RF signal on their own. The implementation in [30] employs a tunable RF filter along with subsampling receiver and ADC to identify the free spectrum for cognitive radio and can receive two or more standards simultaneously. This implementation does not include an LNA and the capability to dynamically identify and change the band used for reception. Also, these architectures focus primarily on the optimization of the sampling frequency for the system level performance and rely on a reconfigurable filter or focus on the baseband system optimization. But, none of the earlier implementations provides the capability to dynamically detect the standard and estimate the signal bandwidth using the incoming RF signal. The second architecture proposed in this thesis is a Mini-SDR based dynamically reconfigurable multistandard subsampling (DRMS) radio receiver shown in architecture shown in Figure 1.16 based on the principle of subsampling [31, 32]. The main features of the proposed architecture include firstly, the capability of dynamically identify the carrier frequency and the standard in which the signal is present and estimate its bandwidth. Secondly, when the radio is switched on, the receiver dynamically tunes to the standard of interest based on the signal bands present at the RF input. The architecture has the capability to process a single communication standard at a time. The proposed architecture presents a way to identify the communication standard available at the current time and location. In such a case where all the communication standards are available, the desired standard can be selected through the digital control. Thirdly, the RF frontend resources such as antenna, RF BPF, low noise amplifier (LNA), sub- 20

45 sampling mixer and ADC are shared between the three targeted standards and fourthly, since the proposed radio uses subsampling, the clocking circuits operate at relatively low frequency leading to less complex frequency synthesizers and consequently low power consumption. In addition, the discrete-time signal processing close to the antenna at a reduced sampling rate decreases the power consumption in the RF frontend which are usually battery powered. The proposed receiver architecture RF frontend is modelled in Verilog-AMS behavioural models and the digital signal processing is implemented in Simulink-Matlab. The complete receiver architecture has been verified to detect and process three different bands belonging to three different standards (GSM, UMTS and WLAN) with the carrier frequency ranging from 0.9 GHz to 2.5 GHz with a maximum signal bandwidth of 22 MHz and the input dynamic range from 109 dbm to 20 dbm. The proposed architecture is further explained in Chapter 3 and the co-simulated results are presented along with system level performance of the receiver Mini-SDR Based Dual-band Subsampling WLAN Receiver To provide more flexibility in the receiver frontends, digital intensive receiver architectures with passive structures are proposed. Mixer first receivers [33] and N-path Filtering based receiver [34] provide the wideband performance with high flexibility and tuning for SDR. RF sampling receivers using TI RF sampling [7] and discrete-time mixing [6] are also reported. Owing to the oversampling ratio of up to 8 times in these receivers, high-performance complex frequency synthesizers are needed with stringent phase noise requirement. Moreover, clocking schemes employed in time-interleaved RF sampling architectures result in additional timing jitter and mismatch offsets [7]. These challenges are alleviated in the sampling receivers, called subsampling receivers [5, 8, 35] where the employed bandpass sampling principle results in less than the Nyquist sampling frequency. This leads to the less-complex and less power hungry frequency synthesizers. The third implementation proposes a dual-band subsampling receiver, shown in Figure 1.17, with subsampling frequency optimization to meet an ultimate receiver EVM of 40 db [36]. Also, a systematic system level optimization of EVM with respect to major receiver impairments like frequency synthesizer phase noise, IQ mismatch, sampling frequency and the unit capacitor in switched capacitor (SC) filter is proposed. subsampling frequency optimization proposed in this work has multi-fold advantages: (a) reduced noise folding in subsampling mixer leading 21

46 2.4 GHz LNA Subsampling IFA 2.4 GHz RX Decimation Filter RF 2g,in GHz f s,2g GHz LNA out Clk Buffer Mixer T/H f s,mixer Mix out Clk Buffer f s,filter IF out clk 1 clk 2 clk 4 M LO Divide by 24 clk 3 clk 23 clk 24 firi out Measurement Buffers BBI 2g,out 2.4 GHz Receiver Chain M firq out BBQ 2g,out 5 GHz Receiver Chain M firi out BBI 5g,out f s,5g GHz Clk Buffer Clk Buffer f s,mixer f s,filter clk 1 clk 2 clk 4 LO Divide by 24 clk 3 clk 23 clk 24 Measurement Buffers RF 5g,in GHz 5 GHz LNA LNA out Mixer T/H Subsampling Mix out IFA IF out M 5 GHz RX Decimation Filter firq out BBQ 5g,out Figure 1.17: Block diagram of the proposed dual-band subsampling receiver for 2.4 GHz and 5 GHz WLAN bands to lower noise figures (b) less complex and less power hungry frequency synthesizer (c) less complex, reconfigurable, less power hungry decimation filter operating at clock rate of 90 MHz. In addition, proposed receiver is capable of down-converting multiple frequency bands to a constant IF, with a single wideband, tunable and switchable LNA. The continuously tunable-gain and tunable-band common-source active balun LNA with buffered resistive feedback [37] has inherent wideband architecture and cane be implemented to process both the WLAN bands with a single LNA. However, for implementations simplicity, two parallel receiver chains are implemented in this work. A subsampling down-conversion mixer working at a sampling frequency (f s ) in the range of 1.78 GHz to 2.15 GHz is interfaced to the output of the LNA. The resulting IF is located in the range of 445 MHz to 540 MHz. Further, this work proposes to reconfigurable decimation filter to baseband, with filter optimization at the circuit level and layout level to reduce IQ gain and phase mismatch with low-frequency clock operation thanks to decimation. A test chip is implemented in 1.2 V 65-nm CMOS technology to prove the concepts proposed, including major system level, circuit level and layout level optimizations. The implementation 22

47 occupies a total active area of 0.72 mm 2 with a total power dissipation of 61 mw. The complete receiver chain including major blocks such as feedback LNA, subsampling mixer and the bandpass filter is measured with an external clock signal for an MCS7 RF input signal of ac standard. The receiver shows an excellent ultimate receiver EVM of 40 db is demonstrated over RF input power range of 19 db. Also, for the complete receiver, the NF of 11.5 db and the IIP 3 8 dbm are achieved. The system level design and optimizations and the circuit implementations are presented in Chapter 4 and the layout optimizations and the CMOS implementation details and the measured results are presented in Chapter Thesis Contributions In this thesis, based on the sub-sampling theory, highly flexible frontends are developed for the multistandard reconfigurable RF radios. The major contributions are listed as follows- (a) Based on the subsampling concept, a Mini-SDR architecture is proposed which alleviates the challenges identified as the research gaps in the existing implementations. (i) Mini-SDR based electronic attack (EA) system is proposed for electronic warfare (EW) applications with the standalone detection, storage and re-transmission feature for SoC implementation. (ii) Mini-SDR based dynamically reconfigurable multistandard subsampling (DRMS) receiver is proposed with the capability to identify and change the standard of the incoming RF signal. (iii) Mini-SDR based dual-band subsampling WLAN receiver architecture is proposed for IEEE ac standard with the system level optimizations. (b) This is the first subsampling receiver implementation demonstrating the performance for both narrowband and wideband RF frequency at 2.4 GHz and 5 GHz respectively. (c) A proof-of-concept prototype of the dual-band subsampling receiver is implemented in 1.2 V 65-nm CMOS technology. (d) The test-chip of the dual-band subsampling receiver designed, simulated, fabricated and it s performance characterized by lab measurements. 23

48 1.8 Thesis Organization The thesis is organized as follows Chapter 2 presents the mini-sdr based standalone electronic attack (EA) system for electronic warfare (EW) applications without the need for a separate instantaneous frequency measurement (IFM) receiver. The proposed system can estimate the incoming radar signal specifications, receiver, store and re-transmit the signal. The system specifications, standalone detection algorithm and performance results are presented in detail. This is followed by the mini-sdr based dynamically reconfigurable multistandard subsampling (DRMS) receiver architecture for SDR receivers in Chapter 3. Here, the system level optimizations and performance results are presented. In Chapter 4, the CMOS dual-band subsampling receiver architecture for IEEE ac standard is proposed alongwith system level optimizations, receiver specifications and circuit level implementations. Chapter 5 presents the implementation details and the measurement results for the dual-band WLAN subsampling receiver. The thesis conclusions and future work are presented in Chapter 6. 24

49 Chapter 2 Mini-SDR Based Electronic Attack System for Electronic Warfare Applications In this chapter, the electronic attack (EA) system is proposed based on the principle of subsampling and mini-sdr architecture. The EA system is a multiband channelized transceiver with the standalone capability to identify an incoming radar signal. Section 2.1 presents the introduction and motivation for the proposed architecture. Then, the proposed architecture is presented in Section 2.2. Here, the state machines used of for the detection, storing and re-transmission of the radar signals are also explained. This is followed by the performance results presented in Section 2.3 for the test cases defined in Table 2.1. The chapter is concluded in Section Introduction The electronic warfare is defined as a military action whose objective is to control the electromagnetic spectrum in presence of a non-friendly communication system. This objective is completed through the offensive electronic attack (EA) system also known as electronic counter measure (ECM) system, defensive electronic protection (EP) system and intelligence gathering and threat recognition electronic warfare support (ES) system. The block diagram for an electronic warfare system application is shown in Figure 2.1. The EP and ES systems focus on intelligence gathering, signal detection, signal parameter estimation and protection of own communication whereas in the EA system, an RF signal is re-transmitted to disrupt the normal operation of the non-friendly radar system. The block diagram of an EA system is shown in Figure 2.2. Traditionally, relies on independent DRFM system for signal reception and 25

50 Radar System EW System Figure 2.1: Block diagram of traditional electronic warfare application re-transmission and a digital instantaneous frequency measurement (DIFM) system for signal parameter estimation operation. The DIFM system identifies the incoming radar carrier fre- ADC Memory DAC ADC LO Processor DRFM System EA System Center frequency Instanteneous BW Signal type Signal parameters LO IFM Receiver Figure 2.2: Block diagram of traditional EA system based on DRFM quency and the DRFM is then utilized to process and store and re-transmit the signal. Hence, the EA system needs both the DRFM and DIFM modules to function properly. However, this results in bulky complex systems. The proposed simulated architecture presents a standalone EA system without the need for separate DIFM system. Hence, the need of additional subsystem is eliminated resulting in less complex, on-chip low power implementation. The implementation of integrated circuits for ECM system is difficult owing to wideband operation and high instantaneous bandwidth of the incoming pulse radar signal. Low noise amplifier (LNA) is required to provide high gain sufficient to overcome mixer stage noise as well as linearity to prevent inter-modulation components due to presence of strong interferes [38,39]. Thus, its performance is bound by the noise figure on the lower side and linearity on higher input amplitude. Achieving these trade-off over ultra wide bandwidths (up to 40 GHz) is grim. Although, shunt-shunt dual resistive feedback in [40] with dc to 22 GHz bandwidth and similar 26

51 feedback with wideband input pi-matching network in [41] with 1.6 GHz to 22 GHz bandwidth is reported. They result in elevated noise figure. The distributed amplifier in [42] while providing high bandwidth from DC to 17 GHz suffers from a large area and high power dissipation. The integrated circuit (IC) implementation for ECM systems is complex owing to area and power constraints in current technologies. Most of the integrated solutions presented for DRFM applications focus on IF or baseband processing and assume independent wideband frontend for signal down-conversion. Such implementations are discussed in [19, 21 24]. Single bit, 0.5 GHz DRFM [21] in 1.25 µm CMOS marks an initial attempt for delay line implementation. The control circuit for DRFM system with emphasis on signal processing [22], VHDL implementation of 6 bit DRFM control [23] and a control circuit for DRFM in 0.18 µm CMOS technology [24] are reported. The implementations [19, 21 24] are based on Nyquist sampling and suffer from the disadvantages of high sampling rates. This places a very stringent requirement on dynamic range and resolution of ADC. Thus, resulting in high power dissipation for ADC. Also, these implementations rely on separate frontend and IFM receivers. Field programmable gate array (FPGA) and DSP processor implementation for DRFM processing blocks is presented [19]. This implementation lacks the advantages of integrated circuits. Another form of active jamming performed in ECM systems is active cancellation as presented in [43 45]. This approach uses signal blanking for cancelling the echo for the target system. The use of subsampling in RF signal processing for radar applications is presented in [46, 47]. These implementations use single bit ADC with sub-nyquist sampling to receive and detect the incoming radar signal. The limitation of low instantaneous dynamic range is present in this implementation due to use of single bit ADC. The model presented in [48] also utilizes the sub-nyquist sampling for DRFM, but lacks the implementation details for system hardware implementation. Also, it is generally observed that, although the carrier frequency is high, the information bandwidth is very low for these systems [49]. Based on these implementations, the architecture for the standalone EA system is presented next. 27

52 2.2 Proposed Electronic Attack System Architecture The proposed integrated architecture shown in Figure 2.3 employs wideband channelized subsampling transceiver framework [25] frontend with a series of subband filters and non-parametric power spectral density estimation method to estimate the carrier frequency and bandwidth of the incoming pulse radar signals with unknown parameters. Thus, integrating the functionality Antenna RF S/H mixer FIR Filter f C f IF S f S Clock Path DLL Multiband Receiver Subband LNA Filter RF Subband Discrete RF A/D Switch Filter Time Switch Mixer Subband Pipelined Filter ADC DLL Subband LNA Filter RF Subband Discrete RF A/D Switch Filter Time Switch Mixer Subband Pipelined Filter ADC DLL To ADC MEMORY Digital Control Detection Storage Analysis System on Chip Multiband Transmitter PLL MOD Gain Compensation Buffer Amplifier D/A Analog VGA Switch Upconversion Mixer Reconstruction Gain Filter Compensation PLL MOD Digital Frequency Synthesizer Figure 2.3: Simplified block diagram of the proposed electronic attack system of instantaneous frequency measurement (IFM) receiver in the system. The sub-nyquist bandpass sampling [50] is employed for frequency down-conversion from RF to baseband. Through intentional aliasing, this technique leads to significant reduction in sampling frequency. The proposed system is verified for linear frequency modulated, constant carrier frequency and costas phase coded pulse radar signals. These test cases are inspired from [51] and their properties are presented in Table 2.1. The RF frontend is modelled in Verilog-AMS and the digital part is implemented with Simulink-Matlab. The system level co-simulation is conducted to validate the input dynamic range from 60 dbm to 20 dbm for continuous carrier frequency coverage from 1 GHz to 10 GHz and 300 MHz instantaneous bandwidth. The minimum delay between reception and re-transmission of 13 PRI is achieved for the system. Bandpass sampling down-conversion used in proposed architecture results in significant reduction in the sampling frequency. This alleviates the stringent requirements of dynamic range and power dissipation in analog-to-digital converter (ADC) design. To avoid inversion of sam- 28

53 Type of Radar Signal Table 2.1: Signal Parameters for test input signals Up-chirp Signal Single Carrier Frequency Signal Costas Phase Coded Signal Input Signal Power 60 dbm 60 dbm 60 dbm Input SNR 20 db 20 db 20 db Carrier Frequency 2.75 GHz 8.2 GHz 1.5 GHz Instantaneous Bandwidth 300 MHz MHz Pulse Width 1 µs 1 µs 1 µs Pulse Repetition Interval 100 µs 100 µs 100 µs No of phases in pulse pled spectrum at base band, only odd values of m lower than m max are chosen in Equation (1.2). Also, the sampling frequency less than 3 GHz is chosen for easier design of ADC. For example, in case of up-chirp signal with carrier frequency 2.75 GHz and 300 MHz bandwidth (first test signal), the f L and f H are 2.6 GHz and 2.9 GHz respectively. The calculated sampling frequency from Equation (1.2) is 2.2 GHz with oversampling ratio above 7. Table 2.2: Proposed EA system specifications Parameter Frequency of Operation Instantaneous Bandwidth Noise Figure Sensitivity Input Dynamic Range ADC Resolution Transmitted Power Value L to C Band (1 GHz 10 GHz) up to 300 MHz (detected from incoming signal) from 2 db to 8 db (based on DRFM channel) 60 dbm (at 20 db SNR) 60 dbm to 20 dbm (at 20 db SNR) 8 bits maximum 0 dbm Table 2.3: DRFM channels specifications DRFM Channels Number of Subband filters 1 GHz 5.5 GHz 7 5 GHz 10 GHz 6 The target system specifications are presented in Table 2.2. The proposed system covers continuous carrier frequency from 1 GHz to 10 GHz with worst case sensitivity of 60 dbm 29

54 with instantaneous bandwidth of 300 MHz. The system can process pulse radar signal from 60 dbm to 20 dbm with input signal-to-noise (SNR) ratio of 20 db. The noise figure (NF) of 2 db to 8 db based on the DRFM channel is proposed. The instantaneous signal bandwidth is estimated based on incoming radar signal. Thus, better sensitivity can be achieved for lower bandwidth signals. For example, with 150 MHz detected bandwidth, 20 db SNR and 8 db NF, 63 dbm sensitivity can be accomplished or with 300 MHz of bandwidth, 8 db NF, 10 db SNR and 70 dbm sensitivity is achieved. The system is proposed for 40 db input dynamic range. This translates to requirement of 8 effective bits with the proposed time interleaved pipe-lined ADC for converting discrete samples into digital data. EA system gain (db) RF frequency (GHz) Figure 2.4: Target system gain profile used for implementation The multiband receiver in Figure 2.3 is divided into two parallel DRFM channels 1 GHz to 5.5 GHz and 5 GHz to 10 GHz as listed in Table 2.3. DRFM channels have 500 MHz overlap to cater overlapping pulse radar signal between the two channels. Each receiver channel employs subband filters for detecting the incoming radar pulse without prior knowledge about signal parameters. The number of subband filters in a DRFM channel contributes to the detection time of pulse radar signal. These filter are designed with 200 MHz of overlap to process overlapping signal between subband filters. Also, their bandwidth is optimized according to bandpass sampling requirements (Section 1.2). For the first DRFM channel seven filters with specification presented in Table 2.4 are employed. This table also presents the sampling frequency calculated from Equation (1.2) corresponding to each subband filter. For simplicity, only three subband filters are displayed in Figure 2.3 for each channel whereas the actual number of filters are 30

55 mentioned in Table 2.3. The digitally controlled RF switches are utilized to activate subband filters. For each receiver channel, corresponding transmitter channel with matched specifications can be observed in multiband transmitter. Both DRFM channels aim to process pulse radar signals concurrently. Hence providing processing capability for multiple radar signals. The system is proposed for shared wideband antenna between receiver and corresponding transmitter channel. Filter Number Table 2.4: Subband filter parameters for the first EA channel Lower Cut-off Frequency (f L GHz) Upper Cut-off Frequency (f H GHz) Information Bandwidth (BW MHz) Sampling Frequency (f S GHz) A discrete time mixer is utilized to down-convert pulse radar signals in the receiver channel as observed in Figure 2.3. The mixer consists of a sample and hold block for sampling downconversion, discrete time low pass FIR filter and clock path. The clock for the down-conversion mixer is generated from digitally controlled delay locked loop. So, the sampling frequency for down-conversion can be controlled digitally and changed as necessary. The multiband transmitter uses common digital to analog converter and a reconstruction filter for both transmitter channels. The signal is later transferred to desired transmitter channel through digitally controlled analog switch. The variable gain amplifier is used in the transmitter to maintain desired gain profile for the system. An example of system gain profile used for implementation is shown in Figure 2.4. For the analog up-conversion mixer, the local oscillator frequency generated by the digital frequency synthesizer is used to generate up-converted RF signal. The power amplifier used for this up-converted signal produces maximum output power of 0 dbm. The system functionality is explained using detection phase, processing phase and transmission phase. The control state machines used for these three phases are presented in Figure 2.5, Figure 2.6 and Figure 2.7 respectively. 31

56 first subband filter selected, filtered signal sampled with corresponding sampling frequency and store downconverted samples Count=2 Filter2 Filter3 Filter4 Count=5 Filter1 Count=3 Count=4 Filter5 Count=1 Idle Detect_done=1 Detect_start=1 Detect Filter7 Count=7 Count=6 Filter6 Estimate the center frequency and bandwidth and calculate the sampling frequency for storage. Figure 2.5: Detection state machine Detection Phase Firstly, the proposed system detects the incoming pulse radar signal using different subband filters in the DRFM channel from Figure 2.3. The control state machine for selection of subband filter corresponding to the first DRFM channel is presented in Figure 2.5. Each filter state corresponds to activation of the corresponding subband filter for first channel. The subband filters are triggered by digitally controlled RF switches. Each filter is activated for a pre-defined time interval to ensure the occurrence of at least two radar pulses. These filters are needed to ensure a precise portion of entire DRFM channel spectrum is passed on to the sampling mixer. This permits the selection of suitable sampling frequency in down-conversion mixer without prior knowledge of incoming signal bandwidth. This sampling frequency is listed in Table 2.4 corresponding to each of the subband filters. The sampling clock for discrete time mixer is produced through delay locked loop. The signal after down-conversion is low pass filtered in discrete domain to separate the baseband spectrum. As the signal after filtering is discrete, re-sampling is not necessary at input of ADC. A non-parametric power spectral density (PSD) estimation technique is used to estimate the signal bandwidth and carrier frequency from the digital baseband samples. The method employs windowed Fourier transform with appropriate averaging for detection of pulse radar signal in the presence of white gaussian noise. This methodology, referred to as Welch method 32

57 Storing for pre-defined time interval for PRI and pulse width estimation. start_storing stop_storing Idle Storing Processing proc_done Edge detection and PRI estimation Store extracted pulses in the buffer Figure 2.6: Storage state machine highlights the signal by diminishing the noise level through an averaging process [52]. With averaging of spectra containing the signal and noise, the variance of the spectrum is the variance of the noise. A threshold based on the noise variance is employed after estimating the PSD corresponding to each subband filter. As a rule of thumb, the outer edges of the scattered spectrum extend up to 3 σ. It concludes to the fact that the upper edge of the noise spectrum is always at 6 db above mean power in the power spectrum [52]. This (mean of PSD + 6 db) is chosen as the detection threshold for estimating the band edge frequencies and instantaneous bandwidth from the digital baseband samples. All the subband filters are activated sequentially as per Figure 2.5 to acquire baseband samples corresponding to subband filtered signal for the first DRFM channel. The individual spectra provided by the PSD estimation and thresholding method are concatenated to form the overall channel spectrum. Therefore an inclusive estimate of instantaneous bandwidth and carrier frequency for complete system spectrum is recorded. Parallel operation is performed for the second DRFM channel concurrently. The detection time depends on the predefined time utilized for detection of a signal in a subband filter and the number of filters in that DRFM channel (Table 2.3). Hence the number of subband filter is minimized to reduce the detection time. The PSD for linear frequency modulated, constant carrier frequency and costas phase coded test signals are laid out in Figure 2.9a, Figure 2.10a and Figure 2.11a along with corresponding thresholds. These results are described in more detail in Section

58 Get oldest entry from the buffer of pulses Keep transmitting till last sample of the signal Idle Tx_on Transmission Counter expired Yes Counter No Is buffer empty Tx_completed Figure 2.7: Transmission state machine Storing and Processing Phase The state machine for storing and processing of the pulses is shown in Figure 2.6. The subband filters are activated only during detection and once signal characteristics are extracted, these filters are bypassed during storing state. The sampling frequency computed based on the estimated signal parameters from detection phase is utilized to acquire further pulses. The selection of sampling frequency is carried out as demonstrated in Section 1.2. In the processing state, the stored digital samples in memory are processed to estimate radar signal parameters such as pulse width and PRI. The extracted pulses from stored samples are stacked in to a FIFO buffer and further utilized to classify the incoming pulse radar signals. The classification of input radar signals is performed on the basis of instantaneous frequency estimation carried out on stored digital pulses. Typically Fourier analysis is employed on conventional non-stationary signal for instantaneous frequency estimation. A limitation of this analysis is that the frequency resolution is affected by the size of short stationary duration under consideration [53]. To overcome this drawback, Wigner-Ville Distribution [54] provides instantaneous energy information of the signal at specific instants of time and it is a bi-linear time-frequency transform. The marginal densities of Wigner-Ville distribution are utilized to calculate the energy density in time and frequency respectively. The Wigner-Ville distribution is specified by Equation (2.1). W x (n, ω) = 2 + m= x(n + m) x (n m)e j2ωm (2.1) 34

59 where x(n) is an input signal samples in time, ω is the frequency variable and m is displacement of n. This distribution looks symmetrical to the left and right sides of the signal at a distance m 2. Time frequency analysis for stored pulses of all three test signals are presented in Figure 2.9b, Figure 2.10b and Figure 2.11b respectively. These results are reviewed with detailed explanation in performance results Section Transmission Phase The transmission state machine is presented in Figure 2.7. The transmission is started after processing the stored samples. After every transmission, if the buffer is not empty, the counter is started to ensure detected PRI is maintained for the output of the system. After the counter expires, the earliest entry from the buffer of the pulses is transmitted and the process goes on until the buffer is empty after which detection can be launched to acquire new pulses. After the transmission is completed, acquisition of pulses and storing is started until the counter expires. A desired RF signature can be added to the stored pulse in terms of Doppler shift and/or time delay after processing in memory. Baseband digital samples for pulses are converted back to analog information signal using digital-to-analog converter (DAC). After DAC, two separate transmission channels can be observed in Figure 2.3. These transmitter channels possess characteristics matched to corresponding receiver channels. A variable gain amplifier (VGA) is employed to provide an adjustable gain to implement desired overall system gain profile. The system gain profile used for implementation is shown in Figure 2.4. Gain variation in VGA in transmitter exhibits the system gain profile that represents the radar cross section (RCS) of the system. The target system can provide any system gain profile within db. The amplified analog baseband signal is up-converted using analog up-conversion mixer utilizing LO frequency based on detected radar signal carrier frequency and baseband intermediate frequency. The power amplifier is assumed to provide maximum 0 dbm output power. Additional external power amplifier is required to provide required before transmitting the pulses by the shared antenna. 35

60 2.3 Performance Results The co-simulation setup used for Cadence-Simulink simulation is illustrated in Figure 2.8. The analog frontend transceiver is modelled in Verilog-AMS. The digital control machines are implemented in Simulink and signal processing algorithms are realized in Matlab. CADENCE Frontend Verilog-AMS Radar signal A/D output SIMULINK Control signals Control state machines MATLAB Welch algorithm Time frequency analysis Figure 2.8: Co-simulation setup The system uses nine control signals in simulink to control various analog blocks in RF frontend. The control signal for RF switches, frequency control for delay locked loop (DLL), gain control for variable gain amplifier (VGA) and frequency control for digital frequency synthesizer are required for each channel. Apart from these, the common control for analog switch is required in multiband transmitter. Three state machines are used in Simulink to control the RF frontend. These are namely the detection, storing and processing and re-transmission state machines. The detection state machine (Figure 2.5) performs the operation of estimating the carrier frequency and bandwidth of the incoming radar signal. Thus the principle of IFM receiver is integrated in the detection state machine. The storing and processing state machine (Figure 2.6) processes the stored samples to identify edges in samples and extracted the pulses. Further processing for time frequency analysis is also carried out in this state machine. The last state machine (Figure 2.7) is used for re-transmitting the reconstructed pulses with desired system gain profile, delay and PRI. This section presents the detailed performance results for the electronic attack system.the three test cases used to evaluate the proposed system are S-band up-chirp linear frequency modulated pulse radar signal, X-band single carrier pulse radar signal and L-band Costas phase coded pulse radar signal. Theses test signals are presented in Table 2.5. Due to limitations of the simulation setup, the pulse widths and PRIs chosen for implementations are 100 ns and 500 ns as opposed to 1 µs and 100 µs respectively for all the test cases. 36

61 Type of Radar Signal Table 2.5: Signal Parameters for test input signals Up-chirp Signal Single Carrier Frequency Signal Costas Phase Coded Signal Input Signal Power 60 dbm 60 dbm 60 dbm Input SNR 20 db 20 db 20 db Carrier Frequency 2.75 GHz 8.2 GHz 1.5 GHz Instantaneous Bandwidth 300 MHz MHz Pulse Width 1 µs 1 µs 1 µs Pulse Repetition Interval 100 µs 100 µs 100 µs No of phases in pulse Chirp Pulse Radar Signal The S band up-chirp pulse radar signal is the first test signal utilized for the system verification. In Figure 2.9a, the TH3, TH4, TH5 represents the thresholds for third, fourth and fifth subband filters in first DRFM channel. After estimating the mean of the averaged periodogram, Mean + 6dB thresholds are computed as dbw/hz, dbw/hz and dbw/hz respectively. The detected signal bandwidth is 320 MHz in the fourth subband filter Single Carrier Frequency Pulse Radar Signal In Figure 2.10a, TH3, TH4 and TH5 represent the calculated thresholds for third, fourth and fifth subband filters in second DRFM channel for single carrier radar signal. The lower cutoff of 8.1 GHz is detected in the fourth filter with TH4 = dbw/hz and the upper cutoff of 8.3 GHz is obtained from the fifth filter with TH5 = dbw/hz resulting to detected bandwidth of 200 MHz Phase Coded Pulse Radar Signal Similarly, for the third test signal of costas phase coded radar signal (Figure 2.11a), TH1, TH2 and TH3 represent the calculated thresholds for first, second and third subband filters in first DRFM channel. The lower cutoff of 1.33 GHz with TH1 = dbw/hz and the upper cutoff of 1.73 GHz with TH2 = 145 dbw/hz is obtained from the second filter resulting in the detected bandwidth of 400 MHz. 37

62 th filter TH4= GHz 2.91 GHz 2.85 Estimated PSD (dbw/hz) TH3= rd filter TH5= Frequency (GHz) th filter MHz Frequency (GHz) Time (µs) (a) PSD for Up-chirp Signal (b) TFA for Up-chirp Signal Figure 2.9: Estimated PSD and TFA for stored samples for up-chirp pulse radar signal listed in Table 2.1 * The dotted line represents the filter threshold and TH1 to TH5 are the threshold for corresponding filter in dbw/hz Summary It can be observed that the detected instantaneous bandwidth is more than the actual bandwidth for all the test signals. The calculation of sampling frequency performed using the detected bandwidth results in extra guard band against the actual signal bandwidth of the pulse radar signal. This results in a robust calculation of the sampling frequency towards minor changes in carrier frequency and bandwidth for incoming radar signal. Time frequency analysis for up-chirp pulse radar signal Figure 2.9b shows continuous increase in carrier frequency from 2.6 GHz to 2.9 GHz in staircase waveform. The signal carrier frequency of 8.2 GHz is observed in Figure 2.10b. The five distinct phases/frequencies present in costas phase coded signal can be observed in their sequence of occurrence in pulse in Figure 2.11b. The performance results for co-simulation are summarized in Table 2.6. The average error in detection of pulse width and PRI for radar signal is below 5 %. The delay between the reception and re-transmission is dependent on the bandpass analog filters and the number of pulses used for detection of each of the filtered radar signal. This can be calculated as D = N F ilter P detection + T processing (2.2) 38

63 rd filter 4th filter 5th filter GHz 8.3 GHz 8.3 Estimated PSD (dbw/hz) TH3= TH4= TH5= Frequency (GHz) MHz Frequency (GHz) (a) PSD for X-band Single Carrier Signal Time (µs) (b) TFA for Single Carrier Signal Figure 2.10: Estimated PSD and TFA for stored samples for constant carrier frequency pulse radar signal listed in Table 2.1 * The dotted line represents the filter threshold and TH1 to TH5 are the threshold for corresponding filter in dbw/hz Type of Radar Signal Table 2.6: Summery of performance results Up-chirp Signal Single Carrier Frequency Costas Phase Coded Signal Input Signal Power (dbm) Input SNR (db) Carrier Frequency (GHz) Sampling Frequency (GHz) Detected Bandwidth (MHz) 320 (300) 200 ( ) 400 (300) Detected Pulse width ( ns) 104 (100) 105 (100) 103 (100) Detected PRI ( ns) 518 (500) 515 (500) 516 (500) Detection Time (PRI) Values in () represent the test case parameters where D is total delay, N filter is the number of subband filters in the DRFM channel, P detetction is the number of pulses used for detection for a subband filter and T processing is time required for processing and re-transmission. Based on Equation (2.2), the delay of 15 PRI and 13 PRI 39

64 st filter 2nd filter TH2= 145 3rd filter 1.6 PSD Estimates (dbw/hz) GHz 1.73 GHz TH1= MHz TH3= Frequency (GHz) Frequency (GHz) (a) PSD for Costas Phase Coded Signal Time (µs) (b) TFA for Costas Phase Coded Signal Figure 2.11: Estimated PSD and TFA for stored samples of costas phase coded pulse radar signal listed in Table 2.1 * The dotted line represent the filter threshold and TH1 to TH5 are the threshold for corresponding filter in dbw/hz are achieved for the first and second DRFM channel respectively. Here the processing time of 1 PRI is assumed. Table 2.7: ECCM signal specifications Type of radar signal ECCM Input signal power (dbm) 40 Input SNR (db) 40 Carrier frequency (GHz) 5.7 GHz 6.3 GHz Number of pulses Pulse Width 20 ns PRI 60 ns Performance of the proposed EA system for an electronic counter countermeasure (ECCM) signal is tested. The ECCM signal specifications are shown in the Table 2.7. The ECCM signal is assumed to have a single carrier: either an f c of 5.7 GHz or an f c of 6.3 GHz with a signal bandwidth of 600 MHz as a pulse radar signal. Also, the ECCM signal has a constant center frequency f c = 5.7 GHz for the first 20 PRIs before changing its center frequency to f c = 6.3 GHz. The ECCM signal is provided to the second channel of EA system for the purpose 40

65 of testing. A total delay of 13 PRI is observed for the detection of the first center frequency located at f c = 5.7 GHz and rest of the 7 pulses are re-transmitted by the EA channel after signal processing and reconstruction. When the pulses with second center frequency at f c = 6.3 GHz arrive, a total 8 PRI is spent for the detection and reacquisition of the ECCM signal. This include, the first pulse for identifying the shift in carrier frequency of ECCM signal from f c of 5.7 GHz to new carrier frequency. The rest of the 7 PRI, calculated from Equation (2.2), by assuming that 3 scanning filters would be sufficient based on the ECCM signal bandwidth for acquiring a new ECCM signal with a different center frequency. After ECCM signal detection, rest of the 12 PRI are used at a new center frequency for re-transmission. Thus the proposed EA system is observed to be robust in the presence of a ECCM system in an enemy radar. The performance of the proposed system is compared with previous implementations in Table 2.8. The previous implementation mainly utilize COTS components for frontend analog transceiver, whereas in this work the integration of the discrete frontend and the processing unit is the main focus. Also, the implementations [55 58] lack in capabilities as the carrier frequency measurement is not available in the system. The implementation in [59] has the capability of instantaneous carrier frequency measurement along with aligned amplitude measurement, but lack in the aspect of supported carrier frequency range. This implementation is scalable only with superior ADC as the processing bandwidth is limited to [0, f S 2 ) where f S is the sampling frequency for Nyquist ADC. The implementation using commercial-off-the-shelf (COTS) frontend with Nyquist ADC and field programmable gate array (FPGA) board to incorporate digital control is presented in [58]. For this implementation, the frontend provides input processing bandwidth of 800 MHz but the overall system is capable of processing up to 200 MHz signal bandwidth. The proposed architecture in this work includes the discrete frontend using subsampling receiver which alleviates the complexity of the ADC and integrates frontend for detection and processing of the incoming radar signal. Also, this architectural solution is scalable for higher carrier frequency coverage with similar performance from ADC/digital-to-analog converter (DAC). Due to elimination of separate IFM receiver, the proposed architecture is highly integrable, less power hungry and low cost solution. Thus, it result in superior choice compared to the previous implementations. 41

66 Table 2.8: Comparison with previous implementations Parameter DRFM channelized receiver [55] COTS DRFM for HIL RES [56, 57] Digital IFM Receiver [59] Digital RF processing for HIL [58] This work Carrier Frequency MHz MHz MHz 2 18 GHz 1-10 GHz Instantaneous bandwidth 500 MHz 800 MHz (100 MHz to 900 MHz) up to 300MHz Sampling Frequency 1.2 GHz # 2 GHz # 1.2 GHz # 2 GHz # up to 3 GHz Carrier Detection Capability Not present Not present Present Not present Present Sampling Nyquist Nyquist Nyquist Nyquist sub-nyquist Architecture DRFM only DRFM only DIFM only DRFM only CMOS Technology Ready DRFM and DIFM Integrated Not Ready Not Ready Not Ready Not Ready Ready Dynamic Range 47 db 15 db 48 db 48 db Re- transmission output Direct Digital synthesis Sample reconstruction frontend Not included Not included Included frontend architecture Minimum Delay for re-transmission NA Sample reconstruction External COTS module Sample reconstruction Integrated Complete analog Complete analog Discrete time 300 ns 13 PRI or 6.5 µs Implementation Simulink PCB with COTS Matlab FPGA Board Cadence-Matlab # ADC Sampling Rate after down-conversion at baseband Depending on detected input signal instantaneous bandwidth, sampling rate at RF sampling mixer Does not include detection time Includes latency in detection and processing (PRI is pulse repetition interval=500 ns) 42

67 2.4 Wideband EA System The proposed architecture for system-on-chip (SOC) implementation is a wide band channelized transceiver as shown in Figure 2.12 along with the system level specifications in Table 2.9. Figure 2.12: Simplified wideband EA system block diagram The front end architecture is divided into parallel EA channels as mentioned in Table 2.9a. However block diagram shows two channels for illustrations. Each channel uses separate wide band antenna with same bandwidth as in Table 2.9a, thus avoiding the losses that may occur due to divider needed for using same antenna for all EA channels. For each EA receiver channel, there is corresponding EA transmitter channel as shown in Figure These frequency bands are formulated keeping in mind constraints for easy antenna realization and practical design considerations for RF front end blocks such as low noise amplifier (LNA), variable gain amplifier, up conversion mixer and power amplifier. All the EA channels are intended to work simultaneously allowing maximum coverage over entire RF spectrum under consideration and 43

68 Table 2.9: Proposed wideband EA system specifications (b) System specifications (a) Wideband EA channels DRFM Channels GHz GHz GHz GHz GHz Parameter Frequency of Operation Instantaneous Bandwidth Noise Figure Sensitivity Input Dynamic Range ADC resolution Value L to K u Band (1-20 GHz) Up to 300 MHz (Detected from incoming signal) From 2dB to 8dB based on LNA Band Up to -60 dbm at 20 db SNR 40dB (-60 to -20 dbm) at 20 db SNR 8 Bits System Gain profile Shown in Figure 2.13 Transmitted Power Maximum 0 dbm Processing Delay Up to 7 clock cycles for ability of system to process more than one simultaneous radar signals. Moreover the EA channels have overlapping spectrum to process the signal present at the edges of the EA channels. As the maximum instantaneous bandwidth for the pulse radar signal is considered to be 300 MHz, overlap of 500 MHz is used to allow processing of the said signal by both adjacent channels to ensure reliable detection and processing Selection of Bandpass Filters Each of the five EA channels listed in Table 2.9a are divided in to several sub-bands using bandpass filters. These filters are used during detection process to filter out-of-band components and facilitate the sampling receiver process. For the first DRFM channel the subband filters are System Gain (db) Frequency (GHz) Figure 2.13: Wideband EA system gain profile used for implementation 44

69 1 0.8 Amplitude Frequency (GHz) Filter Number Figure 2.14: Subband filters responses for first EA channel Table 2.10: Sub-band filter parameters for the first wideband EA channel Lower cut-off frequency (f L ) (GHz) Upper cut-off frequency (f H ) (GHz) Information bandwidth (BW ) (MHz) Sampling frequency (f S ) (GHz) listed in Table It has got seven filters over bandwidth of 4.5 GHz (1 to 5.5 GHz). Also, the corresponding sampling frequencies for each subband are listed in this table. The sampling frequency is calculated based on bandpass sampling from Section 1.2. The filter responses of this filter is shown in Figure Similar subband filters for second, third, fourth and fifth DRFM channel are listed in Table 2.11a, Table 2.11b, Table 2.11c, and Table 2.11d respectively with corresponding sampling frequencies used to store the filtered signal during detection. These sampling frequencies ensures quadrature down-conversion (I and Q components with single clock) and prevent flipping of the original signal spectrum. Also, the upper bound on sampling frequency is decided keeping in mind the compatibility with the time interleaved ADC. 45

70 Table 2.11: Sub-band filter parameters for wideband EA channel filters No (a) Second wideband EA channel f L (GHz) f H (GHz) BW (MHz) f S (GHz) (c) Fourth wideband EA channel No f L (GHz) f H (GHz) BW (MHz) f S (GHz) No (b) Third wideband EA channel f L (GHz) f H (GHz) BW (MHz) f S (GHz) (d) Fifth wideband EA channel No f L (GHz) f H (GHz) BW (MHz) f S (GHz) Table 2.12: Input signal parameters for wideband EA test case EA Channel No Type of radar signal Up-chirp signal Up-chirp signal Up-chirp signal Up-chirp signal Up-chirp signal Input signal power -60 dbm -60 dbm -60 dbm -60 dbm -60 dbm Input SNR 20 db 20 db 20 db 20 db 20 db Carrier frequency 2.75 GHz 8.2 GHz 13.2 GHz 13.2 GHz 17.2 GHz Instantaneous bandwidth 300 MHz 300MHz 300 MHz 300 MHz 300 MHz Pulse width 100 ns 100 ns 100 ns 100 ns 100 ns Pulse repetition interval 500 ns 500 ns 500 ns 500 ns 500 ns Co-simulation results for all five EA channels working together The co-simulation setup used for performance analysis of the wideband EA system is same as shown in Section 2.3. Here, the input signal applied to all the EA channels is given by Table The estimated power spectral density for all five EA channels is as shown in Figure It is observed that the signal detected in third filter of the first and second EA channel, sixth filter of third channel and first filter of Fourth DRFM channel and Second filter of fifth EA channel as evident from Table 2.10, Table 2.11a, Table 2.11b, Table 2.11c and Table 2.11d. Also the Input and output for each of the EA channels are shown in Figure As it is seen in Figure 2.15, 46

71 PSD Estimates (dbw/hz) GHz First Channel GHz GHz Second Channel GHz Third Channel GHz Fourth Channel GHz GHz Fifth Channel GHz GHz Frequency (GHz) Figure 2.15: Estimated power spectral density for all five EA channels EA System Input (400mV) EA Channel 1 Output (20mV) EA Channel 2 Output (50mV) EA Channel 3 Output (200mV) EA Channel 4 Output (200mV) EA Channel 5 Output (200mV) Time ( s) Figure 2.16: EA system input and output signal for all five EA channels the signal is overlapping between third and fourth channel, and hence is detected by both the channels. Both the channels process the signals and corresponding transmitted output is seen in Figure

72 2.5 Conclusions In this chapter, a standalone EA system based on DRFM repeater was presented without a separate IFM receiver. The receiver frontend comprised of programmable analog bandpass filters and discrete time sampling down-conversion filter performing detection of pulse radar signals without prior knowledge of signal parameters. Digital control and transmitter architecture were presented to re-transmit the stored radar pulses after processing. The target system implemented using Verilog-AMS and Simulink models was validated to handle the test pulse radar signals. Capability of classification of incoming pulse radar signals and flexible system gain profile was demonstrated with performance results. The target system covered 1 GHz to 20 GHz carrier frequency with 300 MHz instantaneous bandwidth and dynamic range from 60 dbm to 20 dbm at input signal-to-noise ratio of 20 db. The minimum delay of 13 PRI was achieved with flexible system gain profile from 30 db to 60 db. This architecture served as a step forward towards a single chip silicon implementation of a ECM system with RF front end and digital control combined as a single unit. 48

73 Chapter 3 Mini-SDR Based Dynamically Reconfigurable Multistandard Subsampling Receiver This chapter proposes the dynamically reconfigurable subsampling multistandard receiver architecture based on the principle of mini-sdr [31, 32, 60]. First the introduction and motivation for the proposed architecture is presented in Section 3.1. The proposed architecture is explained first with the state machine in Section 3.2. This is followed by the system level optimization and performance analysis for the three target standards i.e. GSM, UMTS and WLAN presented in Section 3.3. Then the co-simulation setup along with the performance results are presented in Section 3.4. The system is further optimized for bandwidth detection accuracy and verified with modulated signals as presented in Section 3.5 and the chapter is concluded in Section Introduction For many years now, software defined radio (SDR) or digitally reconfigurable radio research has been quite challenging with only a few reported practical prototypes with limited success [2]. The basic demand of the SDR has been the need for a giant ADC and a powerful enough DSP so that it serves as a universal radio platform receiving almost all radio standards and services. These demands are difficult to meet even in modern CMOS technologies. The architecture in [27] does not include the front-end LNA and employs the IF filtering to receive two or more standards simultaneously. The architecture proposed in [28], employs two sampling paths with tunable RF filter and signal processing algorithm to alleviate the effect of jitter and sampling frequency variations. This implementation lacks the effect of the complete 49

74 RF front-end as the LNA is not included. None of the above implementations provides the capability to sense the standard of the incoming RF signal on their own. The implementation in [30] employs a tunable RF filter along with sub-sampling receiver and ADC to identify the free spectrum for cognitive radio and can receive two or more standards simultaneously. This implementation does not include an LNA and the capability to dynamically identify and change the band used for reception. Also, these architectures focus primarily on the optimization of the sampling frequency for the system level performance and rely on a reconfigurable filter or focus on the baseband system optimization. But, none of the earlier implementations provides the capability to dynamically detect the standard and estimate the signal bandwidth using the incoming RF signal. Therefore, the path to universal radio implementation is challenging and the realization is far from what is available today. However, as an intermediate goal, this research targets a reconfigurable radio architecture which can receive three or four bands from different standards [61 63]. This demands a new generation of receiver architectures and RF front-end circuits with digitally assisted RF techniques [14]. The most promising solution to achieve this intermediate goal is by realizing receivers wherein the signals are processed in the discrete-time domain. As it is widely accepted, in deep sub-micron CMOS, time-domain resolution of a digital signal edge-transition is superior to voltage resolution of analog signals [10]. This approach provides additional flexibility in signal processing and brings the ADC close to the antenna which is the intermediate objective of realizing a SDR. The standard communication receiver relies on the MAC layer protocols to identify the carrier frequency and channel number utilized for communication with the base station. For example, in IEEE , the base station transmits beacon frames on the communication channel at rate of pre-defined beacon interval time to announce the availability of the access point (AP). The network interface card (NIC) in the radio receiver scans each of the wifi channels for such beacon frame which contains the information about the AP such as Service Set Identifier (SSID), configuration parameters, MAC ID of the transmitter. Once a beacon frame is received, the radio receiver can chose to connect to the available AP and start receiving the communication data packets. Hence, before actual data communication between the transmitter and the receiver, the channel, signal bandwidth and center frequency of the communication is known to both the transmitter and the receiver systems [63]. 50

75 In this work, additional possibility to identify if the incoming signal belongs to one of the standard bands dynamically in the physical layer is presented. Traditionally this is done in MAC layer through management frames. A reconfigurable multi-standard sub-sampling receiver with dynamic carrier frequency detection and system level EVM optimizations is proposed. The proposed receiver employs subsampling down-conversion along with subband filters to dynamically detect the carrier frequency of the incoming signal, estimate its bandwidth and identify if the signal is present in one of the target standard bands. This approach makes it feasible to move channel selection filtering and dynamic gain adaptability from analog to digital domain. Also, this carrier detection provides a unique capability to reconfigure the receiver dynamically. Additionally, in this work, system level EVM optimization is proposed considering frequency synthesizer phase noise, IQ mismatch, sampling frequency selection and block-level gain, noise, and non-linearity. The rest of the chapter is dedicated to present the proposed architecture and its performance results. 3.2 Proposed Receiver Architecture The block diagram for the proposed reconfigurable multistandard subsampling radio receiver is presented in Figure 3.1 with the proposed receiver system specifications in Table 3.1. The proposed receiver architecture includes a subsampling receiver RF frontend followed by a RF RF Filter LNA RF Frontend (Verilog-AMS) RF Switch GSM UMTS WLAN RF Switch Subsampling Mixer IF I fs S IF Q Clock Path DLL Discrete Time Filter ADC Digital Signal Processing (Matlab/ Simulink) Figure 3.1: Proposed multistandard receiver architecture for GSM, UMTS and WLAN standards baseband DSP with frequency control. The RF frontend utilizes a wideband RF filter along 51

76 Table 3.1: Proposed multistandard receiver specifications Target Standard GSM UMTS WLAN (802.11g) RF band (MHz) RF bandwidth (MHz) Channel bandwidth 200 khz 5 MHz 22 MHz Sensitivity (dbm) Maximum input signal (dbm) Input dynamic range (db) with a wideband, tunable frequency, tunable gain LNA to provide suitable selectivity for each standard. The subsampling RF frontend for the receiver is modelled in behavioural Verilog - AMS and the DSP part is implemented in Simulink - Matlab. The complete system level co-simulation is performed including the RF frontend and digital baseband signal processing with the test signals listed in Table 3.2. The architecture employs a BPF for each of the targeted standards Table 3.2: Test signal specifications for validation of multistandard receiver Signal Carrier Frequency (MHz) Test Signal Standard GSM UMTS WLAN (802.11g) Signal bandwidth 200 khz 5 MHz 22 MHz Signal input power (dbm) and RF switches to estimate the carrier frequency and signal standard from the incoming RF signal. These subband filters are utilized only during detection and are bypassed during normal receiver operation. Optimized sampling frequency as per Section 1.2 is generated using a DLL block which is controlled by the DSP block. The down-converted signal is bandpass filtered by the discrete-time filter and digitized by the ADC. The proposed receiver utilizes a state machine implemented in Simulink and the signal processing is carried out in Matlab. The state machine for dynamic detection of the incoming RF signal standard and signal acquisition is presented in Figure

77 Acquire GSM Signal GSM Subband Filter Acquire UMTS Signal UMTS Subband Filter Acquire WLAN Signal Receiver Idle No Standard Detected WLAN Subband Filter Detect Again/ Reset Acquisition of Detected Signal Bypass all sub-band filters Detection of Standard Initiate Detection Algorithm Figure 3.2: State machine explaining the detection and acquisition algorithm for the proposed multistandard receiver Dynamic Detection Phase In the dynamic detection phase, each bandpass filter (GSM, UMTS, WLAN in Figure 3.1) represents a targeted standard and is selected sequentially for a predefined interval (500 ns for each of the subband filters) as shown in Figure 3.2. For the activated filter, the corresponding pre-defined sampling frequency is selected in the DLL as listed in Table 3.3. Based on the bandpass sampling analysis explained in Section 1.2, a sampling frequency less than 2 GHz is chosen to facilitate the baseband signal processing. A look-up table is utilized in the DSP to generate these pre-defined sampling frequencies. The filtered signal is down-converted and then digitized using the ADC. After the RF signal is received with the three filters, the detection routine is initiated to estimate the band edges, center frequency and signal bandwidth based on the stored samples. These signal parameters are utilized to calculate the sampling frequency to be used in the acquisition phase to receive the detected standard. The main objective of the proposed architecture is to identify the standard in which the incoming RF signal is present. This is achieved after the dynamic detection phase is complete. A non-parametric PSD estimation technique (Welch method) utilizing windowed Fourier transform with averaging is used (in Matlab) to estimate the carrier frequency and signal bandwidth from the digital samples during detection phase in Figure 3.2. A threshold based on the noise variance is employed on the PSD of the stored samples for each bandpass filters [26]. 53

78 Table 3.3: Specification for the subband filters utilized for detection Subband Filter GSM UMTS WLAN Center frequency (MHz) Filter bandwidth (MHz) k value in Equation (1.2) f s for detection (MHz) Oversampling ratio IF for detection (MHz) As a rule of thumb, the outer edges of the scattered spectrum extend up to 3 σ. It leads to the fact that the upper edge of the noise spectrum is always at 6 db above the mean power. This (mean of PSD + 6 db) is chosen as the detection threshold for estimating the band edge frequencies and signal bandwidth. For example, for GSM test case, only the first subband filter detects the RF signal. The detected signal PSD for the first subband filter is as shown in Figure 3.3a along with the detection threshold and the estimated band edges. In this way, once the communication standard is identified with all signal parameters, the further receiver operation can be continued for the selected standard. Detected signal PSD (dbw/hz) MHz BW= 23.3 MHz MHz First filter TH1 = dbw/ ,000 Acquired signal PSD (dbw/hz) IF = 187 MHz Frequency (MHz) Frequency (MHz) (a) First filter detected signal PSD for GSM test signal (b) Down-converted GSM signal PSD with IF of 187 MHz Figure 3.3: Detection and acquisition co-simulation results for GSM test signal of the multistandard SDR receiver 54

79 3.2.2 Signal Acquisition Phase After the successful detection of the RF signal, the acquisition phase is initiated as shown in Figure 3.2. In this phase, the subband filters are bypassed and the sampling frequency calculated at the end of the detection phase is utilized to down-convert the signal in the subsampling mixer. The down-converted signal is stored and further processed in the DSP block for calculating the PSD. For example, for the GSM test case, the carrier frequency of MHz is calculated based on the band edges detected in Figure 3.3a. With k=3 in Equation (1.2) this leads to sampling frequency of 754 MHz. During the signal acquisition phase, all the subband filters are bypassed and this sampling frequency is used to acquire the signal shown in Figure 3.3b at the IF of 187 MHz. 3.3 System Level Optimization In this section, the system level analysis and simulation results for the multistandard subsampling receiver are presented corresponding to each of the selected standards Sampling Frequency Optimization During detection state, the sampling frequency for each standard is optimized based on the RF bandwidth of the corresponding standard, the center frequency of the RF band and the oversampling ratio. For example, for the GSM band, the center frequency and RF bandwidth are MHz and 35 MHz respectively. Thus, based on the sampling frequency Equation (1.2) with k =3 we get the sampling frequency for the detection of GSM standard as 754 MHz. This corresponds to the IF frequency of MHz and first image at MHz. This image is suppressed by the BPF after the sampling and the IF signal is converted to digital domain by utilizing the ADC Figure 3.1. Similarly, sampling frequencies utilized for UMTS and WLAN standard detection are presented in Table 3.3. Once the detection is complete based on one or more available standards, the standard of interest and channel in the chosen standard is determined. As the channel bandwidth is much smaller as compared to RF bandwidth, after detection phase, the oversampling ratio with respect to signal bandwidth is much higher. This results in better noise performance. For example, for GSM standard, if we select the center frequency of the selected channel as 55

80 930 MHz, with channel bandwidth 200 khz, the sampling frequency of 744 MHz with k = 3 in Equation (1.2) results in an oversampling ratio of System-Level EVM Performance of Multistandard Receiver The system level performance for the multistandard subsampling receiver for each standard is evaluated based on the EVM in this section. The receiver analog frontend is optimized for each of the targeted standards and the block level performance is presented in Table 3.4. The effect of receiver impairments on the EVM performance is studies in the rest of the section. Table 3.4: Individual block-level specifications for the multistandard receiver frontend Specification RF Filter LNA RF Bandwidth (MHz) Sub-band Filter Sampling Mixer IFA Buffer Based on Standard a Gain (db) Noise Figure (db) b Linearity (dbm) a depends on the selected standard and sampling frequency, details in Table Sampling Frequency As explained in Section 1.2 and Section 3.3.1, the sampling frequency selection contributes to the overall noise figure of the receiver. This effect is seen in Figure 3.4 for all the three targeted standards. For this calculation, very low phase noise of the DLL is assumed so as not to limit the system performance by the DLL jitter Clock Jitter The effect of the sampling clock jitter is modelled as SNR limitation the output of the subsampling mixer. The maximum signal to noise ratio for the subsampling mixer with the 56

81 EVM degradation (db) EVM for GSM at 35 dbm input power EVM for UMTS at 35 dbm input power EVM for WLAN at 35 dbm input power Sampling frequency (GHz) Figure 3.4: Receiver EVM degradation vs sampling frequency jitter of the clock signal is given by Equation (3.1) [64, 65]. SNR mix,jitter = 20 log (2πf c τ j ) ( = 20 log 2πf c τ ) φ,rad 2πf s ( fc = 20 log τ ) φ,deg π f s 180 (3.1) Here, f c and f s are center frequency of the RF signal and the sampling frequency respectively. τ j is the total RMS jitter for the frequency synthesizer. τ φ,rad and τ φ,deg are the total integrated phase noise in radians and degrees respectively for the frequency synthesizer. The RMS phase noise from 0.1 to 1 is assumed and the overall system level EVM is plotted in Figure EVM at 40 dbm input power EVM degradation (db) ,000 Total RMS jitter (fs) Figure 3.5: Receiver EVM degradation vs frequency synthesizer RMS jitter 57

82 Block-level Performance and Receiver EVM The effect of individual block-level performance on the overall receiver EVM is presented for the WLAN standard in Figure 3.6. Here, the phase noise of and IQ mismatch of 50 dbc is assumed so as not to affect the overall receiver EVM performance. Block level EVM (db) LNA STDFILTER MIXER PN IQ IFA Buffer ADC RX EVM standard 32 db RF input power (dbm) Figure 3.6: Block level EVM for the multistandard receiver for WLAN detection Based on the block-level performance, the overall receiver EVM versus input RF power is shown in Figure 3.7. Here, tree LNA gain steps are shown in the dotted line and the best case receiver performance is shown in the solid line. The EVM versus RF input power curve for the 10 Receiver Ultimate EVM Receiver ultimate EVM (db) limited by noise standard 32 db limited by linearity RF input power (dbm) Figure 3.7: Ultimate EVM simulation for multistandard receiver WLAN detection 58

83 receiver shown in Figure 3.7 is the bath tube curve with hyperbolic nature. It can be readily seen from Figure 3.7 that at low input power levels, receiver EVM is limited by the system noise and at the high RF power levels, linearity limits the receiver EVM. As the RF input power increases from the minimum value, the SNR available at the input of the receiver increases resulting in an improvement in the EVM. Afterwards, the EVM saturated at the maximum EVM value called ultimate EVM and a flat curve with ultimate EVM performance is observed from -35 dbm to -20 dbm in Figure 3.7. Detected signal PSD (dbw/hz) GHz GHz Second filter TH2 = dbw/ 140 BW= 28 MHz Frequency (GHz) Acquired signal PSD (dbw/hz) IF = MHz Frequency (MHz) (a) Second filter detected signal PSD for UMTS test signal (b) Down-converted UMTS signal PSD with IF of MHz Figure 3.8: Detection and acquisition co-simulation results for UMTS test signal of the multistandard SDR receiver 3.4 Performance Results and Discussion The co-simulation set-up used for the simulation of the proposed architecture is presented in Figure 3.9. The RF frontend is simulated using Spectre and the control state machine and DSP are simulated in Simulink and Matlab respectively. The set-up consists of three control signals from Simulink to Spectre which include RF input signal, RF switch control and DLL frequency control. The output from Spectre to Simulink represents the ADC output. Three test cases are utilized to investigate the performance of the proposed multistandard radio architecture. The performance results for the co-simulation are summarized in Table 3.5. For the first test case, a MHz carrier GSM signal with 200 khz bandwidth is applied to the receiver. The PSD for the signal processed by the first subband filter is shown in Figure 3.3a 59

84 RF Input Verilog-AMS Multistandard Receiver ADC Output / Control Signals Simulink-Matlab Control, Detection and Signal Processing Figure 3.9: Simulation set-up for performance evaluation of the proposed multistandard receiver architecture Detected signal PSD (dbw/hz) GHz BW= 25 MHz GHz Third filter TH3 = dbw/hz Acquired signal PSD (dbw/hz) IF = 478 MHz Frequency (GHz) Frequency (MHz) (a) Third filter detected signal PSD for WLAN test signal (b) Down-converted WLAN signal PSD with IF of 478 MHz Figure 3.10: Detection and acquisition co-simulation results for WLAN test signal of the multistandard SDR receiver along with the threshold of TH1 = dbw/hz used for the detection of signal edges. The estimated center frequency from the edges is MHz against the input signal frequency of Table 3.5: Performance summary for the proposed multistandard SDR receiver Test case GSM UMTS WLAN Input power (dbm) Carrier frequency MHz 2.14 GHz GHz Input signal bandwidth 200 khz 5 MHz 22 MHz f s Equation (1.2) 754 MHz GHz GHz f IF (MHz) Equation (1.3) Detection threshold (dbw/hz) Estimated lower edge frequency MHz GHz GHz Estimated higher edge frequency MHz GHz GHz Estimated center frequency MHz 2.14 GHz GHz Estimated bandwidth (MHz) Detected IF frequency (MHz)

85 942.5 MHz. The estimated signal bandwidth (23.32 MHz) is very high as compared to 200 khz channel bandwidth for GSM signal. However, here the main objective is to identify the standard in which a carrier is present and to estimate the center frequency of the channel. The PSD of the stored signal after detection in Figure 3.3b shows the IF of 187 MHz against MHz expected value in Table 3.5. For the second test case, 2.14 GHz carrier frequency, 5 MHz UMTS signal is applied to the receiver. The PSD for the signal processed by the second subband filter in Figure 3.8a shows a detected carrier of 2.14 GHz with a detection threshold of TH2 = dbw/hz. The detection estimated bandwidth of 28 MHz against the channel bandwidth of 5 MHz for UMTS signal. The PSD in Figure 3.8b shows the detected IF of MHz against an expected value of 428 MHz. For the third test case, the GHz carrier, 22 MHz signal bandwidth WLAN signal is applied to the proposed receiver. The PSD for the signal processed by the third subband filter Figure 3.10a shows GHz with a detection threshold of TH3 = dbw/hz. The detection estimated bandwidth of 25 MHz against the channel bandwidth of 22 MHz for WLAN signal. The PSD shows the detected IF of 478 MHz in Figure 3.10b against an expected value of MHz. The performance of the proposed architecture is compared with the previous sampling receiver implementations in Table 3.6. The previous implementations do not consider the complete frontend or do not include the capability to identify the incoming RF signal standard dynamically and lack the details of signal processing. The subsampling receiver is proposed for a system-on-chip implementation with integrated baseband digital control. 3.5 Improved Performance and Verification In this section, the performance results after further optimization of the proposed DRMS system are presented. Here, the detection algorithm is optimized to increase the accuracy of the bandwidth detection in the proposed system. Further, the system is validated with the 4-QAM modulated signals with channel bandwidths as presented in Table

86 Table 3.6: Performance Comparison with the previous sampling receivers Parameter [66] [67] [6] [5] [13] [27] [28] [30] This work Year IJCTA 18 ISCAS 15 JSSC 10 JSSC 05 TWC 09 MTT-S 12 Arch. Homodyne RF Oversampling Sub-sampling Subsampling + tunable IF Filter ISPIMRC 11 RWC 12 Sub-sampling + tunable RF filter Subsampling + Detection Filters RF (GHz) 0.8 to to to to to to to 2.5 Target standard GSM, UMTS, WLAN LTE DBV WLAN GSM, UMTS, WLAN GSM, WCDMA, Bluetooth, WiMAX, WLAN WBAN DBV, Tx Aux, WLAN GSM, UMTS, WLAN fs (GHz) up to a 1.6 to to to 0.42 up to 2 Signal Detection Receiver EVM (db) Not possible Not possible Not possible Not possible Not possible Not possible Not possible Possible Possible NR NR NR NR NR NR 40 Setup CMOS b CMOS b CMOS CMOS ADS Matlab Matlab COTS a equivalent clock frequency b simulated NR Not reported Verilog- AMS and Matlab/ Simulink 62

87 Table 3.7: Improved Performance Summary for The Proposed Multi-standard SDR Receiver Test case GSM UMTS WLAN Input power (dbm) Carrier frequency MHz 2.14 GHz GHz Input signal bandwidth 200 khz 5 MHz 20 MHz Modulation 4-QAM 4-QAM 4-QAM f s Equation (1.2) 754 MHz 951 MHz GHz f IF (MHz) Equation (1.3) Detection threshold (dbw/hz) Estimated lower edge frequency MHz GHz GHz Estimated higher edge frequency MHz GHz GHz Estimated center frequency MHz 2.14 GHz GHz Estimated bandwidth a (MHz) Detected IF frequency (MHz) a The resolution of the estimated bandwidth of the incoming signal is improved in the second architecture Detected signal PSD (dbw/hz) TH2 = TH3 = First filter Second filter Third filter Frequency (MHz) GHz GHz BW= 4 MHz TH1 = Frequency (MHz) Figure 3.11: Detected PSD corresponding to all filters for GSM test signal Similar to previous section, three test cases are utilized to investigate the performance of the proposed multi-standard radio architecture. The performance results for the co-simulation are summarized in Table 3.7. For the first test case, a MHz carrier GSM signal with 200 khz bandwidth is applied to the receiver. The PSD for the signal processed by the first subband filter is shown in Figure 3.11 along with the threshold of TH1 = dbw/hz used for the detection of signal edges. The estimated center frequency from the edges is MHz against the input signal frequency of MHz. The estimated signal bandwidth (4 MHz) is still high as compared to 200 khz channel bandwidth for GSM signal but shows better accuracy compared to result 63

88 from previous section for GSM case of 23 MHz (Table 3.5)The PSD of the stored signal after detection in Figure 3.12 shows the IF of MHz as shown in Table 3.7. Stored signal PSD (dbw/hz) 60 f IF = MHz Frequency (MHz) Figure 3.12: Down-converted GSM signal PSD with IF of MHz Detected signal PSD (dbw/hz) TH1 = TH3 = First filter Second filter Third filter Frequency (MHz) GHz GHz TH2 = BW= 8 MHz Frequency (MHz) Figure 3.13: Detected PSD corresponding to all filters for UMTS test signal For the second test case, 2.14 GHz carrier frequency, 5 MHz UMTS signal is applied to the receiver. The PSD for the signal processed by the second subband filter in Figure 3.13 shows a detected carrier of 2.14 GHz with a detection threshold of TH2 = dbw/hz. The detection estimated bandwidth of 8 MHz against the channel bandwidth of 5 MHz for UMTS signal. The PSD in Figure 3.15a shows the detected IF of MHz against an expected value of MHz. For the third test case, the GHz carrier, 4-QAM modulated signal with 4 sub-carriers along with 20 MHz signal bandwidth WLAN signal is applied to the proposed receiver. The PSD for the signal processed by the third subband filter Figure 3.14 shows GHz with a detection threshold of TH3 = 141 dbw/hz. The detection estimated bandwidth of 20 MHz for WLAN signal. The PSD shows the detected IF of MHz in Figure 3.10b against an expected value of MHz. For the WLAN signal, an 4-QAM modulated signal with 4 sub- 64

89 Detected signal PSD (dbw/hz) 120 TH2 = 131 TH1 = First filter Second filter Third filter Frequency (GHz) GHz BW= 20 MHz GHz TH3 = Frequency (GHz) Figure 3.14: Detected PSD corresponding to all filters for WLAN test signal Stored signal PSD (dbw/hz) f IF = MHz Frequency (MHz) (a) Down-converted UMTS signal PSD with IF of MHz Stored signal PSD (dbw/hz) f IF = MHz Frequency (MHz) (b) Down-converted WLAN signal PSD with IF of MHz Figure 3.15: Down-converted UMTS and WLAN signal PSD carriers and input signal power of -40 dbm is applied, detected, stored, the received signal is down-converted to BB and the constellation for the receiver WLAN stored signal is shown in 1.02 Quadrature 1 1 Ideal constellation points Receiver Output Quadrature In-phase In-phase Figure 3.16: Received Constellation for the Down-converted 4-QAM, 4 sub-carriers, 20 MHz moduated WLAN signal with 40 dbm RF signal power in comparison to ideal 4-QAM constellation 65

90 Figure Here, the RMS EVM of 40 db is simulated for the complete receiver chain based on the demodulated BB data. 3.6 Conclusions In this chapter, the DRMS radio receiver architecture was presented. It was demonstrated by simulation that the proposed architecture is able to detect and process multiple signals from different standards by detecting the signal carrier and estimating its bandwidth. The receiver was tested for GSM, UMTS and WLAN standards with different test cases. Also, the system level optimizations of the overall receiver performance were presented. The proposed receiver performance was verified for carrier frequencies in the range from 0.9 GHz to 2.5 GHz, maximum signal bandwidth of 22 MHz and an input dynamic range from 109 dbm to 20 dbm. In addition, the proposed architecture brought the ADC close to the antenna to achieve the intermediate objective of realizing a universal SDR. 66

91 Chapter 4 Mini-SDR Based Dual-band Subsampling WLAN Receiver In this chapter, an overview of the proposed dual-band subsampling receiver [36, 68] is provided along with underlying principles of the subsampling down-conversion and decimation based filtering. The introduction and motivation for the proposed architecture is presented in Section 4.1. The proposed system architecture, system level optimizations and trade-offs for the subsampling receiver are presented in Section 4.2. Then, the specifications for the proposed subsampling receiver are derived from the IEEE ac standard requirements in Section 4.3. This is followed by the implemented block level circuits and optimizations proposed in Section 4.4 and the chapter is concluded in Section Introduction The challenges in the traditional sampling receiver architectures such as requirement of high frequency clock, phase noise or jitter limited performance and timing mismatches in timeinterleaved paths are alleviated in the sub-sampling receivers [5, 8, 35]. This leads to the lesscomplex and less power hungry frequency synthesizers due to sub-nyquist sampling frequency. The CMOS sub-sampling mixer in [5] demonstrates the performance only at a single-carrier frequency with 20 MHz bandwidth and does not include a front-end LNA. The sub-sampling RF front-end reported in [8] works at a very low sampling frequency clock of 100 MHz to downconvert 2.4 GHz RF signal. This front-end is severely disadvantaged with a high noise figure of 21 db due to noise folding effect and also lacks the I and Q signal component separation at the baseband. Recent sub-sampling receiver implementation [35] employs a high-q tuned front-end LNA followed by a sub-sampling mixer with a sampling frequency of MHz for 67

92 2.4 GHz RF signal and baseband processing. The receiver is targeted for wireless body area network (WBAN) application with 1 MHz signal bandwidth and relies on the selectivity of front-end for noise performance, hence not scalable for larger bandwidths. The previously reported architectures do not include the complete receiver chain [8, 35], utilize oversampling for down-conversion [6, 7, 69 71] or focus on a narrow band application [35]. Also, none of the reported architectures present the ultimate EVM performance for the complete receiver chain with sampling frequency optimization and continuous tuning of gain and frequency. In conclusion, the optimization of sampling frequency has multiple advantages: a) the noise folding effect is reduced leading to smaller noise figures. b) less-complex and less-power hungry clocking scheme. c) quadrature phase readily available between consecutive samples is utilized to separate samples into I and Q paths. d) the ultimate EVM performance of the receiver is significantly better than the subsampling receivers, where the sampling frequency is not optimized. Next in this chapter, the dual-band subsampling WLAN receiver architecture is proposed. 4.2 System Architecture, Analysis and Design The proposed dual-band subsampling receiver architecture is shown in Figure 4.1. The 2.4 GHz and 5 GHz receiver chains process the corresponding WLAN bands simultaneously. An optimized continuously tunable-gain and tunable-band active balun LNA is employed in both the receiver chains. The output of the LNA and the rest of the receiver chain is implemented differentially but Figure 4.1 shows single-ended architecture for simplicity. The subsampling mixer down-converts the RF signal to first IF in the range from 445 MHz to 540 MHz. An integrated dual-function switched capacitor finite impulse response (FIR) bandpass filter for band selection and down-conversion to baseband is employed after the intermediate frequency amplifier (IFA). The decimation filter is a 23-tap FIR bandpass filter. The subsampling mixer and decimation filter utilize an off-chip clock signal fed through clock buffers as shown in Figure 4.1. A clock divider is employed to generate 24 non-overlapping, time-interleaved phases for the decimation filter operation. The I and Q samples are separated in the FIR filter based on the clock phases generated from the divider. A baseband ampli- 68

93 2.4 GHz LNA Subsampling IFA 2.4 GHz RX Decimation Filter RF 2g,in GHz f s GHz LNA out Clk Buffer f s,2g GHz Mixer T/H f s,mixer Mix out Clk Buffer f s,filter 2.4 GHz Receiver Chain 5 GHz Receiver Chain IF out clk 1 clk 2 clk 4 M LO Divide by 24 clk 3 clk 23 clk 24 M M firi out firq out firi out Measurement Buffers BBI 2g,out BBQ 2g,out BBI 5g,out f s,5g GHz Clk Buffer f s,mixer Clk Buffer f s,filter clk 1 clk 2 clk 4 LO Divide by 24 clk 3 clk 23 clk 24 Measurement Buffers RF 5g,in GHz 5 GHz LNA LNA out Mixer T/H Subsampling Mix out IFA IF out M 5 GHz RX Decimation Filter firq out BBQ 5g,out Figure 4.1: Block diagram of the proposed dual-band subsampling receiver for 2.4 GHz and 5 GHz WLAN bands fier (BBA) provides a gain of 12 db after down-conversion. Measurement buffers with 2.5 V supply voltages are used to measure the differential I and Q signals at the output Noise Folding in subsampling Down-conversion Sampling frequency selection is one of the key optimization factors for sampling receiver architectures. The rest of the section is devoted to the analysis of thermal noise, noise folding effect, signal-to-noise ratio (SNR) and sampling frequency optimization. The subsampling down-conversion mainly suffers from the noise folding effect [4] where due to the lower sampling frequency, the out-of-band noise gets down-converted to desired IF band. Another issue is the jitter of the clock affecting the SNR of the down-converted signal. However, the primary advantage of the subsampling principle is the lower LO frequency or sampling frequency needed to down-convert the signal as compared to direct down-conversion or super-heterodyne receiver architecture. The low LO frequency in turn simplifies the frequency synthesizer design implementation effort and results in less power hungry synthesizers. The thermal noise folding effect reduces the SNR of the sampled signal as the out-of-band noise is shifted to desired IF 69

94 band. The output SNR for the sampled signal is given in Equation (4.1) [13]. Here, N o in Equation (4.2) represents the noise power in the out of signal band frequencies and is assumed to be dominated by the thermal noise of the receiver in absence of any blocker signals. Also, B eff is the effective noise bandwidth (equal to carrier frequency), N i is the in-band noise level, N o is the out-of-band noise power level (Noise floor), P S is the output signal power. SNR out = [ ] P S 2 Beff and m = N i + (m 1) N o f S (4.1) N o = NF + 10log (BW RF ) (4.2) For example, for the input signal power level of 36 dbm at 5.61 GHz and 256-QAM modulation with 80 MHz signal bandwidth results in 70 dbm thermal noise floor at the input of LNA (Equation (4.2)) and 5 db NF. Moreover, assuming absence of any out-of-band blocker, the out of band noise level is also equal to N o. The sampling mixer employed in this work is a track and hold circuit with hold capacitor value of C H. There are two dominating components contributing to the noise folding. First one is the in-band thermal noise from the previous stages at the input of the subsampling mixer given as Equation (4.3). The second one is the KT C mixer given by Equation (4.4) for 50 Ω system [5]. noise at the output of the subsampling P T h,mixin = N o + Gain LNA NF LNA (4.3) P KT C ( = 10 log β 2 ) 2kT BW ch f s C H ( ) (4.4) The effect of sampling frequency selection on KT C noise power is shown in Figure 4.2 along with thermal noise level at the input of LNA and at the input of subsampling mixer. sampling frequency has to be selected in such a way so that the thermal noise is the dominant noise to be considered for in-band noise folding effect and not the KT C The noise. This ensures the thermal noise being the in-band noise for noise folding effect. By comparing the Equations (4.3) ( ) and (4.4), it can be concluded that the design variable fsch BW ch 0.2 pf is required to satisfy 70

95 Noise power (dbm) noise floor at LNA input KT C noise power thermal noise at mixer input Sampling frequency (GHz) Figure 4.2: Noise power levels at the output of the subsampling mixer this condition. This lead to the sampling frequency, f s 1.6 GHz and the hold capacitor value C H 10 ff. The effect of noise folding on the output SNR is shown in Figure 4.3 as degradation. It is observed that by proper selection of sampling frequency, the effect of noise folding can be alleviated. SNR degradation (db) 10 5 KT C noise dominating thermal noise dominating Sampling frequency (GHz) Figure 4.3: SNR degradation due to noise folding effect in the subsampling mixer Decimation Down-conversion Filtering The proposed subsampling receiver employs switched capacitor based FIR decimation filter to down-convert the IF signal to the baseband. Discrete-time signal processing provides additional flexibility as the filter is always tuned to the IF which in turn depends on the sampling 71

96 frequency. As the sampling frequency is tuned to receive a particular carrier frequency, the IF changes as per Equation (1.3). The decimation filter is also running at the same sampling frequency, the transfer function aligns itself to filter the alias components from the IF. The decimation ratio is one of the important parameters in the design of the SC filter. Due to down-sampling in decimation, alias frequency components, (f alias as given in Equation (4.5)) are down-converted to baseband if not filtered. Filter transfer function (db) GHz filter 31 db BW= 121 MHz 31 db Frequency (MHz) Figure 4.4: 2.4 GHz decimation filter transfer function f alias = f IF ± n fs M Here, M represents the decimation ratio of the FIR filter and n can be an integer. (4.5) Higher decimation ratio dictates lower output sampling rate leading to easier signal processing in the baseband. This leads to the stringent filtering requirements in a single step as the alias components given by Equation (4.5). Hence, some of the previous implementations utilize step-by-step decimation and filtering [10]. The baseband center frequency after down-sampling is given by Equation (4.6) where p is an integer. Thus, the decimation ratio of 12 is chosen resulting in zero baseband (BB) frequency with 23 tap FIR filter transfer function. ( f BB = min f IF p fs ) M (4.6) The filter transfer functions implemented for 2.4 GHz and 5 GHz decimation filters are given in Equation (4.7) and Equation (4.8) respectively. 72

97 Filter transfer function (db) GHz filter 20 db BW= 134 MHz 20 db Frequency (MHz) Figure 4.5: 5 GHz decimation filter transfer function H 2G (z) = [ z 1 + 4z 3 9z z 7 18z z 11 18z z 15 9z z 19 z 21 ] (4.7) H 5G (z) = [ z 1 + 3z 3 8z z 7 23z z 11 23z z 15 8z z 19 z 21 ] (4.8) The filter response for 2.4 GHz and 5 GHz decimation filters in Matlab are shown in Figure 4.4 and Figure 4.5 respectively. The center frequency, filter bandwidth and the alias frequencies are also mentioned for both the filters. The alias frequency for the 2.4 GHz filter is attenuated by 31 db whereas the alias frequency in the 5 GHz filter is attenuated by 20 db. The decimation filter is implemented using SC circuit with charge sharing technique [72] as shown in Figure 4.6. Here, the filter coefficients are realized by the capacitor ratio of sampling capacitors (C pi or C ni ) to the total capacitor given by Equation (4.9). C total = ΣC ni + ΣC pi (4.9) The samples in decimation filter are routed using 24 clock phases. Here, the sampling phases Clk 2, Clk 4 and so on are used to sample the signal in corresponding sampling capacitors C pi 73

98 SC core Clk 2 IF out Clk 4 Clk out =Clk 24 C n1 C p1 S1 out - Clk 20 Clk 22 S1 out + C Ln C n6 C p5 C Lp Figure 4.6: SC core for the decimation filter and C ni and the output clock Clk 24 is utilized to average the charge on to the load capacitors C Lp and C Ln. The filter transfer function is half band FIR implementation resulting only 11 non-zero coefficients. As the output sample is available on the Clk out phase, the SC core has a decimation ratio of 24. Hence, two SC cores are operated in time-interleaved arrangement to achieve decimation ratio of 12. In total 8 such SC cores are employed for the complete decimation filter in both the 2.4 GHz and 5 GHz receiver chains System-Level EVM Analysis In this section, the effect of system-level optimizations and the individual block level performance on the receiver ultimate EVM are presented with a Matlab system model. Performance parameters for each of the sub-blocks considered for the system level model are listed in Table 4.1. The rest of the section is dedicated to the analysis of important parameters that affect the system level EVM performance. These are back annotated from Spectre simulations to Table 4.1: Block-level specifications for the receiver model Gain (db) Noise Figure (db) IIP 3 (dbm) Low Noise Amplifier Subsampling Mixer IF Amplifier SC Filter Baseband Amplifier Baseband Source Follower Overall RX

99 match the receiver performance. The proposed subsampling receiver is analysed for architecture impairments and to optimize the system performance Sampling Frequency Sampling frequency selection and noise folding from Section and the decimation filter noise figure from Section affect the receiver EVM as shown in Figure 4.7. Here, the EVM degradation (db) EVM at 40 dbm input power Sampling frequency (GHz) Figure 4.7: Receiver EVM degradation vs sampling frequency sampling frequency is varied as per Equation (1.2) and the EVM at 40 dbm input RF power is seen along with the minimum achieved receiver EVM. Lower sampling frequency results in higher noise folding leading to an increase in the subsampling mixer noise figure. At the input power of 40 dbm, the EVM is limited by the noise of the receiver chain and hence the effect of sampling frequency is clearly visible. The EVM degrades by less than 2.7 db for sampling frequency variation from 2 GHz to 1 GHz Unit Capacitor for Decimation Filter The unit capacitor used for the implementation of the switched capacitor filter contributes to the overall noise figure of the filter [5] and thus, in turn, affect the overall receiver EVM. This effect is presented in Figure 4.8. As the unit capacitor increases the overall effective capacitor in the filter increases reducing the KT/C noise contribution. Hence, the receiver EVM improves by 2 db for an increase from 20 ff to 40 ff in decimation filter unit capacitor. The decimation 75

100 filter uses 34 ff as the unit capacitor for implementation based on the layout, area optimizations and the circuit level simulations. EVM degradation (db) 0 5 EVM at 40 dbm input power Unit capacitor (ff) Figure 4.8: Receiver EVM degradation vs decimation filter unit capacitor Phase Noise or Jitter The effect of frequency synthesizer phase noise is modeled as the SNR limitation at the output of the subsampling mixer. The maximum signal to noise ratio for the subsampling mixer with the jitter of the clock signal is given by Equation (4.10) [64, 65]. SNR mix,jitter = 20 log (2πf c τ j ) ( = 20 log 2πf c τ ) φ,rad 2πf s ( fc = 20 log τ ) φ,deg π f s 180 (4.10) Here, f c and f s are center frequency of the RF signal and the sampling frequency respectively. τ j is the total RMS jitter for the frequency synthesizer. τ φ,rad and τ φ,deg are the total integrated phase noise in radians and degrees respectively for the frequency synthesizer. The effect of clock signal phase noise on the overall receiver EVM is presented in Figure 4.9. Here, the total RMS jitter is varied from 50 fs to 1.2 ps and the degradation in the receiver EVM is plotted. As the total integrated phase noise for the clock signal increases, the receiver EVM is limited by the frequency synthesizer jitter performance as per Equation (4.10). Hence, the receiver EVM degrades by 12 db per decade variation from 50 fs to 1 ps. 76

101 EVM degradation (db) 0 EVM at 40 dbm input power ,000 Total RMS jitter (fs) Figure 4.9: Receiver EVM degradation vs frequency synthesizer RMS jitter Subsampling phase locked loop (PLL) in [73] presents a 2.4 GHz output frequency with RMS jitter of 154 fs in 130-nm technology. The subsampling PLL in [74] 65-nm technology has RMS jitter of 448 fs at the 2.2 GHz output frequency. In this implementation sampling from 1.7 GHz to 2.1 GHz is employed for both the WLAN bands. For example, with f c of 5.32 GHz, based on Equation (3.1), the sampling frequency of GHz is calculated. For this sampling frequency, the total integrated phase noise of 0.14 and 0.33 is included in the model which corresponds to RMS jitter 200 fs and 448 fs respectively. This results in ultimate receiver EVM from 37.5 db and 35 db for 200 fs and 448 fs RMS jitter respectively IQ Gain and Phase Mismatch The effect of gain and phase mismatch in I and Q receiver paths on the overall receiver EVM is modelled as signal to distortion ratio (SDR IQ ) in Equation (4.11) [75]. ( M 2 g + tan 2 ) (M ph ) SDR IQ = 10 log Mg 2 tan 2 (M ph ) (4.11) Here, M g and M ph are the gain and phase mismatch in % and degrees respectively. The IQ mismatch variation for a target EVM is seen in Figure Typically, the receiver architectures employ calibration loops to achieve signal to distortion ratio due to IQ mismatch below 50 dbc [76]. The effect of signal to distortion ratio from IQ mismatch on overall receiver EVM is seen as degradation in Figure To analyse the effect of individual sub-blocks, gain and phase mismatch of 0.3 % and 0.5 is considered for the receiver which results in a signal-to-distortion ratio of 50 dbc from IQ impairment. 77

102 Phase mismatch ( o ) db EVM 30 db EVM 40 db EVM 25 db EVM 35 db EVM Gain mismatch (%) Figure 4.10: System level variation of receiver EVM vs IQ mismatch EVM degradation (db) IQ mismatch (dbc) Figure 4.11: System level variation of receiver EVM vs IQ mismatch Block-level EVM Performance and Receiver Ultimate EVM EVM after each of the building blocks is shown in Figure The overall receiver EVM graph shows hyperbolic shape as explained in Section Here, the contribution of each of the building block towards overall receiver EVM is analysed. It can be observed that for the proposed receiver architecture, the overall EVM is mainly limited by the phase noise (PN) performance of the frequency synthesizer and IQ impairment. Based on the receiver impairments and block level performance, the ultimate EVM for receiver chain is evaluated and the bath tube curve is shown in Figure Here, total RMS jitter of 480 fs and the IQ mismatch of 50 dbc are used. The dotted lines show the receiver EVM for three LNA gain settings whereas 78

103 20 LNA MIXER PN IQ IFA FIR BBA BBSF RX EVM Block level EVM (db) standard 32 db RF input power (dbm) Figure 4.12: Block level EVM for the proposed subsampling receiver 10 Receiver Ultimate EVM Receiver ultimate EVM (db) limited by noise limited by linearity standard 32 db RF input power (dbm) Figure 4.13: Ultimate EVM system level simulation the continuous line shows the ultimate EVM for the receiver. The standard requirement for the receiver EVM is shown in blue as 32 db. 79

104 4.3 System Level Specifications From IEEE ac Standard In this section, the standard receiver specifications are derived from the IEEE ac standard Maximum Receiver Noise Figure The sensitivity of the receiver is given by Equation (4.12). Here, NF receiver is the receiver noise figure, BW CH is the channel bandwidth and SNR min is the minimum SNR required at the output of the receiver for a particular modulation scheme and bandwidth. P sensitivity = 174(dBm) + NF receiver (db) + 10 log(bw ch )(db) + SNR min (db) (4.12) BER Eb N 0 [db] BP SK, R = 1 2 QP SK, R = 1 2 QP SK, R = QAM, R = QAM, R = QAM, R = QAM, R = QAM, R = QAM, R = QAM, R = 5 6 Figure 4.14: BER vs E b N 0 The sensitivity requirement for different modulation schemes and data rates for IEEE ac standard is given by Table 4.2 [63]. Moreover, the maximum packet error rate specified by the standard for sensitivity analysis is 10 %. This translates to bit error rate (BER) of 10 5 for 1000 bits packet. The BER curves with respect to energy per bit to noise power spectral density ratio ( E b N 0 ) for the supported modulation schemes and coding rates are presented in Figure These curves are derived based on theoretical calculations for the supported modulation schemes. For the target BER of 10 5, the required energy per bit to noise power spectral density ratio can be extracted from Figure 4.14 [77]. These E b N 0 values are utilized along with the data rate specification from Table 4.3 to compute the minimum SNR required for the 80

105 Minimum SNR (db) MHz 40 MHz 80 MHz BPSK R = 1 2 QPSK R = 1 2 QPSK R = QAM R = QAM R = QAM R = QAM R = QAM R = QAM R = QAM R = 5 6 Modulation Scheme Figure 4.15: Minimum signal to noise ratio for various modulation schemes for WLAN standard decoding data using Equation (4.13). The minimum SNR for the different standards and data rates is shown in Table 4.4. SNR min = E b Data Rate (4.13) N 0 BW ch Here, BW ch is the channel bandwidth and SNR min is minimum SNR required at the decoder for the modulation scheme and channel bandwidth. Modulation Table 4.2: Sensitivity specification CodingRate Sensitivity (dbm) 20 MHz 40 MHz 80 MHz BPSK 1/ QPSK 1/ QPSK 3/ QAM 1/ QAM 3/ QAM 2/ QAM 3/ QAM 5/ QAM 3/ QAM 5/

106 Modulation Table 4.3: Date rate specification CodingRate Date Rate (Mbps) 20 MHz 40 MHz 80 MHz BPSK 1/ QPSK 1/ QPSK 3/ QAM 1/ QAM 3/ QAM 2/ QAM 3/ QAM 5/ QAM 3/ QAM 5/6 NA Table 4.4: Minimum signal to noise ratio values Modulation DataRate SNR min (db) 20 MHz 40 MHz 80 MHz BPSK 1/ QPSK 1/ QPSK 3/ QAM 1/ QAM 3/ QAM 2/ QAM 3/ QAM 5/ QAM 3/ QAM 5/6 NA The values of SNR min are utilized along with Equation (4.12) and Table 4.2 to obtain maximum allowed noise figure for the modulation scheme and channel bandwidth. Assuming RF bandwidth (BW RF ) equal to channel bandwidth the noise figure for the receiver is shown in Figure 4.16 for sensitivity values from standard. For the further calculations the receiver noise figure of 5 db is assumed Minimum Receiver Linearity (IIP 3 ) The out-of-band third order inter-modulation requirement for the overall system is given by Equation (4.14). IIP 3 = 3 2 P int 1 2 P sig SNR min (4.14) The adjacent and non-adjacent rejection levels for the ac standard are as mentioned in 82

107 Table 4.5. The interferer signal level (P int ) and a desired signal level of P sig = Sensitivity + 3 db are utilized for this calculation. The minimum IIP 3 levels required from adjacent channel interferer are shown in Figure 4.17a and from non-adjacent interferer are shown in Figure 4.17b. Maximum Noise Figure(dB) MHz 40 MHz 80 MHz BPSK R = 1 2 QPSK R = 1 2 QPSK R = QAM R = QAM R = QAM R = QAM R = QAM R = QAM R = QAM R = 5 6 Modulation Scheme Figure 4.16: Maximum noise figure with respect to modulation schemes IIP3 required (dbm) MHz 40 MHz 80 MHz IIP3 required (dbm) MHz 40 MHz 80 MHz BPSK R = 1 2 QPSK R = 1 2 QPSK R = QAM R = QAM R = QAM R = QAM R = QAM R = QAM R = QAM R = 5 6 BPSK R = 1 2 QPSK R = 1 2 QPSK R = QAM R = QAM R = QAM R = QAM R = QAM R = QAM R = QAM R = 5 6 Modulation Scheme Modulation Scheme (a) For ACR specifications (b) For NACR specifications Figure 4.17: Minimum IIP 3 requirement from ACR and NACR of the WLAN standard 83

108 It is observed from Figure 4.17a and Figure 4.17b that the choice of -23 dbm as the overall receiver IIP 3 is suitable. Table 4.5: Adjacent and non-adjacent interferer levels Bandwidth (MHz) Adjacent interfere level (db) Non-adjacent interfere level (dbm) For the maximum input power available at the receiver input of -20 dbm and the peak to average ratio for the modulated signal of the standard of 9 db, the 1 db compression point of the overall receive has to be more than -11 dbm. This translates to in-band IIP 3 =-1 dbm. Although, it can be noted that at such high power levels, receiver gains are typically reduced to accommodate high signal levels thus resulting in better possible linearity compared to the receiver linearity at the highest receiver gain Sampling Frequency Phase Noise and Jitter Requirements As explained in Section , the maximum SNR at the output of the mixer is limited by the sampling clock jitter as per Equation (4.10). For EVM target of -41 db, from Equation (4.10), τ φ,deg = 0.2 or 3.6m rad for sampling frequency f s = 2.4 GHz and carrier frequency f c = 6 GHz can be obtained. Assuming that the frequency synthesizer phase noise profile is constant PSD from f S f 1 to f s +f 1 at S 0 dbc/hz. Where f s is center frequency, f 1 is the loop filter bandwidth (typically, 10% of channel bandwidth=8 MHz). The total integrated phase noise is given by Equation (4.15)). τ 2 φ = 4 S o f 1 (4.15) This results in MHz. and thus MHz offset with τ φ = 3.6 m rad, the clock jitter of 250 fs requirement at f s = 2.4 GHz Receiver specifications from ac standard Summary The system level target specifications of the dual-band WLAN subsampling receiver are listed in Table 4.6. These are utilized to design the test-chip prototype based on dual-band subsampling receiver proposed next. 84

109 Table 4.6: System level specifications for the proposed architecture Parameter 2.4 GHz 5 GHz RF Band GHz GHz First Center Frequency GHz 5.18 GHz Signal Bandwidth 20/40 MHz 20/40/80 MHz Sampling Frequency MHz MHz Closest RF Image MHz MHz Intermediate Frequency MHz MHz Noise Figure 5 db P1, db -11 dbm In-Band IIP 3 Out of Band IIP 3 Dynamic Range Phase Noise Clock Jitter 4.4 Circuit Building Blocks -1 dbm -22 dbm 72 db MHz 0.2 integrated phase noise 250 fs In this section, circuit building blocks for the proposed subsampling receiver shown in Figure 4.1 are presented in detail with the performance and design optimizations. First, the dual-band LNA circuit is presented followed by the subsampling mixer, decimation filter. Finally, the clocking scheme employed for the receiver operation and measurement buffers are presented Dual-Band Low Noise Amplifier A continuously tunable-gain and tunable-band active-balun LNA with switchable buffered active feedback is utilized in the proposed receiver as shown in Figure 4.1. The circuit diagram for the active balun LNA shown in Figure 4.18 is an improved version of [37] in terms of linearity performance. The active balun LNA configuration is realized by transistors M 1 to M 4 and the switchable active feedback is realized by M 5 and M 6. These transistors act as a switchable buffer or voltage combiner based on the LNA linearity requirement. The voltage combiner [37] acts as a differential amplifier and has twice the gain and better IIP 2 compared to buffer, which helps in improving the linearity of the LNA. However, at high gains in voltage 85

110 Vdd L L C L LNA out + LNA out - R L V freq V Ctrl Vdd Vdd M 2 C 2 M 4 C 4 Vdd M 6 M 7 C 3 M 3 SN RF in C 1 R bias M 1 M 5 S C 6 V Ctr1 C 5 R F V bias Figure 4.18: LNA circuit implementation for the 2.4GHz and 5GHz receiver combiner mode, M 5 saturates the feedback circuit, which in turn reduces the linearity of LNA and M 5 does not saturate in buffer mode. Even though the voltage combiner has higher gain and better IIP 2, the non-linearity introduced by the saturation of M 5 at high gains is the dominant factor. Hence, the active feedback should act as a buffer at high gain. The opposite is true when LNA operates in low gain mode. Here, the M 5 does not saturate as the signal swings are quite low and now the superior gain and IIP 2 of voltage combiner leads to better linearity for LNA. This switchable active feedback helps in achieving 0 dbm linearity at 21 db gain. The common-source stage (M 1 ) amplifies the input RF signal and the differential balun output is provided by the common-gate (M 2 ) and common-source (M 3 ) stages. The transistor M 7 provides the gain boosting and contributes to the open loop gain of the LNA. The input impedance matching is provided by the feedback resistor RF along with the input transistor M 1. The noise contribution of M 3 is cancelled through the capacitive coupling between M 3 and M 4 leading to the overall LNA noise figure of 2.9 db. Continuous gain tuning of 5 db to 21 db is achieved by varying the load resistor, R L and feedback resistor, R F simultaneously. Active CMOS resistors (ACR) are employed to implement R L and R F, and their values are controlled 86

111 by an external analog control voltage, V ctrl. The ACR used in the present implementation shown in Figure 4.19 is a simplified version of the circuit in [37]. Here, A and B represent the two terminals of active CMOS resistor (ACR) with the control voltage V Ctrl. The total frequency A V Ctrl C 1 M 2 R Large V Ctrl R Large M 1 C 2 B Figure 4.19: Active CMOS resistor used for gain and frequency tuning in dual-band LNA band of interest for 2.4 GHz LNA is only around 80 MHz. Frequency tuning is not required here as the bandwidth of the circuit is small. Therefore, the frequency tuning is necessary only for 5 GHz LNA, where it covers frequencies from GHz. The LC-tank load (L L -C L ) provides a tunable bandpass characteristic from 4.5 GHz to 5.7 GHz using tunable MOS varactors. The inductor is a center-tapped coil with a simulated quality factor (Q) of 13 which guarantees the output voltage balance. Due to high-quality factor of capacitors in the LC-tank load, the open-loop gain of the LNA is given by ( A v G m R out G m 2πf r L Q + 1 ) Q (4.16) Due to the higher gain also higher R F decreases the noise figure NF approximately given by NF 1 + values can be used in the feedback, which in turn γ G m R S + R S R F +... (4.17) Low NF can be achieved in the proposed LNA due to the high input transconductance (G m ) and high feedback resistor (R F ) together with noise cancellation techniques Subsampling Mixer The subsampling down-conversion mixer is realized with a fully differential track and hold circuit as shown in Figure 4.20 with transistors M 8 and M 9. Based on the subsampling principle 87

112 explained in Section 1.2, the sampling frequency (f s ) is selected from 1.78 GHz to 2.15 GHz in Equation (1.2) for the dual-band receiver. This results in the sampled signal at the first IF from 445 MHz to MHz from the Equation (1.3). f s,mixer LNA out + LNA out - C C C C R C R C M 8 M 9 Mix out + C hold C hold Mix out - IF Amplifier IF out + IF out - Subsampling Mixer Figure 4.20: Subsampling mixer down-conversion stage An external signal generator is utilized to provide sampling frequency which is given to clock buffers and afterwards distributed to the subsampling mixer and the clock divider blocks. The LNA-Mixer interface is designed for maximum voltage transfer. The common mode level of the NMOS switches M 8 and M 9 is set to zero for maximum dynamic voltage range by optimizing de-coupling capacitors C C and biasing resistors R C values for cut-off frequency of 1.6 MHz. Owing to the inherent passive nature of the mixer, standalone IIP 3 of up to 19 dbm is achieved in the simulation of mixer block. But the mixer suffers from high noise figure due to the loss in the passive structure and the C C to C hold voltage divider during tracking phase. The ratio C c to C hold is optimized to reduce this loss. Also, noise folding effect is alleviated by selecting the sampling frequency such that the noise floor coming from thermal noise is the most limiting factor and not the KT/C noise, where C is the value of the hold capacitor. The output of the subsampling mixer is fed to an IF amplifier with a fixed gain of 8 db. The IF amplifier consists of pseudo-differential common source amplifier with the buffered output stage. This helps in compensating the loss of the passive subsampling mixer stage and in providing impedance matching to the next stage bandpass decimation filter. 88

113 4.4.3 Decimation Filter The subsampling mixer based down-conversion is followed by a decimation based antialiasing filter in the proposed receiver. The principle explained in Section is utilized to implement a bandpass FIR filter using switched capacitor circuits. The eight SC cores from S1 to S8 used in the decimation filter circuit diagram are shown in Figure Clk out =Clk 12 IF out + Clk out =Clk 24 Filter input Clk Phases SC core Clk out S o,p S o,n SC core S1 Clk 14 Clk 16 SC core S2 Clk 2 Clk 4 S1 o,p S1 o,n S2 o,p S2 o,n S S S S S S S S S S S S S S S S S S S1 S2 S1 S2 S1 S2 DUMMY # Unit Capacitor # Sampling Clock Clkout=CLK12 (for S1) Clkout=CLK24 (for S2) firi out + C Ln BBA BBA I Path C n1 C n6 Clk 8 S1 S2 S3 S4 C p1 Clk 10 C p5 Clk 2 Clk 4 C Lp S1 out - S1 out + S2 out - S2 out + firi out - S1 out + S1 out - S2 out + S2 out - S3 out + S3 out - S4 out + S4 out - Clk 12 Clk 24 Clk 1 Clk 3 C Ln Clk 13 Clk 23 C n1 Clk 20 C n6 S5 S6 S7 S8 C p1 Clk 22 C p5 S5 out + S5 out - S6 out + S6 out - S7 out + S7 out - S8 out + S8 out - BBA BBA Q Path C Lp IF out + firq out + f s,filter firq out - IF out - Figure 4.21: Switched capacitor decimation bandpass filter circuit and the layout implementation for the 5 GHz decimation filter Each of the SC core is a 23-tap filter with a decimation ratio of 24. The SC cores S1, S2 are combined together and their schematic is shown in the extended figure at the top. These SC cores are operated in a time-interleaved fashion to implement the decimation ratio of 12. Thus, for S1 the output is available at the Clk 12 phase and for S2 the output is available at Clk 24. The S1-S2 combination is optimized for symmetry in layout implementation as shown in the Figure 4.21 on left. Here, each square represents a unit capacitor with the number denoting the sampling clock phase. The coefficients are rearranged as per the clock phases and further, the symmetry is achieved as presented in Table 4.7. The output of IFA (IF out +) is connected to the S1-S2 core combi- 89

114 Vdd 1.2V V bias,buff M 5 S out + M 3 M 4 S out - fir out M 1 M 2 Figure 4.22: Baseband amplifier circuit Table 4.7: Switched capacitor filter core implementation Coefficients# Clk out Clock Phase S1 # Clk 2 Clk 4 Clk 6 Clk 8 Clk 10 Clk 12 Clk 14 Clk 16 Clk 18 Clk 20 Clk 22 Clk 24 Clock Phase S2 # Clk 14 Clk 16 Clk 18 Clk 20 Clk 22 Clk 24 Clk 2 Clk 4 Clk 6 Clk 8 Clk 10 Clk 12 Sorted as per clock phases Clock Phases Clk 2 Clk 4 Clk 6 Clk 8 Clk 10 Clk 12 Clk 14 Clk 16 Clk 18 Clk 20 Clk 22 Clk 24 S1 Coeff out S2 Coeff out S1 + S2 Coeff Structure Symmetry Symmetry Coeff Symmetry Clock Clk 12 Clk 10 Clk 8 Clk 6 Clk 4 Clk 2 Clk 14 Clk 16 Clk 18 Clk 20 Clk 22 Clk 24 nation to generate I path output BB samples at the firi out + and is connected to the S5-S6 core combination to generate Q path output BB samples at firq out + respectively. Similarly, for the negative output of IFA, IF out, the BB outputs for I and Q paths are available at firi out and firq out respectively. The filter provides an additional baseband gain of 6 db as the basic structure is single-ended input to differential output and rejects the image signal by 30 db. The output of the switched capacitor filter uses a differential to single-ended baseband amplifier BBA shown in Figure 4.21 to provide a fixed gain of 12 db. 90

115 4.4.4 Clocking Scheme The clocking scheme for the decimation filter is implemented by using a D flip-flop ripple counter running at sampling frequency as shown in Figure The clock phases generated by Non-overlapping Output Clk 1 Clk 2 Clk3 Clk 24 Input DFF preset DFF clear DFF clear DFF clear f s,filter Reset Figure 4.23: Non-overlapping clock generator with clocking divider the counter are then passed on to the non-overlapping clock generator to get 24 non-overlapping Measurement Path RF out + RF in f s RF-IF Buffer Subsampling Decimation Filter LNA IF out + LNA out + Mixer Mix out + IFA T/H M LNA out - Mix out - IF out - Clk Buffer f s,mixer Clk Buffer f s,filter clk 2 clk 1 clk 4 LO Divide by 24 clk 3 clk 24 clk 23 M BaseBand Measurement Buffers RF out - BBI out + BBI out - BBQ out + BBQ out - Figure 4.24: Measurement setup for LNA and mixer characterization 91

116 phases at a frequency of around 90 MHz based on the value of sampling frequency. These phases are utilized in the switched capacitor filter to down-convert IF signal to baseband. The synchronization between sampling mixer and the decimation filter clock phases is very important as the phases separate the IF samples into I and Q path. The input clock for the divider f s,filter is generated from the clock buffer and it is synchronized to f s,mixer with respect to layout extraction clock to Q delay of the divider and the wire delays of the clock routing Measurement Buffer Two measurement buffer types are employed in the proposed receiver measurement setup as shown in Figure The RF-IF measurement buffer is utilized to characterize the dualband LNA and the performance of LNA-mixer combination. The BB measurement buffer is utilized to capture the BB output after the baseband amplifier in the I and Q paths. Both the buffers are implemented with 2.5 V transistors to eliminate the need of de-embedding of the buffer non-linearities in the measurements. The RF-IF buffer shown in Figure 4.25 is a source follower with two control inputs to provide a selection of input for LNA out and IF out outputs in Figure Vdd 2.5V M 4 M 6 LNA out C C R C C C M 2 M 3 R C IF out R C R C LNA en M 5 M 7 Mixer en RF out V bias,buff M 1 Figure 4.25: RF-IF measurement buffer Here, control pins LNA en and Mixer en are utilized to select the measurement input to the source follower. Each branch in buffer consumes 5 ma. The RF-IF buffer has a standalone linearity of 29 dbm with the loss of 2 to 2.5 db in simulations. The BB buffer is a source 92

117 Vdd 2.5V V bias,bb 1.2V M 2 BBI out firi out M 1 Figure 4.26: Baseband measurement buffer follower circuit shown in Figure The buffer provides with 50 Ω output impedance for measurements with loss of 1 db and consumes 1 ma current. The BB buffer has a linearity of 29 dbm in the simulations. 4.5 Conclusions In this chapter, the system architecture and system level optimization followed by the receiver specification requirements from the IEEE ac standard were presented. Systematic system level analysis of the receiver chain with major impairments such as sampling frequency, synthesizer phase noise, IQ mismatch and unit capacitor in the SC filter was proposed. This systematic analysis served as base for the overall system optimization. The circuit level implementations for the sub-blocks were also presented. It was demonstrated that the subsampling frequency optimization proposed in this work leads to lower noise folding due to careful selection of the sampling frequency. Inherently, lower than Nyquist sampling frequency in subsampling receiver also resulted in less complex and less power hungry frequency synthesizer. The circuit level implementations and the optimizations of the dual-band receiver on circuit level such as filter coefficients were also presented. 93

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119 Chapter 5 CMOS Implementation of Dual-band subsampling WLAN Receiver This chapter presents the layout implementation, post-layout performance, CMOS implementation and the measurements performed for the proposed dual-band sub-sampling receiver [78]. Based on the system level design optimizations and circuits presented in Chapter 4, the test-chip prototype for the dual-band subsampling receiver is implemented in 1.2 V 65-nm CMOS technology and it s performance is measured. The individual block layouts are optimized for the overall receiver chain performance, signal symmetry and for the IQ mismatch in the receiver baseband. The overall presents an excellent EVM of 40 db over 20 db input signal power range which is far superior among the published results for the subsampling receivers. This chapter is organized as follows- Section 5.1 presents the optimized layouts for individual sub-blocks and the complete dual-band subsampling receiver. Also, the post-layout performance verification carried out for the 5 GHz receiver down-conversion is presented next. Then, Section 5.2 presents the measurement setup for the test-chip. Afterwards, the measurements are presented for the LNA, decimation filter and the complete receiver chain. Finally, Section 5.3 presents the performance comparison with the state-of-the-art implementations and Section 5.4 concludes the chapter. 5.1 Layout Implementation The subsampling receiver is implemented in the 1.2 V 65-nm CMOS technology and the full custom layout is implemented for the receiver test-chip. This section presents the block level 95

120 implementations of the important blocks for the dual-band subsampling receiver followed by the top level layout implementation and post-layout performance verification LNA Layout The layout for the 2.4 GHz LNA and 5 GHz LNA is shown in Figure 5.1a and Figure 5.1b respectively. The RF input RF2g,in (RFin,5g ) and the outputs LN Aout + and LN Aout are LNAout + LNAout + RF5g,in RF2g,in LNAout LNAout (a) 2.4 GHz low noise amplifier (b) 5 GHz low noise amplifier Figure 5.1: Layout for low noise amplifier marked for 2.4 GHz (5 GHz) LNA. An increase in the layout of the 2.4 GHz LNA is due to the higher value of the LL for tuning Subsampling Mixer Layout The subsampling mixer layout for the 2.4 GHz and 5 GHz mixer are shown in Figure 5.2a and Figure 5.2b respectively. Here, the differential input to mixer from the LNA and the sampling frequency input from the clock buffers are marked. The layout also includes the IFAs as marked in the Figure 5.2a and Figure 5.2b. The de-coupling capacitors at the mixer input is seen. The capacitor values are optimized based on post-layout simulations for the lower mixer loss. The de-coupling capacitor of 1.3 pf are used for layout implementations. The sampled output of the mixer is given to the IFA and the output of the IFA is symmetrically obtained as marked in Figure 5.2a and Figure 5.2b and provided to the decimation filter. 96

121 LNAout IFAout fs,mixer Mixer IFA LNAout + Clock buffers fs,2g IFAout + LNAout IFAout Mixer fs,mixer Clock buffers IFA LNAout + fs,2g (a) 2.4 GHz subsampling mixer, IFA IFAout + (b) 5 GHz subsampling mixer, IFA Figure 5.2: Layout for subsampling mixer and IFA Decimation Filter Layout The 2.4 GHz decimation filter layouts are shown in Figure 5.3a. Here, the important subblocks such as clock divider, reset synchronizer, BBA and BBSF are marked along with the differential input to the decimation filter (IFout + and IFout ) and the baseband outputs (BBI2g,out +, BBI2g,out, BBQ2g,out + and BBQ2g,out ). Similarly, the 5 GHz decimation fil- ter layout is shown in Figure 5.3b. The input to the decimation filter are routed symmetrically and the capacitor array as explained in filter section are also seen Complete Dual-band Receiver Layout The top level layout for the complete test-chip with both the 2.4 GHz and 5 GHz receiver chains is shown in Figure 5.4. Here, the major sub-blocks of the receiver such as the LNA, mixer, and decimation filter for both the receiver chains are also marked. As mentioned in the measurement setup, additional measurement path with RF2g,out +, RF2g,out outputs for 2.4 GHz receiver and RF2g,out +, RF2g,out for 5 GHz receiver are available to measure the performance of the standalone LNA and LNA+Mixer combination. 97

122 BBI2g,out + BBI5g,out + BBQ2g,out + BBSF BBSF BBA BBA IFout + Clock Divider IFout fs,mixer BBQ2g,out BBI2g,out reset fs, f ilter Reset Sync + Clock Buffer IFout + reset fs, f ilter Clock Divider IFout fs,mixer BBQ5g,out BBI5g,out (a) 2.4 GHz decimation filter layout (b) 5 GHz decimation filter layout BBI2g 5 GHz RX 2.4 GHz Decimation Filter 5 GHz Decimation Filter BBQ5g,out BBQ5g,out + RF5g,out + RF5g,out RF2g,out RF2g,out GHz RX BBI5g,out BBI5g,out + fs,5g LNA + Mixer fs,2g RF2g,in LNA + Mixer RF5g,in BBI2g + BBQ2g,out Figure 5.3: Layout for decimation filter BBQ2g,out + Reset Sync + Clock Buffer BBQ5g,out + Figure 5.4: Top level layout of the complete test-chip with both the receiver chains 98

123 5.1.5 Post-layout Performance Results The post-layout operation of the dual-band receiver is verified with RC extracted netlist and the performance is presented in this section. To verify the proper operation, a transient simulation is carried out with 5310 MHz RF input with 40 dbm input power to 5 GHz receiver chain with GHz sampling frequency signal applied to the LO. The clock divider operation is verified as shown in Figure 5.5. Here, the divided clock phases are seen. At the baseband Amplitude (V) Time (ns) Clk 1 Clk 2 Clk 12 Clk 13 Clk 23 Clk 24 Clk reset Figure 5.5: Post-layout simulated clock phases for 5 GHz receiver chain output, the transient 10 MHz I and Q component is seen in Figure 5.6. The overall performance Amplitude (mv) BBI 5g,out BBQ 5g,out Time (ns) Figure 5.6: Post-layout simulated BB output for 5 GHz receiver chain of the receiver chains is summarized in Table 5.1. Table 5.1: Post-layout performance summary Parameter LNA Mixer IFA Filter+BBA BBSF Voltage Gain Av (db) Noise Figure NF (db) IIP 3 (dbm)

124 5.2 CMOS Implementation The dual-band subsampling receiver test chip is implemented in 1.2 V 65-nm CMOS technology with an active area of 0.72 mm2. This section presents firstly the measurements set-up utilized for test chip verification, followed by individual building block level measurements and lastly the complete receiver chain measurements. The performance of the proposed receiver is compared with the state-of-the-art implementations and the summary of measurements is presented CMOS Measurement Setup The test chip is directly glued on to the PCB as shown in Figure 5.7 and measurements are BBQ5g,out + BBI2g,out + BBI2g,out BBI5g,out BBI2g + BBQ2g,out + BBQ5g,out BBI2g BBI5g,out + 5 GHz RX 2.4 GHz Decimation Filter 5 GHz Decimation Filter BBQ5g,out BBI5g,out BBI5g,out + fs,5g LNA + Mixer fs,2g RF2g,in RF5g,in fs,5g fs,2g LNA + Mixer RF2g,in BBQ5g,out + RF5g,out + RF5g,out RF2g,out RF2g,out GHz RX RF5g,in BBQ2g,out BBQ2g,out BBQ2g,out + RF5g,out + RF5g,out RF2g,out RF2g,out + performed for the complete receiver chain. On the left side, the PCB with marked I/O ports Figure 5.7: Characterization board photograph is shown and on the right side, the extended view of the die micro-photograph is shown. The important sub-blocks such as LNA, mixer, decimation filter are marked for both the receiver chains. The 4 layer PCB with co-planar wave guides is utilized for high-frequency 50 Ω input and output ports. These high-frequency outputs are needed for standalone LNA characterization as per Figure The block diagram of the measurement set-up is shown in Figure 5.8 with the measurement equipment utilized for the measurement. The test chip is given 1.2 V and 2.5 V supply and all the core blocks use 1.2 V. The 2.5 V supply is utilized only for I/O pad ring and measurement buffers. The test chip utilized separate supply domains for both receiver chains 100