A Digitally Configurable Receiver for Multi-Constellation GNSS

Transcription

1 Innovative Navigation using new GNSS SIGnals with Hybridised Technologies A Digitally Configurable Receiver for Multi-Constellation GNSS

2 Westminster Contributors Prof. Izzet Kale Dr. Yacine Adane Dr. Alper Ucar Mr. Burak Bardak Mr. Ilker Yavuz

3 Overview Introduction Overview of a Typical GNSS Receiver Next Generation GNSS Sub-Nyquist Sampling (Subsampling) Receivers A Digitally Configurable Receiver (DCR) for Multi- Constellation GNSS Dual RF Front-end Architecture Digital Baseband Processor Conclusions Future Work

4 Introduction

5 A Typical GNSS Receiver Antenna DSP RF Frontend ADC Acquisition Tracking Demodulation Range Processing Position (x,y,z) Received signal is below the thermal noise floor 128.5dBm for GPS L1 C/A SNR in 2.046MHz 0 K is dB The RF front-end down-converts the signals to an IF Heterodyne RF Front-end (Dual or Triple Down-conversion) Low-IF RF Front-end (Single down-conversion) Sub-Nyquist Sampling (Subsampling) RF Front-end (Downconversion via intentional aliasing) A/D conversion at IF (1 to 3 bits) From RF Front-end ~ AAF S/H n-bit Quantizer To DSP

6 Next Generation GNSS Faster chipping rates lead to a sharper main peak in the auto-correlation function Correlation main peak multipath component Better range precision Better multipath performance Longer codes have narrower frequency bin spacing GPS L1 C/A Correlation main peak 300 multipath component Distance [m] Reduced vulnerability to narrowband interference since the amount of power per frequency bin is reduced GPS L5 Distance [m] Signals from multiple frequencies enable ionosphere estimation by measuring the delay between EM waves ARNS Galileo E5 Galileo E5a Galileo E5b GPS L5 Galileo GPS (Bloc III) GPS L2 Galileo E6 1191,795 MHz 1278,75 MHz ARNS Galileo L1 GPS L1 1575,42 MHz 1176,45 MHz 1227,6 MHz 1575,42 MHz

7 Subsampling Receivers ADC should be placed as near to the antenna as possible in a Digitally Configured Radio (DCR) Frequency translation via intentional aliasing Eliminating the need for analogue mixers Shifting the IF stage into the digital domain, hence eliminating the need for IF analogue filters Minimizing the signal distortion caused by analogue impairments Key Components Anti-aliasing RF Filter(s) Low Jitter ADC Magnitude f S f L Df f 0 f U Frequency Wideband Antenna GPS L1 Receiver IC, Gramegna et.al., IEEE Journal of Solid-state Circuits, vol. 41, no. 3, 2006 Gain G Tunable BPF ~ ADC DSP The Concept of SDR

8 A Digitally Configurable Receiver for Multi-Constellation GNSS

9 Digitally Configurable Receiver Requirements Dual-channel RF front-end for left/right-hand polarized antennas Fast update rate (down to 500 ms) Multi-constellation GPS L1/L2C (CDMA) GLONASS G1/G2 (FDMA) GALILEO E1 can be easily added Correlation outputs (Early/Prompt/Late) at each code epoch (1 to 10 ms) Programmable correlator spacing and loop filter bandwidth

10 Digitally Configurable Receiver Two separate RF channels synchronised with a single master atomic (Cs/Rb) clocks Both RF channels are connected to a high-speed dualchannel ADC, which digitizes and down-converts each of the incoming RF into an IF Digital signal processing is performed with a HW/SW co-design approach (FPGA/Linux Workstation) Cs/Rb Oscillator 10MHz -115dBc/Hz@100Hz LO Horizontal Polarization Antenna Vertical Polarization Antenna Dual Multi- Frequency RF Frond-End GPS L1/L2C, Glonass G1/G2 Galileo E1 Dual-Channel ADC Horizontal Channel 4-bit Vertical Channel Virtex 5 FPGA - Data Capture - Tracking Loops PCIe 4Gbit/s Linux Workstation - FFT Acquisition - Code/Carrier Discriminators - User Interface - RINEX File

11 Dual Channel RF Front-End

12 db(s(2,1)) Anti Aliasing RF Filters Home-made micro-strip filters High flexibility, low cost, good rejection, flat group delay, low insertion loss, compact size Dually-diplexed folded resonators Good performance when used with cascaded m5 m6 freq= 1.574GHz amplifiers db(s(2,1))= m2 freq= 1.187GHz db(s(2,1))= m2 m3 freq= 1.633GHz db(s(2,1))= m3 freq= 1.281GHz db(s(2,1))= m5m Dual-band Micro-strip RF Filters freq, GHz Measured Filter Response

13 Low-Jitter High Speed Clock Ability to generate a master clock from 10 MHz to 500 MHz Chip Scale Atomic Clock (CSAC) oscillator as a reference ensures a superior MHz the clock jitter is σ c =150 fs Phase Noise Plot

14 Low Jitter High Speed Clock Precision clock conditioner that provides low-noise jitter cleaning, clock multiplication Two cascaded PLL PLL1 provides a low-noise jitter cleaner function PLL2 performs the clock generation

15 High Speed Dual ADC Sampling rate range up to 500 MS/s RF input bandwidth up to 1.6 GHz 1:2 demultiplexer feeds two LVDS buses Time-Interleaved The output data rate reduced in each bus to half the sampling rate. Aperture Jitter 0.4 ps

16 Dual-Channel RF Front-End Channel 0 Channel 1 Dual Channel RF Frond-end PCB RF Frond-end Connected to the Clock Board and the Virtex-5 FPGA

17 The Baseband Processor

18 The Baseband Processor Hardware/Software Co-design Approach Correlations calculated on the FPGA to enable real-time satellite tracking FPGA connected to Linux workstation via highspeed PCIe Post-processing done on Linux workstation Cs/Rb Oscillator 10MHz LO RF Front-End Virtex-5 FPGA Horizontal Polarization Antenna Vertical Polarization Antenna Dual Multi- Frequency RF Frond-End GPS L1/L2C, Glonass G1/G2 Galileo E1 Dual-Channel ADC Horizontal Channel 4-bit Vertical Channel Virtex 5 FPGA - Data Capture - Tracking Loops PCIe 4Gbit/s Linux Workstation - FFT Acquisition - Code/Carrier Discriminators - User Interface - RINEX File

19 HW/SW Design Flow # of Acquired Satellites < 4 PLL ADC Equivalent # of Sequential Correlations via IFFT Doppler Search Interval (Default: 500Hz) Acquisition Threshold 1 Acquire # of Acquired Satellites > 4 Digital Frontend FPGA PCIe 2 Carrier Pull-in Carrier Frequency Resolution (Default: 10Hz) FFT Acquisition PC C/N 0 > 30dB-Hz Position Update Interval Correlator Spacing Code/Carrier Loop Filter Bandwidth Discriminator Type 3 Track 4 RINEX & Other Outputs Tracking Processor FPGA Tracking Co- Processor PC Simplified Signal Processing Flowchart Measurements PC

20 Resulting IF [MHz] G1 L1 The Digital Front-End Delivers signals of interest from the ADC to the baseband processor with minimum aliasing and a low sampling rate Power/frequency (db/hz) 20 Welch Power Spectral Density Estimate L5/E5a E5bL2 G2 E6 L1 G GPS L1 Glonass G L2C G X: 241 Y: GPS L2C Glonass G Frequency (GHz) L-Band Spectrum after RF Filters (Simulated) Sampling Frequency [MHz] Ladder Diagram for Signals of Interest to Find the Minimum Sub-Nyquist Sampling Rate

21 The Digital Front-End (2) From PLL Power/frequency (db/hz) D2S DCM 13.37MS/s (GPS L1/L2C) 24.08MS/s (GLONASS G2) 30.10MS/s (GLONASS G1) CLK MUX From ADC MS/s DI_p DI_n DQ_p DQ_n 4 D2S MS/s 4 MUX MS/s 4 Bandpass Filter GPS L1_ MUX 4 Shift Register Welch Power Spectral Density Estimate L2 G2 Differential Frequency (MHz) Spectrum after Sub-Nyquist Sampling at MS/s (Simulated) G1 L1 Single-ended Bandpass Filter GPS L1_2 Bandpass Filter GPS L2_1 Bandpass Filter GPS L2_1 Bandpass Filter GLONASS G1_1 Bandpass Filter GLONASS G1_2 Bandpass Filter GLONASS G2_1 Bandpass Filter GLONASS G2_ CLK MUX 13.37MS/s 24.08MS/s 30.10MS/s FIFO PCIe

22 Magnitude Signal Acquisition 2D search (code offset/carrier frequency bins) to initialize the code generator and carrier NCO in the tracking channels Time-domain search (time consuming) Frequency-domain search (fast/computationally expensive/large Silicon area for eventual integration) DCR cold start acquisition (7 to 30s) DCR warm start acquisition (3 to 12s) I 8 x 10 5 SVN 1 From ADC 0 p / 2 Q NCO. 2 Correlation FFT IFFT Values 500 Hz increments Complex Conjugate Code Phase Resolution : 1 Sample DFT Code Generator Frequency-domain acquisition Frequency [MHz] Code Offset [chips] Acquired Signal (PRN01) 1000 DFT :

23 Signal Tracking (1) Enable From Digital Front-End Mixer 4 I 8 X 4 4 Q X Mixer 8 X X X 8 X IE 8 IP 8 IL X QP QE 8 Accumulate & Dump Accumulate & Dump Accumulate & Dump Accumulate & Dump Accumulate & Dump 21 IE 21 IP 21 IL 21 QE 21 QP FIFO PCIe Core To Linux Workstation PCIe Controller RAM Code Loop Discriminator Carrier Loop Discriminator Code Loop Filter Carrier Loop Filter S Code NCO Bias Carrier NCO Bias S Position Update Rate SIN TIC COS Programmable Correlator Spacing 1 1 P L Shift Register E 1 X QL Code Generator Code Phase Counter 1 Accumulate & Dump DUMP Offset 11 Register Code NCO Carrier NCO CarrierPhase Counter QL 11 Epoch Counter Programmable Tracking Coprocessor (Linux Workstation) PCIe Controller Code/Carrier Filter Code/Carrier Discriminator Pseudorange Calculator RINEX writer Single Tracking Channel (Virtex-5 FPGA)

24 PCIe Core Signal Tracking (3) FIFOs Tracking Channels Filters GLONASS G2 GLONASS G1 GPS L2C TIC GPS L1 Tracking Processor 0 Constellation 0 Constellation 0Tracking Constellation Processor 0 1 I & Q [21] Carrier Register [32] Code Register [21] PC Epoch Register [21] I & Q [32] Carrier Register [32] Code Register [21] PC Epoch PC Register [21] Slice Registers Virtex-5 FPGA Floorplan Slice LUTs Memory IOBs Baseband* 25% 15% 10% N/A PCIe Core 15% 10% 9% N/A Total 35% 25% 19% 11% *Device Utilization for 12 Tracking Channels Tracking Processor 11 Baseband Processor for 4 constellations I & Q [21] Carrier Register [32] Code Register [21] PC Epoch Register [21]

25 Signal Tracking Results PRN Time (s) PRN Time (s) PRN Time (s) PRN Time (s) PRN Time (s) PRN Time (s) Decoded Navigation Bits SV C/N 0 [db-hz] Elevation [Degrees] Good C/N0 performance Successful Tracking of Satellites with an Elevation Angle down to 7 0 Navigation Solution

26 Conclusions and Future Work Shown good tracking performance with high C/N0 Tracking channels driven by an atomic clock Tailor-made for cutting-edge research applications Correlator outputs available at each epoch Programmable correlator spacing, loop filter bandwidth to change the parameters at will Two-highly synchronized receivers Acquisition implemented on the FPGA with novel reduced-complexity FFT approach (Poster session) Fully-integrated Receiver (RF+DSP) on CMOS IC to follow

27 Thanks for attention! Questions?