Implementation And Evaluation Of An RF Receiver Architecture Using An Undersampling Track-And-Hold Circuit

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1 Implementation And Evaluation Of An RF Receiver Architecture Using An Undersampling Track-And-Hold Circuit Magnus Dahlbäck LiTH-ISY-EX Linköping 5 January 2004

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3 Implementation And Evaluation Of An RF Receiver Architecture Using An Undersampling Track-And-Hold Circuit Examensarbete utfört i Elektroniksystem vid Linköpings tekniska högskola av Magnus Dahlbäck LiTH-ISY-EX Handledare: Mark Vesterbacka Examinator Mark Vesterbacka Linköping

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5 Avdelning, Institution Division, Department Datum Date Institutionen för systemteknik LINKÖPING Språk Language Svenska/Swedish X Engelska/English Rapporttyp Report category Licentiatavhandling X Examensarbete ISBN ISRN LITH-ISY-EX C-uppsats D-uppsats Övrig rapport Serietitel och serienummer Title of series, numbering ISSN URL för elektronisk version Titel Title Implementation och utvärdering av en RF-mottagare baserad på en undersamplande track-and-hold-krets Implementation and Evaluation of an RF Receiver Architecture Using an Undersampling Track-and-Hold Circuit Författare Author Magnus Dahlbäck Sammanfattning Abstract Today's radio frequency receivers for digital wireless communication are getting more and more complex. A single receiver unit should support multiple bands, have a wide bandwidth, be flexible and show good performance. To fulfil these requirements, new receiver architectures have to be developed and used. One possible alternative is the RF undersampling architecture. This thesis evaluates the RF undersampling architecture, which make use of an undersampling track-and-hold circuit with very wide bandwidth to perform direct sampling of the RF carrier before the analogue-to-digital converter. The architecture s main advantages and drawbacks are identified and analyzed. Also, techniques and improvements to solve or reduce the main problems of the RF undersampling receiver are proposed. Nyckelord Keyword RF, track-and-hold, undersampling, receiver, noise folding, harmonics aliasing

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7 Abstract Todays radio frequency receivers for digital wireless communication are getting more and more complex. A single receiver unit should support multiple bands, have a wide bandwidth, be flexible and show good performance. To fulfil these requirements, new receiver architectures have to be developed and used. One possible alternative is the RF undersampling architecture. The RF undersampling architecture, which make use of an undersampling track-and-hold circuit with very wide bandwidth to perform direct sampling of the RF carrier before the analogue-to-digital converter, is evaluated in this thesis. The architecture s main advantages and drawbacks are identified and analyzed. Also, techniques and improvements to solve or reduce the main problems of the RF undersampling receiver are proposed.

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9 1 Introduction Background Assignment Main Thesis Questions Motivation For The GSM900 Choice Method Prestudy Measurements Evaluation Limitations Disposition Reading instructions RF Receiver Basics RF Overview The Generic RF Receiver Theory Concepts Noise Figure Sensitivity Harmonic Distortion Intermodulation Third-Order Intercept Point Mixer-Based Receiver Architectures The Mixer - An Introduction Downconversion Image Response LO Leakage Half-IF Response LO Spurious Responses The Superheterodyne Architecture Component Density Sensitivity And Selectivity The Direct-Conversion Architecture Noise and Distortion Performance Component Density Table of Contents

10 4 The RF Undersampling Architecture Architecture Overview Undersampling Downconversion By Undersampling Advantages Less Analogue Processing Multiple Frequency Bands Flexibility Noise Folding SNR Degradation Sample Frequency Considerations Front-End Gain Further Reduction Of Performance Loss Clock Noise Harmonics Aliasing Low-Pass Filtering Changing Sample Frequencies T/H and ADC Integration Considerations Sample Clocks Frequencies Clocks Phase Difference Measurement Results Measurements Setup The T/H Circuit T/H Measurements Setup T/H And ADC Integration Measurement Setup T/H Measurement Results Downconversion Noise Folding Noise Figure Harmonic Distortion Two-Tone Intermodulation Distortion T/H And ADC Integration Measurement Results Clocks Phase Difference Spectrum Response Spectrum Response With Intermediate Filtering 51 Table of Contents

11 6 Conclusions Future Work Differential Signalling Double Scanning Variable Sample Frequencies References Recommended Literature Table of Contents

12 Table of Contents Magnus Dahlbäck

13 List of Figures Figure 2-1. The front-end, the analogue-to-digital interface and the Digital processing hardware... 6 Figure 2-2. Harmonic distortion Figure 2-3. Power changes for harmonic signals Figure 2-4. Second- and third-order intermodulation products Figure 2-5. Third-order IMD rejection ratio Figure 2-6. Floor of in-band IMD products Figure 2-7. Distortion from adjacent channels Figure 2-8. Third-order intercept point Figure 3-9. Frequency translation in a mixer Figure The image signal Figure LO leakage to RF input Figure Half-IF spurious response Figure LO spurious responses Figure 3-1. The typical superheterodyne architecture Figure 3-2. The typical direct-conversion architecture Figure 4-1. The RF undersampling architecture Figure 4-2. The wide-band track-and-hold in front of the ADC Figure 4-3. Frequency response of Nyquist sampling Figure 4-4. Aliasing distortion Figure 4-5. Frequency spectrum before undersampling Figure 4-6. Downconversion by undersampling Figure 4-7. Functional diagram for support of multiple RF bands Figure 4-8. Signal spectrum before noise folding Figure 4-9. Signal spectrum after noise folding Figure Modelled SNR degradation versus sample frequency Figure total noise figure versus T/H noise figure and front-end gain Figure Modelled SNR degradation due to noise folding versus difference between in-band and out-band noise power density Figure Expected T/H output spectrum for GSM downlink Figure Expected ADC output spectrum for GSM downlink

14 Figure Aliasing of second-order harmonics Figure Elimination of harmonics aliasing by low-pass filtering Figure Changing clock frequency may solve harmonics aliasing Figure T/H output and ADC sampling Figure 5-1. RTH010 functional diagram Figure 5-2. Close-up of the T/H PCB Figure 5-3. T/H measurements setup Figure 5-4. TH1 and TH2 out-of-phase clocking Figure 5-5. The MP4 PCI card mounted in a PC Figure 5-6. T/H and ADC clocking Figure 5-7. T/H output spectrum confirms downconversion by undersampling Figure 5-8. T/H output spectrum for GSM Downlink signal in first nyquist zone when sample frequency is MHz Figure 5-9. T/H output spectrum for GSM Downlink signal in first nyquist zone when sample frequency is MHz Figure Measured SNR degradation versus. sample frequency Figure T/H output harmonics when sample frequency is MHz Figure T/H output harmonics when sample frequency is MHz Figure Two-tone intermodulation distortion Figure T/H output spectrum DC - 1 GHz Figure ADC output spectrum Figure Low-pass filter output spectrum DC - 1 GHz Figure ADC output spectrum with filter Figure 6-1. Mathematical description for elimination of even-order harmonics Figure 6-2. First scan (unattenuated input signal) Figure 6-3. Second scan (attenuated input signal)... 58

15 Terminology ADC Analog-to-Digital Converter db Decibel P 1 db = 10log 10 P2 dbc Decibel relative to carrier dbm Decibel relative to 1 mw dbm GSM900 The 900 MHz GSM band IF Intermediate Frequency IIP3 Third-Order Input Intercept Point IMD Intermodulation Distortion I/Q In-phase and quadrature-phase signals used for demodulation LO Local Oscillator NF Noise Figure P 10log = 3 Nyquist Region When sampling, the frequency spectrum is often divided into Nyquist regions. The first Nyquist region is DC to half the sample

16 frequency, the second Nyquist region is half the sample frequency to the sample frequency and so on. PCB Printed Circuit Board RF Radio Frequency SFDR Spurious-Free Dynamic Range SNR Signal-to-Noise Ratio SDR Software Defined Radio T/H Track-and-Hold

17 1 Introduction This is the thesis for the Master of Science in Computer Science and Engineering at Linköping Institute of Technology, Sweden. It was carried out as a research project at Swedish Defence Research Agency (FOI), Linköping, Sweden. 1.1 Background To meet up with increasing performance requirements, improve flexibility and shorten the design time of radio-frequency receivers, it is desirable to design an all-round receiver - a receiver with support for several frequency bands, multiple standards and different applications. Therefore, functionality is to a great extent moved from analogue hardware to software implemented on digital hardware. This approach gives much flexibility since the analogue-to-digital converter (ADC) is moved closer to the antenna and the receiver can be digitally configured to meet the current needs. Software Defined Radio (SDR) is today a general term for these types of configurable and programmable RF receivers. However, there are still many improvements to be made before the ideal SDR receiver becomes a reality. The main problem with SDR receivers today is that as functionality is moved from analogue hardware to software, the ADC and digital-signal-processing (DSP) performance requirements increases drastically, especially the ADC requirements. To ease the ADC and DSP requirements, the signal must be down-converted from the high-frequency RF carrier band to a lower frequency band before the ADC. The conventional technique to perform this frequency downconversion is to use a mixer circuit, see section 2.3. The mixer is used in the very common superheterodyne and direct-conversion receiver architectures, which are further explained in chapter 3. However, several problems are related to the mixer and its functionality. To reduce these problems, additional analogue hardware is required, which is not desirable. Chapter 1: Introduction 1

18 1.2 Assignment Due to the desire of reducing analogue hardware to increase flexibility and to eliminate some of the mixer related problems, it is desirable to find other architectures. One possible solution is the RF undersampling architecture. The main goal of the thesis was therefore to implement and evaluate the RF undersampling architecture. In this architecture, a wide-band undersampling T/H circuit is placed in front of the ADC. Due to the nature of undersampling, see section 2.2, the RF signal is downconverted to a lower frequency manageable by the ADC. In other words, the T/H and ADC integration should result in a wide-band highperformance ADC. The main intention with the RF undersampling architecture is to reduce the analogue component count and to increase the bandwidth and flexibility Main Thesis Questions Questions that the thesis should answer are: What advantages does the RF undersampling architecture have over conventional mixer-based architectures? What problems are specific to the RF undersampling architecture and how are these solved? Motivation For The GSM900 Choice Within the scope of this thesis, but not the report, a single-channel GSM receiver was implemented to support the GSM900 band. Most theoretical examples and measurements are therefore done for GSM900 signals. The GSM900 band was chosen due to the following reasons: Easy to find suitable components Easier measuring and testing because of the density of GSM signals in the ether Different signal sources types: Strong remote base stations Weak local transmitter units 2 Section 1.2: Assignment

19 1.3 Method The thesis main goal was divided into three sub-goals: Pre-study, measurements and evaluation Prestudy To start with, the advantages and disadvantages by using an undersampling T/H followed by an ADC to perform the frequency downconversion of the RF signals were identified. The pre-study phase consisted of an exhaustive study on existing material about downconversion techniques in RF receivers and other RF receiver architectures. This material included research papers, books, web sites etc Measurements Next, lab measurements were performed to enable evaluation of the RF undersampling architecture and to verify the theoretical performance calculations. The measurements were performed for GSM900 signals Evaluation After the measurements were performed, the results were analyzed and compared with the modelled results. It was of special concern to compare the performance with the mixer-based architectures to see what advantages and problems the RF undersampling architecture has compared with the most common architectures used today. 1.4 Limitations The accuracy of the T/H performance measurements was not extremely important. Rather, the measurements were supposed to give an indication of the main performance problems of the evaluated architecture. For more detailed measurements, see [7]. The measurements and evaluation were only performed for the GSM900 band, since the primarily application FOI is interested of is for that band. There was no focus on creating a finished product in the sense that the final receiver created in this thesis should be usable in live scena- Chapter 1: Introduction 3

20 rios and real applications. The goal was to create a prototype to enable performance evaluation and field tests. 1.5 Disposition Chapter 2 Gives an introduction to RF receivers and the most important concepts and theory. Chapter 3 Presents existing receiver architectures and their advantages and disadvantages. Chapter 4 Presents the RF undersampling architecture and describes its basic structure and properties. Chapter 5 Presents all measurements performed to evaluate the RF undersampling architecture. The measurement results are analyzed and then compared with the modelled results. Chapter 6 In this chapter, conclusions are drawn and the main thesis questions are answered. Also, future work to improve the RF undersampling architecture are proposed. 1.6 Reading instructions This report is intended to be read by students at a Master of Science programme, typically Computer Science or Electrical Engineering. Basic knowledge about radio communication and signal theory is required. 4 Section 1.5: Disposition

21 2 RF Receiver Basics An introduction to the subject of wireless RF receivers is presented in this chapter as well as the most important theory concepts used in this thesis. 2.1 RF Overview Radio frequency (RF) refers to an electromagnetic field with characteristics such that it is suitable for wireless broadcasting and communication. The frequencies of these electromagnetic signals constitutes a very wide range of the electromagnetic spectrum, often defined from 9 khz to 3 GHz. Frequencies above 3 GHz are sometimes defined as RF, but more often they are referred to as the microwave spectrum. The RF spectrum can be divided into several bands. For example, the spectrum from 300 MHz to 3 GHz is defined as the Ultra High Frequency (UHF) band. The UHF band is further devided into more bands, where each band is allocated by a specific service or system. One example is the GSM system, which operates in the bands 890 MHz MHz (GSM900) and 1710 MHz MHz (GSM1800). The RF spectrum is used by many wireless communication systems, such as cellular telephony, WLAN, cordless communication, radioand television broadcasts and satellite communication. 2.2 The Generic RF Receiver The main purpose of the RF receiver is to detect RF signals within a specific band and to extract the baseband information carried in the detected RF signal. To do this, the incoming RF signal has to be processed and modified, both by the analogue and digital hardware. This includes tasks such as: Filtering Amplification Frequency downconversion Demodulation Chapter 2: RF Receiver Basics 5

22 The hardware of all existing RF receivers can be divided into three main blocks: The analogue front-end, the analogue-to-digital interface and the digital signal processing (DSP). FIGURE 2-1. THE FRONT-END, THE ANALOGUE-TO-DIGITAL INTERFACE AND THE DIGITAL PROCESSING HARDWARE. Front-end AD Interface DSP The main tasks of the front-end are band-selection filtering, amplification and frequency downconversion. However, in the RF undersampling architecture evaluated in this thesis, the front-end does not perform any downconversion. Instead, this is performed by the analogue-to-digital block. The analogue-to-digital interface converts the analogue signal to a digital representation, which is then further processed by the DSP. The DSP often performs demodulation, channel filtering and application-specific algorithms. 2.3 Theory Concepts All concepts presented in this chapter are further explained in [4] Noise Figure Each receiver component adds noise to the desired signal. The amount of added noise is defined by its noise figure: EQUATION 1 Sin N in NF = 10 log = 10 Sout Nout 10 log 10 where S is the power of the desired signal and N is the noise power. F is called the noise factor and is the linear representation of the noise figure. By this definition, it is clear that a low noise factor is better than a high noise factor. F 6 Section 2.3: Theory Concepts

23 The noise figure for a set of cascaded components cannot be calculated by just adding the individual noise figures together. Instead, Friis equation is used: EQUATION 2 F F 2 3 N tot = N 1 G1 G1G 2 i= 1 The noise factors and gains for all N cascaded components are in linear numbers, not in db. Notice that the equation above concerns total noise factor. The total noise figure is the decibel value of F tot. One important conclusion that can be drawn from Friis equation is that the noise performance degradation due to a high noise figure of a certain component can be decreased by having higher gain in the components before that component. It is also clear that the noise performance of the first component in the system is very important Sensitivity The sensitivity of a receiver or a chain of cascaded components defines the minimum acceptable signal strength at the input to obtain a certain SNR at the ADC output. It is defined as: EQUATION 3 MDS is the abbreviation of minimum-detectable signal, which is the minimum signal strength that a signal can have before disappearing into the noise floor. SNR req is the required signal-to-noise ratio in db after the ADC digitization. As given by the equation above, MDS is defined as: EQUATION 4 F 1 F 1 S + F 1 = MDS + SNRreq = n0 + NF SNR req MDS = n 0 + NF where n 0 is the thermal noise power in dbm and NF is the cascaded noise figure of the component set. The thermal noise power at room G i Chapter 2: RF Receiver Basics 7

24 temperature for a certain bandwidth can be calculated using the following expression: n0 = log10 B Harmonic Distortion No analogue component is perfectly linear. This is of great concern in RF receiver design, since the non-linearity gives rise to many difficult problems. Examples of such problems are harmonic distortion and intermodulation. When a signal is applied at the input of a non-linear circuit, the output signal will contain several harmonics of that input signal, see figure 2-2. Harmonics are non-desired signals located at multiples of the fundemental signal frequency. Assume that the signal frequency f is 10 MHz in the example below. Then the harmonics will appear at 20 MHz, 30 MHz, 40 MHz and so on. FIGURE 2-2. HARMONIC DISTORTION. f 2f 3f An interesting property of harmonics is that the amplitude changes in a different manner than the amplitude of the desired signal. The power change of a certain harmonic is directly related to the order of that harmonic. The N:th-order harmonic power changes with N times the power change of the fundamental signal. As an example, assume that the input signal has a power of 4 dbm. Further assume that the circuit gives rise to a -40 dbm second harmonic (2f) and a -60 dbm third harmonic (3f). If the input signal strength is decreased by 6dB to -2 dbm, the second harmonic decreases to Section 2.3: Theory Concepts

25 dbm (2*6=12 db change) and the third harmonic decreases to -78 dbm (3*6=18 db change). FIGURE 2-3. POWER CHANGES FOR HARMONIC SIGNALS. f 4 dbm -2 dbm 6 db 12 db 2f -40 dbm 3f -52 dbm -60 dbm -78 dbm 18 db This well-known behaviour can be used to differentiate the desired signal from its harmonics Intermodulation As mentioned, non-linearity also causes intermodulation. When signals with different frequencies are applied to the input of the nonlinear component, the non-linearity gives rise to spurious distortion signals on other frequencies. Intermodulation between two signals with different frequencies is called the two-tone intermodulation distortion. The intermodulation distortion products appear at frequencies defined by equation 5. EQUATION 5 IMD = ± Mf1 ± Nf 2, M, N = 0,1,2,3,... where f 1 and f 2 are the frequencies of the two input signals. The order of a certain intermodulation signal is defined as the sum of M and N. Chapter 2: RF Receiver Basics 9

26 Figure 2-4 shows the typical output spectrum of a non-linear device where second- and third-order IMD products are shown. The two input signals are f 1 and f 2. FIGURE 2-4. SECOND- AND THIRD-ORDER INTERMODULATION PRODUCTS. Passband f 1 f 2 f 1 -f 2 f 1 +f 2 2f 1-f 2 2f 2-f 1 2f 1+f 2 f 1+2f 2 The even-order products (f 1 -f 2 and f 1 +f 2 ) can be filtered out be the band-selection filters. However, the odd-order products, mainly the third-order products, are often impossible to filter out as they are located inside the desired band. The power difference between the desired signal and the IMD products is called the IMD rejection ratio. The power difference between the desired signal and the n:th-order IMD products is therefore called the n:th-order IMD rejection ratio. Third-order rejection ratio decrease 2 db for each 1dB increase of input signal power. In other words, the third-order IMD products power increase 3 db for each 1 db input signal level increase. FIGURE 2-5. THIRD-ORDER IMD REJECTION RATIO. f 1 f 2 2f 1 -f 2 2f 2 -f 1 3rd-Order IMD Rejection Ratio In an RF receiver, intermodulation distortion causes two types of problems: Increased in-band noise Distortion from adjacent channels 10 Section 2.3: Theory Concepts

27 All in-band signals will intermodulate with each other and generate a wide in-channel floor of IMD products, see figure 2-6. FIGURE 2-6. FLOOR OF IN-BAND IMD PRODUCTS. Non-linear System Another problem is that the IMD products created in adjacent channels can fall into the channel of interest. FIGURE 2-7. DISTORTION FROM ADJACENT CHANNELS. Non-linear System Ch. 3 Ch. 5 Ch. 7 Ch. 3 Ch. 5 Ch. 7 If the signal power of the adjacent channels is high and the channel of interest is weak, there is a risk that the desired channel will be totally drowned by the IMD products generated from other channels. Therefore, the linearity performance is very important in an RF receiver Third-Order Intercept Point When the input signal strength is increased to a certain level, the output power of the desired signal and the power of the third-order IMD products will equal, i.e. the third-order rejection ratio is zero. The input power at this point is defined as the third-order input intercept point (IIP3). Chapter 2: RF Receiver Basics 11

28 To calculate IIP3 for a certain component, the linear region of the third-order IMD and the desired signal are extrapolated and the virtual intersection between the two lines sets the IIP3, see figure 2-8. FIGURE 2-8. THIRD-ORDER INTERCEPT POINT. Pout Fundamental 3 rd IMD 3 IIP3 Pin The following relationship between the third-order intercept point and the third-order rejection ratio is often used: EQUATION 6 RR3 OIP = Pout out where OIP3 is the output third-order intercept point, that is, IIP3 + gain. 12 Section 2.3: Theory Concepts

29 3 Mixer-Based Receiver Architectures As already stressed, the main purpose of this thesis is to evaluate the RF undersampling receiver. To do this, it is necessary to know about the alternatives and their respective benefits and drawbacks. Thus, the intention of this chapter is to present existing receiver architectures and their properties, good as bad. 3.1 The Mixer - An Introduction The receiver designed in this thesis does not use any mixer to perform the signal downconversion from RF to a lower frequency band. However, it is still necessary to study the mixer circuit and its properties to make it possible to draw conclusions on whether it is preferable to use an undersampling T/H instead of the conventional mixing technique, which is used in the superheterodyne and directconversion architectures, see sections 3.2 and 3.3. Problems related to the mixer circuit are common problems in the architectures based on it Downconversion In a mixer-based RF receiver, the mixer circuit is used to translate RF carrier frequencies to a lower intermediate frequency (IF).The translation is performed by mixing (multiplying) a local oscillator (LO) signal with the RF signal. This results in one lower frequency and one higher frequency component. Figure 3-9 illustrates this effect. FIGURE 3-9. FREQUENCY TRANSLATION IN A MIXER. LO LO-RF RF RF+LO Chapter 3: Mixer-Based Receiver Architectures 13

30 The mathematical description of this behaviour is given by equation 7. EQUATION 7 A1 A2 y( t) = A1 sin ω RFt A2 sin ωlot = LO RF sin LO Image Response It is possible that another RF signal, called the image signal, also will mix with the LO signal and distort the desired IF output. The image and LO frequencies are spaced apart by an amount equalling the difference between the desired RF signal and the LO. The mixing will cause the image signal to end up on the same IF frequency as the RF carrier. The image signal must be removed by an RF image-reject filter before the mixer. The sharpness requirement of this filter depends on the sample frequency used. FIGURE THE IMAGE SIGNAL. Distortion! RF LO ( sin( ω ω ) t + ( ω ω ) t) RF LO-RF Image Signal LO Leakage Another common problem related to the mixer is LO leakage. Due to parasitic conductances between the LO and RF ports, the LO signal can leak to the RF input and vice versa. FIGURE LO LEAKAGE TO RF INPUT. RF DC Offset LO The result of this leakage is that the LO signal is mixed with itself and the output will therefore suffer from a DC offset due to a large zero-frequency component. If unlucky, this DC offset saturates the mixer and following circuits, which can lead to a severe performance 14 Section 3.1: The Mixer - An Introduction

31 degradation. If the LO signal also leaks to a prior amplifier, the DC component can be much larger than the desired signal Half-IF Response The mixer suffers from a problem called half-if spurious response, which is similar to the image response problem. The undesired half- IF signal, f u, is located exactly between the RF signal and the LO signal, see figure The LO and its second harmonic are shown with solid spectral lines. The half-if and the desired RF signal and their respective second harmonics are both shown in solid spectral lines. FIGURE HALF-IF SPURIOUS RESPONSE. Distortion! RF f u LO 2RF 2f u 2LO 2LO-2f u LO-RF The second harmonic of the half-if signal, called the half-if spur, mixes with the second harmonic of the LO signal. This mixing will also produce an IF signal, shown with a dotted spectral line, located exactly on the desired IF output, which will be distorted LO Spurious Responses The problem of LO spurious responses is similar to the image response problem, but instead of image signals mixing directly with the LO signal, they are mixed with the LO harmonics. All RF signals located one IF distance away from an LO harmonic will mix with the respective harmonic to produce a distorting IF signal. This behaviour is illustrated in figure 3-13, where the second and third LO harmonics are included. FIGURE LO SPURIOUS RESPONSES. Distortion! LO-RF RF LO 2LO 3LO Chapter 3: Mixer-Based Receiver Architectures 15

32 3.2 The Superheterodyne Architecture The superheterodyne architecture is the classical receiver architecture. It was first devised during the first world war and is still today the definitely most commonly used architecture for RF receivers. It is currently being challenged by other architectures, such as the directconversion and the RF undersampling architectures. The single-conversion superheterodyne receiver front-end is shown in figure 3-1. FIGURE 3-1. THE TYPICAL SUPERHETERODYNE ARCHITECTURE. ADC 90 LO LO ADC The distinguishing feature of the superheterodyne architecture is that the downconversion from RF to baseband is performed using one intermediate frequency stage. The RF signal is down-converted by a mixer to an IF frequency, where additional signal processing is performed. It is then down-converted to baseband and separated into its I- and Q components by the second mixer pair Component Density As a consequence of its great performance, the superheterodyne receiver requires many analogue components, especially in the multi-stage cases. A high analogue component density is not desirable, since it implies limited flexibility, increased design- and manufacturing costs, a larger chip area and high overall complexity Sensitivity And Selectivity The superheterodyne receiver offers excellent selectivity. Selectivity is the ability to isolate the desired signal, that is, rejecting all nondesired signals. The reason for this is that the superheterodyne receiver operates on lower (IF) frequencies, which makes selective filtering more effective. The selectivity is especially high in multi-stage (more than one IF stage) superheterodyne receivers. 16 Section 3.2: The Superheterodyne Architecture

33 Another benefit of the superheterodyne receiver is its good sensitivity. A proper choice of IF frequency or IF frequencies improves IF amplification and filtering, leading to great overall sensitivity. 3.3 The Direct-Conversion Architecture The direct-conversion architecture is a special case of the superheterodyne architecture. Due to its properties, it is also called zero-if and homodyne architecture. Figure 3-2 shows the typical direct-conversion receiver front-end. FIGURE 3-2. THE TYPICAL DIRECT-CONVERSION ARCHITECTURE. ADC 90 LO ADC As shown by the figure, the significant feature of the direct-conversion receiver is that the RF signal is converted directly to baseband, thereby its name. The downconversion process also splits the baseband signal into its inphase (I)- and quadrature-phase (Q) components for demodulation Noise and Distortion Performance Together with these sought-after properties, some problems are introduced, see [1],such as DC-offset 1/f-noise Even-order distortion I/Q mismatch One of the main problems of the direct-conversion receiver is that it suffers from time-varying DC offsets. Insufficient LO-RF isolation causes LO-leakage to the signal prior to the mixer. The LO signal leakage component is then self-mixed in the mixer, which generates DC as a mixing product at the mixer output. The DC offset interfere with Chapter 3: Mixer-Based Receiver Architectures 17

34 the desired signal and may saturate following circuits, such as the ADC. Another problem is the flicker noise, denoted 1/f-noise. 1/f-noise is a low-frequency noise device noise that can distort signals in the receiver chain. The 1/f-noise is especially serious in direct-conversion receivers, due to the baseband signal processing. The third problem also has to do with low-frequency noise. Two adjacent signals present at the LNA input may be affected by intermodulation and generate a low-frequency even-order distortion component interfering with the desired signal. The problems related to the direct-conversion strategy can nowadays be partially solved by careful receiver design and by utilizing special baseband signal processing algorithms. For example, the secondorder IMD products can be minimized by using differential circuits and balanced transmission lines. The DC offset problem is handled by measuring the DC component and executing special algorithms. The separation into the I and Q components is performed at RF frequency. Due to the high input frequency, there is a risk of mismatch between the I and Q signals, which will degrade the SNR Component Density The direct-conversion receiver eliminates the IF stage because it down-converts the RF signal directly to baseband.. This drastically reduces the number of components. Without the IF stage, there is no need for the IF mixer or the IF LO. Direct-conversion also eliminates the image-rejection problem because the image is the channel itself. It is therefore possible to also remove the image-reject filter. Due to the reduced component number and the fact that the off-chip image-reject filter can be removed, the direct-conversion architecture is suitable for designs where cost, power consumption and chip area are central design parameters. A direct-conversion receiver is preferred when the entire receiver is to be implemented on a single chip. 18 Section 3.3: The Direct-Conversion Architecture

35 4 The RF Undersampling Architecture In this chapter, the RF undersampling architecture is presented. It describes the basic structure and properties of the RF undersampling architecture and how the architecture is realized. Also, the main workhorse of the RF undersampling architecture, the track-and-hold circuit, is described. 4.1 Architecture Overview The superheterodyne and the direct-conversion architectures both have important advantages but they also suffers from unwanted drawbacks. The intention with the RF undersampling architecture is to combine the benefits from these two architectures and eliminate the main problems. Primarily, the performance of the superheterodyne receiver and the low component count and flexibility of the direct-conversion architecture are desired. The RF undersampling architecture is simple and straight-forward. The analogue RF front-end consists of band-specific gain stages and band-pass filters. The front-end is followed by a wide-band digitizing block. FIGURE 4-1. THE RF UNDERSAMPLING ARCHITECTURE. Band-specific Digitizing Block To make digitization of RF signals possible in the RF undersampling architecture, the digitizing block in figure 4-1 needs to be very fast and have a wide bandwidth. However, few ADC circuits fulfil both these requirements today. ADC s that are fast enough to digitize RF signals often have a poor SFDR. Instead, in the RF undersampling Chapter 4: The RF Undersampling Architecture 19

36 architecture, a fast track-and-hold circuit with very wide bandwidth is placed in front of the ADC, see figure 4-2. FIGURE 4-2. THE WIDE-BAND TRACK-AND-HOLD IN FRONT OF THE ADC. RF T/H IF ADC Undersampling Oversampling The undersampling and downconversion is performed by the trackand-hold circuit, which eases ADC bandwidth and sample rate requirements drastically. The T/H and ADC together results in a very wide-band and fast digitizing block, where the T/H interfaces the high-frequency RF signals and down-converts them to a frequency manageable for the digitizing ADC circuit. This is the unique property of the RF undersampling architecture and thereby its name. This solution is possible because track-and-hold circuits, at least the one used in this thesis, can have a much wider bandwidth, offer better sample performance and are overall more flexible than most ADC circuits. The majority of the signal processing is performed in the digital domain, such as downconversion to baseband, additional filtering and demodulation Undersampling To really understand the functionality of the RF undersampling architecture, it is necessary to understand the concept of undersampling. The sampling theorem states that to avoid aliasing distortion and to enable correct signal reconstruction for a band-limited signal, the sampling rate (assumed uniform) must be at least twice as high as the maximum signal frequency, i.e., EQUATION 8 f S 2 f h where f S is the sampling frequency and f h is the highest frequency component of the desired signal. 20 Section 4.1: Architecture Overview

37 This minimum sample rate is defined as the Nyquist sample rate. Practically, the sample rate should be at least 2.5 times greater than the maximum signal frequency to relax anti-alias filter requirements. Figure 4-3 shows the frequency response of a signal sampled by a signal with frequency 2f h = 600 MHz. No aliasing distortion exists. FIGURE 4-3. FREQUENCY RESPONSE OF NYQUIST SAMPLING. f S f h MHz However, if the maximum frequency of the original signal would have been 400 MHz, that is, greater than half the sample frequency, the aliases would interfere with each other and result in signal distortion. FIGURE 4-4. ALIASING DISTORTION. Aliasing Distortion f S f h MHz Generally, it is not possible to perform Nyquist sampling of RF signals. Sampling at Nyquist rate or above would require extremely high sample rates. For example, a 2.4 GHz signal would require a sample rate of at least 4.8 GHz. A high sample rate leads to a very high data rate, expensive sample circuits, troublesome generation of high-frequency clock signals and so on. Nyquist sampling of RF signals is therefore not practically feasible. To overcome this problem, undersampling can be used. Undersampling is a modification of the Nyquist theorem, saying that the sample rate must be greater than twice the information bandwidth, rather Chapter 4: The RF Undersampling Architecture 21

38 than twice the maximum frequency. This is expressed by equation 9, see [1]. EQUATION 9 f 2 f S > IF + where f IF is the intermediate frequency, f S is the sample frequency and BW is the signal bandwidth. The intermediate frequency is limited by the inequality in equation 10: EQUATION 10 BW f IF > 2 BW Downconversion By Undersampling Undersampling is a useful technique that can be used effectively in certain applications. The sampling device, in this case the T/H, will behave like a mixer in that it can take a high-frequency RF signal and produce an image of that signal at a lower frequency. In other words, it behaves like a down-converter, see [5]. Figure 2 shows the spectrum of an RF signal before undersampling. The RF signal is centered at 26 MHz with a bandwidth of 2 MHz. This signal is undersampled with a sample rate of 6 MHz. The resulting spectrum is shown in figure 4-6. FIGURE 4-5. FREQUENCY SPECTRUM BEFORE UNDERSAMPLING. f S FIGURE 4-6. DOWNCONVERSION BY UNDERSAMPLING. f S desired 22 Section 4.1: Architecture Overview

39 Image signals appear at 2 MHz, 4 MHz, 8 MHz, 10 MHz and so on. The original RF signal is periodically aliased on the frequency axis at frequencies defined by equation 11. EQUATION 11 f k = f RF k = 0,1,2,... k f S Each Nyquist region contains one alias of the original signal. The signal is mirrored in each multiple of half the sample frequency. All odd Nyquist zones contain a correct image of the original signal, whereas the frequency content in all even Nyquist zones is inverted, see [6]. It is now possible to select an identical image of the original RF signal at a much lower frequency, i.e. the undersampling has resulted in a downconversion of the RF signal. In the example above, the 2 MHz alias could be selected and digitally processed. 4.2 Advantages The RF undersampling architecture has many advantages over conventional radio architectures. The most important advantages are discussed in this section Less Analogue Processing Another key advantage of the RF undersampling architecture is the significant reduce of analogue components and analogue signal processing. This is possible due to the direct sampling of RF signals, which eliminates the following components IF filters IF gain stages Mixers High-frequency LO:s As the architecture has no IF stage, all corresponding filters and amplifiers can be removed. Further, as no mixer circuits are used, there is no need to generate high-frequency signals from the LO s. The elimination of all these circuits results in a substantial decrease of analogue component density and many problems related to these Chapter 4: The RF Undersampling Architecture 23

40 components no longer exist, such as LO-leakage, image-signal distortion and LO-jitter sensitivity. Compared with the superheterodyne architecture, especially the multi-stage variant, the difference in amount of analogue components is substantial. Analogue component density reduction and analogue processing have many advantages, such as: Increased flexibility Lower power consumption Area reduction IF off-chip filters removed Multiple Frequency Bands Because of the undersampling strategy and the wide T/H bandwidth, the RF undersampling architecture enables receiver designs with possibility to support multiple frequency bands and bands located at several GHz without using mixers. The functional diagram of a multi-band receiver using the RF undersampling architecture is shown in figure 4-7. FIGURE 4-7. FUNCTIONAL DIAGRAM FOR SUPPORT OF MULTIPLE RF BANDS. RF Band 1 T/H ADC RF Band N A certain RF band is supported by simply selecting the corresponding front-end. This selection could be performed manually or dynamically at run-time by the software. Depending on which bands to supports, it may be necessary to make the T/H clock frequency variable. The implemented receiver, which is not discussed in this report, supports two RF bands, the GSM900 uplink and downlink, which are manually selected. 24 Section 4.2: Advantages

41 4.2.3 Flexibility Since many tasks are moved from the analogue domain to the digital domain, the RF undersampling architecture offers much more flexibility than the mixer-based architectures. To simultaneously support different frequency bands, modulation schemes and so on, only the running software has to be changed. Several existing systems and services can be implemented in the same receiver and future standards may also be supported without changing the hardware platform. The possibility to reconfigure and extend the receiver functionality in a flexible manner is a very attractive property of the RF undersampling architecture. Thus, this architecture is a great step closer to the SDR receiver. 4.3 Noise Folding One disadvantage of the RF undersampling architecture compared with the architectures presented in chapter 3 is the decreased noise performance due to the phenomena called noise folding. Noise folding is extra serious in the RF undersampling architecture due the undersampling strategy and the wideband T/H. To understand the noise folding problem and why it exists, study the example in figure 4-8. FIGURE 4-8. SIGNAL SPECTRUM BEFORE NOISE FOLDING. f S FIGURE 4-9. SIGNAL SPECTRUM AFTER NOISE FOLDING. f S Chapter 4: The RF Undersampling Architecture 25

42 Assume the sampling frequency f S is 6 MHz and the desired signal is centered at 26 MHz with a 1 MHz bandwidth. This results in a downconversion of the desired signal to 2 MHz. However, all noise energy on the equivalent distance from all harmonics of the sample signal will also end up on 2 MHz and degrade the SNR ratio. The overall result is that noise folding increase the noise floor level of the entire output signal spectrum, as shown in figure SNR Degradation The SNR degradation due to noise folding by undersampling can be approximated by the following expression, see [3]: EQUATION 12 SNR = N + where S is the power density of the desired signal, N i is the in-band noise power density, N O is the out-band power density and m is the largest k that fulfils equation 13, see [2]. EQUATION 13 f S k B 2 where B is the sample device s analogue input bandwidth. The above expression assumes that all sample signal harmonics give rise to an equal amount of folded noise. The constant k determines how much noise will be folded into the desired signal s Nyquist zone. The larger k is, the more noise will fold onto the signal and decrease the SNR. Assume that the in-band noise power equals the out-band noise power. The SNR, and therefore also the noise figure, degradation in db due to noise folding can then be expressed as: EQUATION 14 i S ( m 1) No k 1 ( ) m SNR db log deg, =10 26 Section 4.3: Noise Folding

43 4.3.2 Sample Frequency Considerations According to equations 12 to 14, the SNR degradation is decreased by avoiding a low sampling frequency relative to the signal passband. A low sample frequency leads to more aliases and therefore noise will fold back into the desired band. Due to this, it is wise to choose the highest possible sample frequency that still undersamples the RF signal and down-converts it to the desired intermediate frequency. Figure 4-10 shows the theoretical SNR degradation versus sample frequency for three different T/H bandwidths. Notice that the noise power density is assumed to be constant over the entire T/H bandwidth. The in-band noise power density is assumed to be equal to the out-band noise power density. FIGURE MODELLED SNR DEGRADATION VERSUS SAMPLE FREQUENCY. 25 SNR Degradation (db) Bandwidth (GHz) Sample Frequency (MHz) The graph shows that doubling the sample frequency increases the SNR by 3 db. Chapter 4: The RF Undersampling Architecture 27

44 4.3.3 Front-End Gain The SNR degradation leads to a noise figure degradation by the same amount, which implies that the noise figure of an undersampling T/H is large. However, the cascaded noise figure and total receiver sensitivity can be kept relatively unaffected by providing enough front-end gain. Since the T/H is located after the front-end, the T/H noise figure is suppressed by the front-end gain, see section Assume the front-end noise figure is 7 db. This implies a front-end noise factor of approximately 5. The total noise figure is calculated using equation 15. EQUATION 15 NF tot FT / H 1 = FT / = 10 log10 F + + front end 10 log 10 5 G front end G H front 1 end 28 Section 4.3: Noise Folding

45 The graph in figure 4-11 shows the total receiver noise figure as a function of the T/H noise figure and the front-end gain. The frontend noise figure is assumed to be 7 db. FIGURE TOTAL NOISE FIGURE VERSUS T/H NOISE FIGURE AND FRONT- END GAIN. Total Noise Figure (db) Front-End Gain (db) T/H Noise Figure (db) For front-end gains above 40 db, the total noise figure is approximately constant (7 db) for a T/H noise figure between 10 db and 40 db. The T/H noise figure doesn t really affect the total noise figure at all for a normal frant-end gain. If the front-end gain is decreased, the T/H noise figure becomes much more important, as the graph illustrates Further Reduction Of Performance Loss The performance loss due to noise folding does not only depend on the sample frequency. It also depends directly on the following factors: Stop-band attenuation Chapter 4: The RF Undersampling Architecture 29

46 T/H bandwidth and noise performance Clock quality The amount of folded noise can be reduced by using high-quality band-select filters before sampling. The RF bandpass filter is an important component since its purpose is to attenuate out-band noise before downconversion. Due to the nature of noise folding, it is especially important that the filter provide enough attenuation over the entire T/H bandwidth, rather than it has sharp passband edges. From figure 4-12 we see that if the out-band noise can be attenuated to a certain level below the in-band noise power, the SNR degradation due to noise folding is reduced to approximately zero. For smaller attenuation factors, a 1 db attenuation of out-band noise compared to in-band noise implies a 1 db SNR improvement. The in-band noise power density is -100 dbm, the analogue input bandwidth is 9 GHz and the input signal power is -50 dbm. FIGURE MODELLED SNR DEGRADATION DUE TO NOISE FOLDING VERSUS DIFFERENCE BETWEEN IN-BAND AND OUT-BAND NOISE POWER DENSITY. SNR Degradation (db) Sample Frequency (MHz) N in-band - N out--band (db) 30 Section 4.3: Noise Folding

47 However, certain noise sources cannot be filtered out by the bandselect filters, such as: Switching noise Thermal noise Quantization noise (for ADC) Quantization noise and thermal noise are both of wide-band nature and will always alias to the desired band. Therefore, also the T/H circuit s own noise performance is important to reduce loss due to noise folding. Also, the T/H bandwidth should not be unnecessary wide Clock Noise Sampling clock aperture jitter shows up as input noise. If the jitter is white, also the signal will show a white noise floor which is included in the noise folding. The SNR due to jitter depends on the sample frequency according to equation 16. EQUATION 16 SNR j f = f where f in is the input signal frequency in Hz and SNR clk is the signalto-noise ratio of the sample clock. Again we see that a high clock frequency is preferable. If the clock noise is dominating the total T/H noise, the clock frequency choice becomes very important. The SNR due to aperture jitter for a full-scale input signal is always limited by: EQUATION 17 SNR j clk in 2 20log SNR clk ( 2πf t) in where t is the standard deviation aperture jitter in seconds. The maximum allowed aperture jitter depends on the resolution of the ADC following the T/H. To ensure that the T/H jitter does not Chapter 4: The RF Undersampling Architecture 31

48 degrade the ADC SNR performance, the jitter must fulfil the following inequality: EQUATION 18 t 1 6π f in 2 N 4.4 Harmonics Aliasing Figure 4-13 shows the T/H output spectrum of the GSM900 downlink band (925 MHz MHz) after undersampling with clock frequency MHz. According to undersampling theory, the first Nyquist band (0 MHz to MHz) will contain the following alias: Downlink alias (105.8 MHz MHz, a 1 in figure) whereas the second Nyquist band (409.6 MHz to MHz) will contain the following alias: Frequency-mirrored downlink alias (678.4 MHz to MHz, a 2 in figure) FIGURE EXPECTED T/H OUTPUT SPECTRUM FOR GSM DOWNLINK. f s /2=409.6 f s = GSM900 Downlink 0 a 1 a MHz The ADC samples this signal with a sample frequency of MHz. This leads to that a 1 is mirrored in f s /2 so that another alias is created at 64 MHz to 99 MHz (a 3 in the figure 4-14). The two aliases a 1 and a 3 are periodically repeated by the sample frequency, so that each ADC 32 Section 4.4: Harmonics Aliasing

49 Nyquist region contains exactly one alias of the original downlink signal. The a 1 alias is digitally selected and processed. FIGURE EXPECTED ADC OUTPUT SPECTRUM FOR GSM DOWNLINK. f s /2=102.4 f s = GSM900 Downlink 0 a 3 a 1 a MHz However, the spectrum response above does not take non-linearity effects into account. In reality, the T/H circuit will give rise to harmonics and spurious signals causing distortion when sampled by the ADC. Figure 4-15 illustrates how the second-order harmonics of the desired signal at the T/H output will alias during ADC sampling and interfere with the desired band. I call this problem harmonics aliasing. FIGURE ALIASING OF SECOND-ORDER HARMONICS. f s/2=102.4 f s= nd Harmonics 0 Distortion MHz In this example, the desired band is located between MHz and MHz. The second-order harmonics of this band are shown in the figure and located between MHz and MHz. When this spectrum is sampled by the ADC, the second-order harmonics are mirrored in MHz so that the desired signal is distorted by aliased harmonics. There are two possible solutions to the problem of harmonic aliasing: Low-pass filtering Changing sample frequencies Chapter 4: The RF Undersampling Architecture 33

50 4.4.1 Low-Pass Filtering The most effective solution to aliasing of harmonics and spurious signals is to low-pass filter the T/H output. In this way, the harmonics and spuriouses can easily be attenuated. In the example above, the filter should have a cut-off frequency at about f c = 150 MHz, see figure FIGURE ELIMINATION OF HARMONICS ALIASING BY LOW-PASS FILTERING. f s /2= f c =150 f s = MHz However, filtering is not a desirable solution. By placing a filter between the T/H and the ADC, the possibility to support multiple bands is drastically decreased. The filter makes it more difficult to find an appropriate T/H sampling frequency and the filter bandwidth limits the set of supported RF bands Changing Sample Frequencies Harmonics aliasing may also be solved by changing the sample clocks frequencies. In the GSM900 downlink example above, increasing the ADC clock from MHz to MHz would eliminate aliasing of the second-order harmonics into the desired band, see the figure below. FIGURE CHANGING CLOCK FREQUENCY MAY SOLVE HARMONICS ALIASING. f s /2=153.6 f s = nd Harmonics MHz 34 Section 4.4: Harmonics Aliasing

51 However, changing the sample frequency is probably not generally valid. Also, harmonics other than the second-order ones may cause interference instead. 4.5 T/H and ADC Integration Considerations Sample Clocks Frequencies The result of the T/H and ADC integration is that the signal is sampled twice before being digitized. It is first undersampled by the T/H and then Nyquist sampled by the ADC. It is therefore important to have a clear frequency plan to minimize performance loss due to spurious signals and alias distortion. Thus, the T/H clock frequency choice depends on the ADC clock frequency and vice versa, as well as on the RF bands of interest. Therefore, the first design question concerning the RF undersampling architecture to answer is the choice of the T/H and ADC clock frequencies. The T/H and ADC used in this thesis to evaluate the RF undersampling architecture have clock frequencies of MHz and MHz, respectively Clocks Phase Difference Another important question is how the phase of the ADC clock relative to the T/H clock affects the performance. The reason for this is in the basic function of a T/H circuit. When the T/H samples a signal, it starts charging or discharging a capacitive load until the voltage over that load equals the sample voltage, see figure FIGURE T/H OUTPUT AND ADC SAMPLING. CLK2 T/H2 Output Acquisition Interval Invalid ADC Sampling Point Ideal ADC Sampling Point There is a risk that the ADC samples the T/H output signal before the signal has reached the correct voltage level. It is also possible that Chapter 4: The RF Undersampling Architecture 35

52 that the signal frequency at the sampling point is not within the ADC s bandwidth, leading to an invalid output. Therefore, it is important that the ADC clock samples the T/H output during the acquisition interval shown in figure Section 4.5: T/H and ADC Integration Considerations

53 5 Measurement Results All measurements performed to evaluate the RF undersampling architecture are presented in this chapter. The measurement results are analyzed and then compared with the modelled results. 5.1 Measurements Setup The T/H Circuit The circuit chosen to perform the undersampling and downconversion of the RF signals is the RTH010 track-and-hold from Rockwell Scientific. The RTH010 is suitable for undersampling applications due to the following reasons: 9 GHz full-scale range bandwidth (small signals) Wide range of clock frequencies Provides a held output for more than a half clock period, relaxing bandwidth requirements of the subsequent ADC Independent clocking of the two T/H circuits (as low as 100 MHz) FIGURE 5-1. RTH010 FUNCTIONAL DIAGRAM. CLK1A CLK1B CLK2A CLK2B TMS BUF 1 BUF 2 INP INN T/H1 T/H2 OUT- BUF OUTP OUTN The RTH010 has differential input-, output and clock signals and cascades the two internal T/H circuits. The first T/H is optimized for dynamic range, bandwidth and jitter, whereas the second T/H is Chapter 5: Measurement Results 37

54 optimized for noise and low gain loss. The most important parameter specifications of the RTH010 T/H are listed in table 1. TABLE 1: CENTRAL SPECIFICATIONS OF THE RTH010 TRACK-AND-HOLD Parameter Note Typical Value Input Bandwidth Clock Frequency Harmonic Rejection Ratio (Worst Harmonic) -3 db Gain, < 0.1 Vpp -3 db Gain, 0.5 Vpp -3 db Gain, 1 Vpp CLK1 (T/H1) CLK2 (T/H2) 1020 MHz, 1 Vpp Input 1020 MHz, 0.5 Vpp Input Integrated Noise Input Referred, Hold Mode, 500 MHz clock Integrated Noise Full Scale Range Input Referred, Track Mode, 500 MHz clock 9 GHz 8 GHz 6 GHz MHz MHz 60 db 65 db 550 µv 400 µv 1000 mvpp Input Resistance Each Lead to Ground 50 Ohm Output Swing 50 Ohm Input Resistance, 1 Vpp Input 0.8 Vpp Figure 5-2 shows a close-up of the T/H board, with the RTH010 circuit in focus. The T/H board was not designed in this thesis. Instead 38 Section 5.1: Measurements Setup

55 a complete evaluation board from the T/H vendor, with the T/H already mounted, was used. FIGURE 5-2. CLOSE-UP OF THE T/H PCB T/H Measurements Setup To measure the RTH010 performance and evaluate the RF undersampling, the setup shown in figure 5-3 was used. FIGURE 5-3. T/H MEASUREMENTS SETUP. Clock Generator Signal Generator Two-way 180 Splitter Two-way 180 Splitter Power Splitter Power Splitter T/H PCB Spectrum Analyzer Hybrid Junction PCB Chapter 5: Measurement Results 39

56 The Hewlett Packard 8648C signal generator generates a GSM900 signal, which is made differential by a 180 splitter before being applied at the T/H input. The clock is generated by the Rhode & Schwarz SMY 01 signal generator. First, the clock signal is split into a 180 differential signal to support the T/H differential clocking. These two signals are then power splitted into two signals each, making a total sum of four clock signals - CLK1A, CLK1B, CLK2A and CLK2B. This allows for out-of-phase clocking of the TH1 and TH2 internal T/H circuits, which is the clocking scheme used in all tests, see figure 5-4. FIGURE 5-4. TH1 AND TH2 OUT-OF-PHASE CLOCKING. The differential T/H output is terminated, AC coupled and made single-ended by the hybrid junction board. The hybrid junction output is then analyzed by a spectrometer T/H And ADC Integration Measurement Setup The ADC is placed on a PCI-based daughterboard called MP4. Except from digitizing the analog signal, the MP4 board also performs digital signal processing and transfers the digital data to software running on the local PC machine. 40 Section 5.1: Measurements Setup

57 The ADC performance was measured by logging the digital signal via the PCI bus using a software program running on the local PC. FIGURE 5-5. THE MP4 PCI CARD MOUNTED IN A PC. When the clock frequencies were decided and phase difference measurements were completed, the clock distribution shown in figure 5-6 was decided to be used. A clock with frequency f S,TH = MHz is generated by a local oscillator. This clock is then split into two paths, where the ADC clock frequency is divided by 4, so that f S,ADC = f S,TH /4 = MHz. FIGURE 5-6. T/H AND ADC CLOCKING. T/H ADC MHz MHz LO Frequency Divider (4x) Chapter 5: Measurement Results 41

58 5.2 T/H Measurement Results Downconversion The downconversion effect of undersampling was confirmed using a continous 940 MHz (GSM900 downlink) input signal and a MHz clock. Figure 5-7 shows the T/H output spectrum from DC to 3 GHz. Observe that the increasing attenuation by frequency is caused by the hybrid junction, which has a bandwidth of only 500 MHz. FIGURE 5-7. T/H OUTPUT SPECTRUM CONFIRMS DOWNCONVERSION BY UNDERSAMPLING. Down-Converted Signal Input Signal Clock Frequency 1 st Nyquist 2 nd Nyquist 3 rd Nyquist As the spectrum shows, each nyquist region contains exactly one alias of the original input signal, where the aliases are mirrored in half the sample frequency and in each multiple of it. The signal marked Down-Converted Signal is located in the first nyquist region at ( ) MHz = MHz and is the desired signal. The weaker signals (-55 dbm and below) located in the first nyquist region are harmonics of the desired signal and aliased harmonics of the input signal, see section for more details. 42 Section 5.2: T/H Measurement Results

59 5.2.2 Noise Folding In the previous chapter, it was found that the SNR degradation due to noise folding is directly proportional to the sample frequency and the T/H analogue input bandwidth. To evaluate this, two tests were performed. In the first test, the continous 940 MHz signal was undersampled by a clock with frequency identical to the ADC clock frequency, that is, MHz. The output spectrum of the GSM downlink band in the first nyquist region is shown in figure 5-8. FIGURE 5-8. T/H OUTPUT SPECTRUM FOR GSM DOWNLINK SIGNAL IN FIRST NYQUIST ZONE WHEN SAMPLE FREQUENCY IS MHZ. The first Nyquist region alias of the 940 MHz signal is located at 84 MHz, as expected. f IF = = 84 MHz As seen by the spectrum above, the noise floor within the specific region is located at about -101 dbm. Notice that the resolution band- Chapter 5: Measurement Results 43

60 width of the spectrum analyzer is 1 khz, which would imply a noise power density of approximately -131 dbm/hz: ( 1000) = 131dBm Hz N = log / In the second test, the clock frequency was increased four times to MHz.. According to the calculations in section 4.3.1, this would imply a 6 db improvement of the noise floor level: ( 4) db SNR = 10log 6 deg = The new output spectrum is shown in figure 5-9. The noise power density is now decreased from -131 dbm/hz to approximately -137 dbm/hz: ( 1000) = 137 dbm Hz N = log / That corresponds to a 6 db improvement. FIGURE 5-9. T/H OUTPUT SPECTRUM FOR GSM DOWNLINK SIGNAL IN FIRST NYQUIST ZONE WHEN SAMPLE FREQUENCY IS MHZ. 44 Section 5.2: T/H Measurement Results

61 Next, SNR measurements were performed for nine different sample frequencies from 200 MHz to 1000 MHz. Figure 5-10 shows the modelled SNR degradation (dashed line) and the measured SNR degradation (solid line) using the spectrum analyzer. FIGURE MEASURED SNR DEGRADATION VERSUS. SAMPLE FREQUENCY. 21 SNR Degradation (db) Modelled Measured Sample Frequency (MHz) The measured results follows the logarithmic behaviour relatively well. Thus, the relationship between sample frequency and noise figure degradation seems to be true. However, the measured values are about 4 db less than the modelled values over the entire range of sample frequencies. One possible reason for this is that the model assumes that all aliases will contribute with the same amount of noise, which may not be the case. Chapter 5: Measurement Results 45

62 5.2.3 Noise Figure The T/H noise figure was measured by calculating the difference between the input noise power density and the output noise power density and then adding the gain to this value, see equation 19. EQUATION 19 NF = SNR input SNR output = S output = S input + Gain = N output N input Gain By figure 5-9 we saw that the output noise power for a MHz sample clock is approximately -137 dbm/hz. The input power density (at 940 MHz) was measured to approximately -150 dbm/hz. The signal gain through the entire measurement setup is -9 db. Therefore, the noise figure for the given sample frequency and input frequency is 22 db: EQUATION 20 ( 120) ( 9) db NF = 107 = 22 However, a certain amount of the input noise measured by the spectrum analyzer is generated by the spectrum analyzer itself. The true input signal noise power density may be as low as -160 dbm/hz. The noise figure could therefore be approximately 10 db greater than 22 db. However, as shown in section 4.3.3, the T/H noise figure really doesn t affect the total noise performance of the typical RF receiver, since the front-end gain is often large enough to suppress the T/H noise figure. Also, the exact value of 22 db is not that important. Instead, the important conclusion from the measurement is that the noise figure is significantly higher than the typical noise figure of a mixer circuit, which is approximately 10 db Harmonic Distortion A high clock frequency also reduce the in-band harmonic distortion. By selecting a clock frequency in an intelligent manner, it is possible to ensure that all signal harmonics fall outside the frequency band of interest. 46 Section 5.2: T/H Measurement Results

63 Figure 5-11 shows the spectrum of the first Nyquist region of a 955 MHz signal sampled by a MHz clock. The worst (second) harmonic is located in-band (about 2 MHz from desired signal) and therefore it cannot be filtered out. The second-order and third-order harmonic distortion rejection ratio is approximately 48 db and 50 db, respectively, for the present input signal strength. This is not as good as the data-sheet specification, but still acceptable. FIGURE T/H OUTPUT HARMONICS WHEN SAMPLE FREQUENCY IS MHZ. The noise floor is set by the source and the spectrum analyzer. Chapter 5: Measurement Results 47

64 However, if the clock frequency is increased to MHz, all harmonics are located outside the desired band, see figure Notice that the frequency range is DC to MHz. FIGURE T/H OUTPUT HARMONICS WHEN SAMPLE FREQUENCY IS MHZ Two-Tone Intermodulation Distortion The RTH010 data-sheet does not specify two-tone intermodulation distortion. Therefore, to measure this, two input signals were combined and applied at the T/H input. The signal frequencies were 940 MHz and 941 MHz, both with a signal strength of -5 dbm. The output spectrum shown in figure 5-13 is for a MHz sample frequency. The noise floor is set by the source and the spectrum analyzer. As seen by the figure, the third-order IMD products appear at the expected frequencies, that is, MHz and MHz. They both have a power of -60 dbm, whereas the two main signals are -15 dbm. The 10 db loss is mainly due to the cables and the hybrid junction 48 Section 5.2: T/H Measurement Results

65 board. The third-order intermodulation distortion rejection ratio is - 15 dbm - (-60 dbm) = 45 db. FIGURE TWO-TONE INTERMODULATION DISTORTION. The output third-order intercept point is 7.5 dbm.: RR3out 45 OIP3 = P + = 15+ = out 5 dbm The exact value of OIP3 is not that important. The main purpose of this measurement was to roughly compare the intercept point between this T/H circuit and the typical mixer IP3, which is approximately equal to the measured value. 5.3 T/H And ADC Integration Measurement Results Clocks Phase Difference Since the T/H and the ADC are located on separate boards, it is very difficult to control the clock phase difference. However, all tests have Chapter 5: Measurement Results 49

66 shown that the problem described in section is unlikely to appear. The main reason for this is probably that the T/H circuit s rise time is very small relative to the ADC clock period. In future implementations of the RF undersampling architecture it is recommended to have the T/H and the ADC on the same board so that the clock phase can be controlled Spectrum Response The T/H input signal frequency is 955 MHz and the T/H sample frequency is MHz. The T/H output spectrum from DC to 1 GHz measured by the spectrum analyzer is shown in figure FIGURE T/H OUTPUT SPECTRUM DC - 1 GHZ. Signal Aliases Input Signal Alias Harmonics Input Signal Harmonics (Aliased) Two aliases of the input signal are generated at MHz and MHz. The second- and third-order harmonics of the low-frequency alias are labeled Alias Harmonics. Also, the harmonics of the 955 MHz input signal are aliased down to the second Nyquist zone. As shown, the spectrum of the first and second Nyquist zones are filled with non-desired signals, such as harmonics, aliased harmonics and one signal alias. When the signal above is sampled by the ADC with a sample frequency of MHz, some of the non-desired signals will alias into the desired band. 50 Section 5.3: T/H And ADC Integration Measurement Results

67 The ADC output signal was logged and its FFT was computed and plotted using Matlab. The resulting spectrum is shown in figure By studying this spectrum, it is clear that some of the non-desired signals have aliased into the desired band, for example the secondand third-order harmonics of the MHz ADC input signal. These are marked with the two arrows in figure FIGURE ADC OUTPUT SPECTRUM dbc MHz Please notice that the distortion is more worse than it appears to be by the spectrum above due to the unintentional attenuation of nondesired signals caused by the hybrid junction Spectrum Response With Intermediate Filtering From the last chapter it was found that low-pass filtering the T/H output should reduce the total harmonic distortion. To evaluate this, the previous measurements were performed again, but now with a 150 MHz low-pass filter placed at the hybrid junction output. Chapter 5: Measurement Results 51

68 The filtered T/H output spectrum is shown is figure As seen, the filter removes the majority of the non-desired signals shown in figure FIGURE LOW-PASS FILTER OUTPUT SPECTRUM DC - 1 GHZ. The reduction of non-desired harmonics and aliases, compared to the non-filtered case, implies that the ADC output distortion is decreased. Figure 5-17 shows the FFT spectrum of the ADC output. By comparing this spectrum with the spectrum in figure 5-15, it is clear that the distortion rejection is reduced. For example, the third- 52 Section 5.3: T/H And ADC Integration Measurement Results

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