THE DYNAMIC THRESHOLD VOLTAGE MOSFET

Transcription

1 THE DYNAMIC THRESHOLD VOLTAGE MOSFET F. Javier De la Hidalga-W. 1,2 and M. Jamal Deen 1 1 Electrical and Computer Engineering, McMaster University, Hamilton, Ontario, Canada L8S 4K1 jamal@ece.eng.mcmaster.ca, javier@crlipc.eng.mcmaster.ca 2 Instituto Nacional de Astrofísica, Óptica y Electrónica, INAOE, P.O. Box 216 & 51, Z.P , Puebla, México jhidalga@inaoep.mx Abstract In this contribution, the development of the dynamic threshold voltage (DT) MOSFET is reviewed. The forward-biasing of the source-substrate junction was proposed for the first time in 1984 as part of an early strategy to improve the MOSFET performance when scaled. This led to the design of a quarter-micron technology, operating at 77 K, using a 0.6 V voltage supply and with the substrate connected to a fixed forward-biasing potential. Ten years later, the operation of the gate controlled lateral bipolar transistor (GC-LPNP) and the SOI MOSFET with the substrate tied to the gate terminal, both operating as dynamic threshold devices, were demonstrated. The SOI DTMOS was the best alternative for ultra low power CMOS applications and the GC-LPNP was used for some compact low power analog circuits. Aggressive technological improvements led to successful fabrication of bulk DTMOS, whose current representatives show impressive figures of merit regarding gate delay-power consumption products, well above those of conventional CMOS. I Introduction The age of mobile and portable electronics has developed rapidly during the last few years. As a consequence, there has been an increasing demand for high performance and low power digital circuits. Earlier portable electronic systems, such as calculators and digital watches, required modest performance. However, today s most popular applications such as wireless communication and portable computers require the highest performance in terms of speed at low power consumption. The portability of these recent systems limits the size and weight of the battery that ultimately determines their economic viability, and this imposes severe constraints on their power consumption. CMOS is still the leading semiconductor technology able to fulfil such demanding requirements. Standard CMOS technologies are, however, reaching their limit since the technological reduction of threshold voltage (V TH ) necessary for low voltage/low power operation, leads to a degradation of the subthreshold current. The dynamic power consumption in CMOS gates is given by P = 2 C L V DD, (1) where C L is the total load capacitance, V DD is the power supply voltage and f is the average operating frequency of the gate. Therefore, the most effective way to reduce the power consumption while maintaining high performance is by reducing the supply voltage. This approach, however, must be accompanied by the scaling of the threshold voltage since reducing V DD below ~3 V TH will importantly degrade the switching speed of the gate. On the other hand, the technological scaling of V TH normally leads to a degradation of the MOSFETs subthreshold characteristics. This increases the stand-by current in static circuits and may produce failures in dynamic circuits, thus imposing a lower limit for V TH of ~0.4 V. The most recent approach proposed to overcome such constraints, namely the operation at very low V DD and low V TH with steep subthreshold characteristics, is to tie the gate to the substrate in order to operate the device as a dynamic threshold voltage MOSFET (DTMOS). In this configuration, the gate input voltage forward biases the substrate, and because of the well known body effect, V TH will decrease for the MOSFET in the on-state. The characteristics of the non-scaled- V TH MOSFET (the conventional MOSFET with a steep subthreshold slope) is maintained when the device operates in the off-state since the gate voltage input will be zero. The forward-biasing of the substrate to reduce V TH was proposed for the first time as a part of an early strategy for scaling MOSFETs for operation at 77 K [1]. Thus, this contribution starts discussing such approach even though those MOSFETs were not true dynamic threshold devices. The different versions of real DTMOS are presented and discussed in Sec. III. The bipolar counterpart, BJT devices that make use of a MOS-like gate to improve the current gain, and thus involving the operation of a DTMOS, is briefly presented in Sec. IV for completeness. Finally, the first f Proc. Second IEEE Int. Caracas Conf. on Devices, Circuits & Systems (ICCDCS ), Cancun, Mexico (15-17 March 2000).

2 attempts for characterizing and modelling the DTMOS are presented in Sec. IV. II Forward biasing the source-substrate junction In the early 70 s, the miniaturization limits of MOSFETs were the subject of several investigations. The drain-source punch through and the gate-oxide breakdown were identified as the most important limiting factors in 1972 [2]. At that time, the channel implant for adjusting V TH led to a further flexibility in device design, since better trade-offs between drain-induced barrier lowering and substrate sensitivity were achieved. In the same year, the well known conventional scaling theory was presented [3], and a systematic approach for the design of small MOSFET was used. According to this theory, the physical dimensions and applied potentials must be scaled by the same factor, while the impurity concentration is increased by the reciprocal of such factor. The electric field conserved the shape and distribution and two dimensional effects such as punch-through, and V TH sensitivity to channel length and drain voltage remained under control. Such criteria led to the successful fabrication of the first 1-µm MOSFET based on the scaled behaviour of longer devices [4]. In 1984, Baccarani et al. [1] identified the limiting factors of the conventional scaling theory that prevented its application for scaling in the submicrometer regime: 1) The temperature dependence of V TH, which led to a large threshold fluctuation for an extended operating temperature range. This dependence was mainly due to the variation of the substrate Fermi level with temperature. 2) The non-scalability of the junction built-in potential, leading to a larger depletion width and worsening of the short channel effects. These two considerations called for V DD and V TH not to be reduced to such low values as those dictated by the conventional scaling. Hence, a new generalized scaling theory was developed, allowing for the local field to increase though conserving the shape of the electric field and potential distributions within the scaled device [1]. The physical dimensions and the applied voltages were thus scaled by independent factors giving a higher design flexibility and controlling the short channel effects. These new guidelines were used to design a 0.25 µm-mosfet for operation at room temperature and at 77 K. As an integral part of the strategy used for designing the low temperature version of this MOSFET, the forward biasing of the substrate was proposed as a mean for scaling V TH. In this way, short channel effects were avoided and the sensitivity of V TH to the channel length was reduced. The optimum choice for the substrate bias was V DD =0.6V, which was low enough as to be applied directly to the substrate contact without injecting a significant amount of substrate current. In this way, the use of a second voltage supply was also avoided. The resultant bias-scaled threshold was V TH = 0.15 V. Soon after the publication of this scaling theory, Sai-Halasz et al. [5] used such scaling guidelines and presented the first experimental results of a 0.1-µm MOSFET technology for operation at 77 K. Since at such short channel lengths, the carriers are more likely to travel at their saturation velocity, then the increase of power, i.e. V DD, is not accompanied by an increased performance. Hence, the low voltage operation at V DD = 0.6 V and a bias-scaled V TH = 0.15 V are well suited to improve the devices performance. These researchers also concluded that even though there were no fundamental obstacles for the design of a room temperature 0.1-µm MOSFET technology, a worthwhile performance would be obtained only for low temperature operation. The forward biasing of the substrate at 0.6 V allowed for the scaling of the depletion region without introducing a substantial substrate leakage current at 77 K. The output characteristics of the MOSFETs obtained are shown in Fig. 1. FIGURE 1: Output characteristics of a) 0.16 µm gate length, and b) 0.1 µm gate-length MOSFETs located on the same wafer. Gate voltage increments are in 0.1 V steps up to 0.8 V. Substrate bias is 0 and 0.6 V at 300 K (dashed lines) and 77 K (solid lines), respectively. Taken from [5].

3 Following the same reasoning, Yamamoto et al. [6] proposed a new CMOS structure for low temperature operation with a forward-biased substrate. In contrast to [1] where p- and n-well were connected to V DD and ground, respectively, the substrate of the entire CMOS structure was connected to V DD /2 while keeping both wells on the top surface of the substrate short-circuited, as shown in Fig. 2. The intent of this approach was to increase the gate speed since a higher value for the voltage supply was allowed, V DD =1.5 V. No penalty in area was assessed and low-power, high-speed operation was obtained by using a 0.4-µm technology. Some results are shown in Fig. 3 for a 51-stage ring oscillator operating conventionally and with a forward biased substrate at 300 K and 77 K. In 1993, Matsumoto [7] discussed the evolution of the CMOS VLSI performance until the year As shown in Fig.4, 77 K-CMOS has an edge over the 300 K-CMOS of about five years; the limit marked in that figure will be due to hot carrier degradation. According to this author, the success of the 77 K technology will be due to the possibility of effectively scaling V TH, by means of more aggressive technological improvements such as in engineered source/drain and/or channel profiling, or by forward-biasing the substrate. FIGURE 2: Schematic cross section of the CMOS inverter with a local well contact. The same forward substrate bias is applied to both wells with a single voltage supply of V DD /2. Taken from [6]. FIGURE 4: Evolution of CMOS VLSI performance operated at room and liquid nitrogen temperatures. Taken from [7]. III The dynamic threshold voltage MOSFET A true DTMOS was presented for the first time in 1994 for applications at 300 K, operating at V DD =0.6 V and fabricated with a SOI technology [8]. In contrast to the above-mentioned approaches, the gate was tied to the substrate, thus allowing the substrate voltage to vary with the input gate voltage. As was pointed out by the authors, SOI technology was well suited for this applications for the following reasons. 1) Reverse-biased junction is not needed for device insulation in a digital SOI CMOS IC. 2) SOI provides smaller junction areas than those of bulk technology, thus lower capacitances and substrate parasitic currents are achieved. FIGURE 3: Propagation delay vs. power dissipation per channel width at 1 GHz. The forward biasing of the substrate improved the performance of the conventional CMOS structure. Taken from [6]. CMOS inverters built with this DTMOS approach were operational at voltages as low as 0.2 V; however, the higher performance was achieved at 0.6 V. This DTMOS presented several drawbacks, as a high bulk resistance that introduced long RC delays for wiringdominated gate propagation delay. Improvements to this device were published in 1996 [9], where parasitic

4 capacitances were minimized by engineering the lateral doping, and the sensitivity of V TH ( V TH ) to substrate voltage was increased by retrograde- or counter-doping the channel. This V TH has to be maximized for improved performance. However, an increase of V TH by increasing the body-effect parameter (by increasing the substrate concentration) also produces an undesirable increase of V TH. Thus, a trade-off between V TH and V TH was established in terms of the depletion width [9], x dep, and the gate oxide thickness, t ox, and it is time of 83.6 psec at 0.6 V operation and psec at 0.5 V operation. V TH 3t ox = V DD x dep. (2) The scaling of x dep by profiling the channel also improved the short channel effects, but it had a detrimental effect on the subthreshold slope in the conventional MOSFET. Fig.5 shows the MEDICI simulated performance of a two-input NAND gate with an inverter as its load by using this DTMOS [10]; this performance is compared to that of conventional MOS gates. FIGURE 6: Schematic cross section of a bulk dynamic threshold voltage MOSFET with trench isolation and gate/shallow-well connection using SICRON-salicide. Taken from [11]. Although B-DTMOS solved the RC-body delay drawback of DTMOS, it presented large junction capacitances that degraded the high speed operation of logic gates. This was overcome by the development of the low capacitance sidewall elevated drain dynamic threshold voltage MOSFET (LCSED-DTMOS), also implemented in bulk technology [12]. In this device, sidewall elevated drain structure was applied to the earlier B-DTMOS to reduce the junction capacitances. As shown in Fig. 7, the elevated structure of the drain and source enhances the effective surface area necessary to make contact to such regions. On the other hand, the extension of these junctions in the substrate is reduced to only 2/3 of the gate length. Even though this structure effectively reduces the junction capacitances, it increases the capacitance between gate and source/drain. FIGURE 5: Predicted performance for logic DTMOS gates as compared to conventional MOS counterpart. Taken from [10]. The long RC delay of gate to body signal transmission present in the SOI DTMOS was overcome by using a bulk (B) based CMOS technology for designing the B-DTMOS [11]. To achieve low V TH and reduction of the body resistance simultaneously, a layered shallow well structure in which a high concentration layer was sandwiched by low concentration layers was used in B- DTMOS, as shown in Fig. 6. Advanced silicidation process achieved very low metal to source/drain and gate contact resistances, resulting in a propagation delay FIGURE 7: Schematic cross section of the LCSED- DTMOS. Taken from [12]. The sidewall elevated source and drain were fabricated by polysilicon deposition using an oxygen free

5 load-lock LPCVD system and subsequent etch-back after the gate formation. This structure also overcame the large occupation area presented by B-DTMOS, reducing it to 60% of its original value. The added capacitances, however, were too small to affect the high speed performance of the logic gates obtained with this technology. The figure of merit of power consumption versus speed, comparing equivalent gates built with B- DTMOS to conventional CMOS technologies are shown in Fig.8. The superiority of this new structure compared to that of the conventional technology is impressive: the power consumption when switching at 8 GHz is only 1/50 of the required by conventional MOS- FETs for operation at V DD = 0.5 V. substrate) this BJT is off. However, when the substrate is forward biased at voltages well above 0.6 V, the bipolar effect will come into the picture. Most injected carriers from the source will be collected by the drain terminal; some will be recombined in the substrate. Thus the GC-LPNP operates similarly to DTMOS; nevertheless, in this case, the forward biasing of the sourcesubstrate (emitter-base) junction can be high so that the bipolar current dominates the MOS-channel current. It is worth mentioning the very high values of current gain achieved by dynamically modulating the base of GC- LPNP through an MOS gate. An example of this is shown in Fig. 9 where current gains of more than 10 6 are possible. IV Other versions of DTMOS and related devices In the field of dynamic threshold MOSFETs, it is possible to find some variations of the above mentioned devices. Nevertheless, these kind of devices were intended to operate dynamically but without the restrictive low values of V DD imposed by the forward-biasing the source-substrate junction in DTMOS, whose main goal was to precisely obtain devices for ultra low power operation. In [13] a subsidiary transistor is connected to the primary one in order to keep the substrate voltage below 0.6 V when a higher voltage supply is used. FIGURE 9: Experimental β F vs. V E curves of the GC- LPNP BJT device. V B = 0V and V G is varied from -0.4V to 0.4V for both cases. V Characterization and modelling FIGURE 8: Power consumption of LCSED, B-DTMOS and conventional MOSFET as a function of propagation speed, where τ represents the propagation delay. Taken from [12]. A closely related device is the gate-controlled lateral PNP bipolar transistor (GC-LPNP) [14-18] which exploits the extra current coming from the MOS transistor embedded in its structure. Any MOSFET has an intrinsic BJT associated structurally with it; under normal MOS operating conditions (reverse or zero biased In spite of the growing importance of the DTMOS, little attention has been paid to the correct modeling and characterization of its electrical behaviour. Regardless of the lack of physical justification, the conventional MOSFET circuital model has been used to predict the response of DTMOS [10]. It has to be noted that the circuit model of a MOSFET is based on the depletion approximation that may be violated by the presence of a high density of free carriers due to the forward biasing of the substrate. It has been proven, however, that the well-known long channel model for the threshold voltage is still valid for a forward bias as high as 0.5 V, different values of surface potential, and for temperatures in the 77 K-300 K range [19]. Fig. 10 shows the measured and expected values of V TH for a wide temperature

6 range and both polarities of the substrate bias. The expected values were calculated by using the long channel V TH model. As it is also pointed out in [19], such a model is valid as long as the density of free carriers in the depletion region remains negligible in comparison to the doping concentration; this is unlikely to occur at voltages above 0.5 V or close to the built-in potential. In the event that a higher carrier density occurs in the depletion region, the total amount of charge will increase, thus disturbing the potential distribution along the channel and a more generalized MOSFET model is needed. true DTMOS was obtained. This device evolved to the present and it shows very impressive figures of merit for applications at room temperature and for ultra low power. The modeling and electrical characterization of DTMOS are still in their early stage and more research is expected in the near future. VII Acknowledgments This work was partially supported by Micronet, a federal network centre of excellence in microelectronics, Canada, NSERC of Canada, and CONACyT, Mexico. VIII References [1] G. Baccarani, M.R. Wordeman and R.H. Dennard, Generalized Scaling Theory and its Application to a 1/4 Micrometer MOSFET Design, IEEE Trans. Electron Dev., Vol. ED-31, No. 4, (1984). [2] B. Honeisen and C.A. Mead, Fundamental Limitations in Microelectronics-1. MOS Technology, Solid-State Electron., vol. 15, pp , (1972). FIGURE 10: Experimental (symbols) and expected (lines) threshold voltage for a W/L=14 µm/2.0 µm n- MOSFET. Taken from [19]. Recently McKinnon et al. [20] extended the Pao- Sah model in order to include the effect of this forwardbiased junction. They derived an expression where the purely MOSFET-drain current was distinguished and added to the purely BJT-collector current. This is the same model used in [14],[16],[17] to model the dc characteristics of the GC LPNP and circuits based on it. Therefore, the earlier modeling of DTMOS as a parallel combination of a BJT and a MOSFET was justified. Nevertheless, the development of a true DTMOS circuital model still remains a subject for further research. VI Conclusions The development of the dynamic threshold voltage MOSFET has been presented in this contribution from a historical perspective. The forward biasing of the substrate was originally proposed as a way to improve the performance of MOSFETs operating at low temperatures. Later, by connecting the gate to the substrate, a [3] R.H. Dennard, F.H. Gaensslen, L. Kuhn, and H.N. Yu, Design of Micron MOS Switching Devices, in IEEE Int. Electron device Meet., Washington, DC, Dec., (1972). [4] R.H. Dennard, F.H. Gaensslen, H.N. Yu, V.L. Rideout, E. Bassous, and A. Le Blanc, Design of Ion- Implanted MOSFTE s with Very Small Physical Dimensions, IEEE J. Solid-State Circuits, Vol. SC- 9, pp , (1974). [5] G.A. Sai-Halasz, M.R. Wordeman, D.P. Kern, E. Ganin, S. Rishton, D.S. Zicherman, H. Schmid, M.R. Polcari, H.Y. Ng, P.J. Restle, T.H.P. Chang and R.H. Dennard, Design and Experimental Technology for 0.1-µm Gate-Length Low-Temperature Operation FET s, IEEE Electron Dev. Lett., Vol. EDL-8, No. 10, pp , (1987). [6] T. Yamamoto, T. Mogami and K. Terada, A New CMOS Structure for Low Temperature Operation with Forward Substrate Bias, IEEE Symposium on VLSI Technology Digest of Technical papers, pp , (1992). [7] S. Matsumoto, Research on Low-Temperature Operation of CMOS Devices in Japan, in Low Temperature Electronics and High Temperature Superconductivity, The Electrochemical Soc., Proceedings Vol. PV-93-22, pp. 3-18, (1993).

7 [8] F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, P.K. Ko, and C. Hu, A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation, IEEE International Electron Device Meeting, IEDM, Proc., pp , (1994). [9] C. Wann, F. Assaderaghi, R. Dennard, C. Hu, G. Shahidi, and Y. Taur, Channel Profile Optimization and Device Design for Low-Power High-Performance Dynamic-Threshold MOSFET, IEEE International Electron Device Meeting, IEDM, Proc., pp , (1996). [10] F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P.K. Ko, and C. Hu, Dynamic Threshold-Voltage MOSFET (DTMOS) for Ultra-Low Voltage VLSI, IEEE Trans. Electron Dev., Vol. 44, No. 3, pp , (1997). [11] H. Kotaki, S. Kakimoto, M. Nakano, T. Matsuoka, K. Adachi, K. Sugimoto, T. Fukushima and Y. Sato, NOvel Bulk Dynamic Threshold Voltage MOS- FET (B-DTMOS) with Advanced Isolation (SITOS)and Gate to Shallow-Well Contact (SSS-C) Processes for Ultra Low Power Dual Gate CMOS, IEEE International Electron Device Meeting, IEDM, Proc., pp , (1996). [16] M. J. Deen, A New Gated Lateral pnp Bipolar Transistor Using 0.8 µm BiCMOS Technology - Characteristics and Applications, Proceedings of the 7th International Conference on Microelectronics (ICM 95), Kuala Lumpur, Malaysia, pp (19-21 December 1995). [17] M.J. Deen and Z.X. Yan, Low Temperature Characteristics of Gated Lateral PNP Transistors, 25th European Solid-State Device Research Conference (ESSDERC 95), The Hague, Nederland, pp (25-27 September 1995). [18] M.J. Deen and Z.X. Yan, Unique D.C. Characteristics of a New Gated LPNP BJT Using 0.8µm BiC- MOS Technology, Canadian Journal of Physics, Vol. 74, pp. S189-S194 (1996). [19] F.J. De la Hidalga-W., M.J. Deen, E.A. Gutiérrez- D., F. Balestra, Effects of the Forward-Biasing the Source-Substrate Junction in n-mos Transistors for Possible Low Power CMOS ICs Applications, Journal of Vacuum Science and Technology B, Vol. 16, No. 4, pp , Jul/Aug (1998). [20] W.R. McKinnon, R. Ferguson, and S.P. McAlister, A Model for Gated-Lateral BJT s Based on Standard MOSFET Models, IEEE Trans. on Electron Dev., Vol. 46, No. 2, pp , (1999). [12] H. Kotaki, S. Kakimoto, M. Nakano, K. Adachi, A. Shibata, K. Sugimoto, K. Ohta and N. Hashizume, Novel Low Capacitance Sidewall Elevated Drain Dynamic Threshold Voltage MOSFET (LCSED) for Ultra Low Power Dual Gate CMOS Technology, IEEE International Electron Device Meeting, Proc., pp , (1998). [13] M. Horiuchi, A new Dynamic-Threshold SOI Device having an Embedded Resistor and a Merged Body-Bias-Control Transistor, IEEE International Electron Device Meeting, Proc., pp , (1998). [14] Z. Yan, M.J. Deen, and D.S. Malhi, Gate-Controlled Lateral PNP BJT: Characteristics, Modeling and Circuits Applications, IEEE Trans. Electron Dev., Vol. 44, No. 1, pp ,(1997). [15] M.J. Deen, D. S. Malhi, Z.X. Yan and R.H. Hadaway, Modulation Circuit, U.S. Patent Serial Number 5,498,855 (12 March 1996).