Chapter IV Low Noise Amplifier Design and Optimization

Transcription

1 Chapter Low Noie Aplifier Dein and Optiization. CMOS Overview Low Noie Aplifier (LNA) i the ot critical part of a receiver front end, in ter of the receiver perforance. Many circuit with different confiuration have been propoed for LNA, in different application. After chooin proper circuit for LNA, thi circuit ut be deined and optiized. ariou technique have been propoed for LNA dein and optiization. n thi ection an overview of available LNA circuit and dein and optiization technique will be overviewed. tel , verion - 8 Jan 00.. CMOS LNA Circuit LNA circuit in CMOS technoloy are deined a Coon Source (CS) or Coon Gate (CG) tae. Cacode tae that i widely ued in CMOS RF LNA, can be conidered a current reue confiuration of a CS tae, followed by a CG tae. Chooin proper circuit depend on the pecific application for which the LNA i deined and the deiner experience. For each application, oe of LNA characteritic are ore iportant than the other and thi i a uideline for the deiner to chooe proper circuit for LNA.... CS veru CG confiuration CS and CG are two widely ued tranitor confiuration in CMOS LNA circuit. CS LNA ha hih ain and ood noie perforance []. Placin an inductor in the ource of a CS tae the well known nductive Source Deenerated i obtained. Thi inductor affect the ain and noie perforance of LNA, a will be dicued in the future. CG confiuration lead to low power, robut aaint paraitic and table circuit [], []. CG confiuration ha weak noie perforance [3]. Soe technique, uch a capacitive cro couplin, ha been preented to iprove the CG tae noie perforance [4], [5], [6]. Wideband input atchin i poible for CG confiuration and hence thi confiuration i widely ued in broadband LNA circuit [7], [8]. However CS confiuration ay be ued in wideband application uin pecial feedback or atchin circuit. nductive ource deenerated CS confiuration i conventionally ued in narrowband LNA circuit [9].... Cacode LNA Cacode LNA proie hih power ain, ood noie perforance, low power conuption and hih revere iolation [0], [], []. n lower band of icrowave frequencie, the noie ource of the upper tranitor of cacode tae (cacode tranitor) i deenerated by the lower tranitor output ipedance [3]. Conequently cacode tae ha uperior noie perforance. Unfortunately excellent noie and ain perforance of cacode tae derade in very hih frequencie. Thi i due to ubtrate paraitic adittance at the drain-ource coon node that increae a frequency increae [4], [5]. n conequence of lower ipedance in the ource of upper tranitor, it drain noie appear in the output [3], [6]. A will be explained later, cacode tae ha widely been ued in -wave frequencie. Like a CS tae, cacode tae i proper for narrowband application, however uin feedback technique ake poible uin of cacode tae in ulti band and wide band application [7], [8]. Another way to ue cacode confiuration in wideband application i uin coplicated LC atchin network in the input [9]. 84

2 ...3 Sinle Stae eru Multitae Multi tae LNA propoe hiher ain, in coparion with inle tae LNA. The noie perforance of ulti-tae LNA i not deraded, ince the noie perforance i ainly deterined by the firt tae. Thi can be hown uin Free noie equation [0]: F F F F3 FN L (-) G G G G G LG N Where F i the total noie factor and F i and G i are the noie factor and power ain of i th tae. Norally the ain of firt tae i hih enouh to uppre the effect of econd tae in the total noie fiure. Baed on the above equation, hiher ain for LNA i very iportant to reduce the noie contribution of the ixer (followin the LNA) in the NF of receiver front end. Conequently ulti tae LNA i ued in hih perforance receiver. Unfortunately two tae LNA need hih DC power conuption and hence i not uitable for low power application. Two ucceive cacode tae have widely been ued in variou application, fro few GHz to -wave band [], [], [3]. tel , verion - 8 Jan 00.. CMOS LNA Characteritic A it nae iplie, noie perforance and power ain are the ot iportant characteritic of an LNA. Beide thee characteritic, the ain paraeter affectin the election of a popper circuit for an LNA are DC power conuption, bandwidth, tability, linearity, upply voltae and chip area.... Noie and Power Gain Matchin Uin optiu noie atchin, iniu achievable noie fiure of an LNA (NF in ) i obtained. On the other hand, power ain (conjuate ipedance atchin) yield the axiu available power ain for a circuit. Unfortunately thee two atchin are contradictory and hence both of axiu available ain and iniu noie fiure are not iultaneouly poible. Fortunately, in CMOS technoloy thee two atchin condition are very cloe toether and thi i an iportant advantae of CMOS circuit that can alleviate inherit crucial noie perforance of CMOS technoloie [3]. Thank of thi property, iultaneou noie and power atchin becoe poible in CMOS technoloy []. For axiu power ain atchin, the input ipedance of LNA ut have a reitive ter. Then atchin network tranfor thi reitance to the real part of the ource (enerator) ipedance. Different claic technique to produce required reitive ter in the input ipedance of an LNA ha been hown in Fi. - [4]. n the cae of CG tae, the reitive ter i part of the input ipedance to the ource of the CG tranitor. For a CS or cacode tae the input ipedance i pour capacitive (in very low frequencie) and hence a reitive part hould be added to the input ipedance. Thi i done by a reitive feedback, or a parallel reitance in the ate or a deeneratin inductance in the ource of CS tranitor, a depicted in Fi. -. Parallel reitance in the ate increae the noie fiure of LNA and hence doe not ued in noral dein. The feedback reitor between drain and ate, for a elf-bia echani for tranitor, a well contribute in the real part of the input ipedance to relax the atchin circuit [5]. 85

3 Fi. -. Different claic technique to produce reitive ter in the input ipedance of an LNA [4] tel , verion - 8 Jan 00 Deeneratin inductance in the ource of CS tae produce a reitive ter in the input ipedance of MOS tranitor. Thi technique i widely ued in CS and cacode LNA circuit [6], [7], [8], [9]. n addition, thi inductor ake optiu noie and power point ore cloe toether [30]. Gate poly ilicon reitance can be ued for producin reitive ter in the input ipedance of a CS tae. n thi way the ate reitance i tranlated to 50 oh, uin an LC network [3]. n [3] a new technique ha been propoed that produce a reitive ter in the input ipedance of a cacode tae, without uin deeneratin inductor that derade the ain, in 60 GHz band. Matchin bandwidth i an iportant factor in deinin atchin network. CS and cacode tae are proper choice for narrowband dein. Source deenerated cacode or CS tae i exhibit a ood narrowband atchin, hih tability and ood noie perforance. A entioned earlier, cacode and CS tae can be ued in broadband or ulti-tandard application, uin reitive feedback or pecial LC atchin network. n contrat to CS tae, CG tae propoe wideband atchin poibility, a decribed previouly. Soe pecial atchin technique have been developed for UWB application [33]. Direct atchin of antenna to LNA in a receiver front end ha been conidered in recent year [34], [35], [36]. Uin thi technique, iultaneou optiu noie and power atchin of LNA becoe poible. A part of iae frequency rejection i conventionally accoplihed by the RF filter in the LNA input. n interated dein, thi filter can be deined a a part of input atchin network [37], [38], [39].... Noie and Linearity proveent Technique Noie cancellation technique are ued for iproveent of LNA noie perforance [40], [4], [4]. Many noie cancellin technique have been developed for CMOS broadband LNA for UWB application [43], [7]. Thee technique are not neceary in narrowband dein. The reaon i that in a narrowband LNA iniu noie fiure (NF in ) i achievable with proper atchin dein, however in the cae of broadband LNA the atchin circuit frequency repone varie in the LNA operation band and can not atify NF in in all of the band [7]. Ultra Wide Band 86

4 tel , verion - 8 Jan 00 Noie cancellin bai ha been depicted in Fi. - [4]. The noie current due to CS tranitor drain theral noie, and inal current both arrive in the output node fro two different path. Sinal current fro thee path are in phae, but two arrivin noie current are 80 0 out of phae. Conequently noie current i attenuated in the output, but the deired inal current aplified [7].A hown in Fi. -, noie cancellin technique are baically feed-forward chee. Conequently, in very hih frequencie, in which the accurate control of inal phae in different path i not poible, thee technique can not be ued. Noie cancellin ha been reported for frequencie up to 0 GHz [43]. The external noie oriinated fro other circuit in the chip and coupled throuh the ubtrate, affect the noie perforance of a CMOS LNA [44], [45]. Noie fiure deradation of an LNA, due to power and round noie, ha been analyzed in [46]. Global uard rin around whole of the LNA circuit can be ued for reducin penetration of noie of diital circuit into the LNA ection. Thi iue i very iportant in Syte-on-Chip (SoC) dein [47]. Nonlinearity of a CMOS LNA i due to the nonlinear nature of MOS tranitor conductance and tran-conductance and hence the tranitor bia reatly affect the linearity of the circuit. Linearity analyi for CS, CG and cacode tae have been addreed in variou paper [48], [3], [49]. Drain current can be explained a: 3 i d v v v L (-)! 3! caue the third order nonlinearity and i neative in weak inverion and i poitive in tron inverion reie of MOS tranitor. Conequently, uin two tranitor in different (a) (b) Fi. -. Noie cancellin bai ha for a CS tae: Repreentative diara (b) Practical circuit(a) [4] 87

5 bia reie can be rejected. The bia value at which i zero, i called Linearity Sweet Point [7]. caue the econd order nonlinearity. Althouh ha not weet point, it can be eliinated uin oe technique. The ot popular technique i uin differential circuit, in which econd order ter appear a coon ode inal and hence hihly rejected in the differential output. The other technique i uin nverter Type Aplifier, in which NMOS and PMOS tranitor pair in CS confiuration yield very ood econd order linearity [50]. n narrowband circuit, econd order ter fall out of circuit operatin band and hence are not iportant. However in broadband circuit in which noie cancellin or linearity iproveent technique are ued, the econd order ter appear a extra third order ter in output [7]. Third order nonlinearity effect can be iproveent uin oe technique. n [3] a iple ethod ha been preented to iprove the linearity of a cacode tae. The third order ter in the drain current of a cacode tae can be aborbed by a PMOS tranitor. Thi technique ha been addreed in [5] to iprove the P3 of a cacode LNA. Active pot ditortion ha been developed in [5] to iprove the LNA linearity. tel , verion - 8 Jan Other ue in CMOS LNA Dein..3. Feedback in CMOS LNA Circuit Feedback technique can be ued in circuit in which the active device pole are in frequencie well above the feedback loop bandwidth. With increain f T of MOS tranitor in recent year, it ha been poible to ue feedback in hih frequency LNA circuit [53]. Feedback loop i ueful in wideband atchin of CS tae [7]. n [8] reitive feedback ha been ued in dein of cacode ulti-band LNA for ulti tandard tranceiver. n [54] RLC feedback ha been ued in wideband atchin of a cacode tae. Feedback technique are often adopted in deinin low-noie aplifier in order to hift the optiu noie ipedance to the deired point [55]. Feedback reduce the nonlinearity of the circuit and iprove P3 point [48]. ariou feedback technique ha been invetiated and copared in [56]...3. Electrotatic Dichare Protection Due to hih input ipedance and low ate breakdown voltae in the CMOS circuit, ESD protection in the /O pad i an iportant iue in thee circuit. n RF circuit, the trend i to ue iple ESD protection circuit, to prevent the perforance deradation. n the frequencie above 5 GHz, tow diode are conventionally ued between the inal line and GND and the inal line and DC power line [57], [58]. However in oe work SCR baed ESD protection, beide LC circuit have been ued uccefully in up to 8 GHz [5], [59] Power Diipation and Chip Area To reduce the LNA power diipation, pecial care hould be done in circuit confiuration and dein tep. Current reue i one the ucceful technique in reducin DC power of interated circuit. Thi technique ha been widely ued in low power RF dein to reduce DC power conuption. [43]. A an exaple, in [60] a CS tae followed by a cacode tae ha been deined in current reue confiuration. LNA with CMOS tranitor in ub-threhold reie i ueful in very low power application [6]. However, by thi way the tranitor i very low and hence can not be Third order nput ntercept Point Electrotatic Dichare 88

6 tel , verion - 8 Jan 00 ued in very hih frequencie, in which increaed loe in different part of circuit neceitate hih for tranitor. The tran-conductance of CMOS tranitor decreae with decreain the drain current. n oe cae -bootin technique are ued to increae total, without increain drain current [] [6]. Uin active load (PMOS tranitor) in drain of NMOS tranitor of LNA, hih load reitance i obtained, without hih DC power diipation in load reitance [5]. However, paraitic capacitance in the output node in conjunction with hih load reitance, liit the axiu frequency. For exaple, due to thi proble, the unity ain of a reitive-load differential pair in 90 n CMOS technoloy i liited to 5 GHz [63]. To olve thi proble, inductive load i ued for aborb the paraitic capacitance. Paive inductor have low Q in CMOS technoloie and not only add any difficultie to circuit dein proce, but alo need increae the chip area. To overcoe thi proble, active inductor are ued intead of paive inductor, to obtain very all hih-q inductor [64]. Uin active inductor, an LNA ha been deined in chip area a all a [57]. The ain proble with active inductor i their liited frequency. nductor-le LNA ha been reported in [7] and in [65] up to 0 GHz. Uin luped eleent, intead of ditributed eleent lead to aller chip area. The different apect of luped eleent veru ditributed eleent have been copared in [66] and []...4 CMOS Principle ariou technique have been adopted for CMOS LNA dein and optiization. Soe claified and well known technique have been reviewed and explained in [55]. The Claical Noie Matchin (CNM) technique wa reported in [67]. n thi technique, the LNA i deined for iniu NF by creatin the optiu noie ipedance to the iven aplifier, which i typically ipleented by addin a atchin circuit between the ource and input of the aplifier. By uin thi technique, the LNA can be deined to achieve an NF equal to NF in of the tranitor, the lowet NF that can be obtained with the iven technoloy. However optiu noie ipedance ha coniderable difference with optiu power ain ipedance (coplex conjuate atchin) and hence the aplifier can experience a inificant ain iatch at the input. Therefore, the CNM technique typically require coproie between the ain and noie perforance. Siultaneou Noie and nput Matchin (SNM) i obtained uin erie feedback, without deradation of the NF [55], []. The erie feedback with inductive ource deeneration, which i applied to the coon-ource or cacode topoloy, i epecially widely ued for narrow-band application []. nductive ource deeneration facilitate the iultaneou noie and ipedance atchin, without deradation of NF in and R n [30]. Power Contrained Noie Optiization (PCNO) i ued for noie optiization, for a iven DC power diipation. The drawback of thi ethod i a CNM, by which the power ain i carified. Specially in low power dein the power ain deradation i crucial. To overcoe thi proble, Power Contrained Siultaneou Noie and nput Matchin (PCSNM) technique wa addreed [55]. Uin thi technique, SNM condition i held for a iven DC power. A we entioned previouly, SNM i potentially achievable in CMOS technoloie. However the proble i a proper optiization ethod to obtain SNM for a iven DC power diipation. The PCSNM technique developed in [55] i an analytic optiization and ha been derived uin very iple tranitor odel. Thi iple odel i ueful in frequencie up to few GHz, but loe it accuracy for hiher frequencie. 89

7 n [68] a ulti-tep iulation baed proce ha been ued in optiization of inductively ource deenerated cacode LNA. n firt tep uin iulation, F in and noie equivalent reitance (R n ) of cacode tae, without deeneratin inductor i calculated for variou tranitor width, keepin the DC power diipation contant. By thi way optiu tranitor width i deterined. Then feedback inductance and atchin network i calculated to obtain iniu noie fiure, with iven DC power. Graphical optiization of a CG LNA ha been addreed in [69] and in [70], an LNA dein flowchart ha been preented, coniderin linearity perforance...5 CMOS LNA in Millieter Wave Frequencie tel , verion - 8 Jan CMOS LNA in -band n recent year, any -wave tranceiver ub-circuit have been reported in CMOS technoloy. Recently publihed -wave LNA in CMOS technoloy have been tabulated in Table -. Like old RF LNA, cacode topoloy ha preerved it excellence in -wave frequency rane. Cacode tae ha been widely ued in technoloie other than CMOS [7], [7] [73]. Neverthele, other circuit confiuration like CS and CG topoloie have been tried in thi context [74], [75]. Razavi reported a CG LNA in 60 GHz, in 0.3 u CMOS technoloy in 006 [75]. He claied that cacode tae ha difficultie in -wave rane, due to it pole in the coon node that i in order of f T /. Thi pole hunt derade the cacode ain and noie perforance in -wave frequency. He alo invetiated that conventional CG tae i not uitable for -wave rane, due to the capacitive part of the tranitor input ipedance. Finally he propoed a odified CG confiuration, a hown in Fi. -3(a). He ued an inductor, intead of the CG tae current ource, to copenate the capacitive ter of the input ipedance. By thi way the contribution of the current ource of CG tae i alo eliinated. Cacode tae aain wa introduced in -wave rane by Terry ao et al. in 006 [3]. They ued a all erie inductor in drain of lower tranitor, to tune up the cacode pole. Thi technique wa ued in earlier eneration of RF CMOS [7]. TABLE - Recently publihed -wave LNA in CMOS technoloy Ref. Topoloy Technoloy Freq. Power P db P3 Gain NF Area ear (CMOS) (GHz) (W) (db) (db) (db) ( ) [76] 3-tae 30 n NA Cacode (in) [] 3-tae 30 n NA Cacode [77] -tae 90 n NA NA. 6* Cacode [3] -tae 90 n 58 4 NA * Cacode [78] -tae 90 n 60 4 NA NA Cacode [79] -tae 90 n 58 4 NA NA * Cacode [80] -tae 65 n 60 34* NA NA.5* 7.3* 0.4* 007 Cacode [8] -tae 90 n 64 86/48 NA NA Cacode /3.5 /6.7 [74] 3-tae C.S. 30 n NA * * Siulation Reult 90

8 The odified cacode tae ha been hown in Fi. -3(b). The odified cacode ha uperior perforance and ha been ued in the lat reported -wave LNA by Para and Razavi [8]. Neverthele, tandard cacode tae i ued yet in CMOS -wave LNA dein [80]. Perforance of CMOS technoloy in -wave band i well coparable with np-baed HEMT, HBT and SiGe technoloie. Still the chip ize of fabricated LNA in CMOS technoloy i very aller than other technoloie [], [3]. tel , verion - 8 Jan CMOS LNA in Q-band (Ka-band) n pite of reported -band LNA in the lat ection, where cacode tae wa doinantly ued by the deiner, the reported work in around 30 GHz band how that CS tae ha been conidered in any wok. n [83] two LNA, one in 0 GHz, uin a inle tae CS, and another in 40 GHz uin two CS tae have been reported. Two tae CS LNA with deeneratin inductor ha been reported in [84] in 4 GHz. A 3-tae CS LNA in 40 GHz band ha been reported in [85]. n [86] two cacode tae ha been ued in dein of a 3-34 GHz LNA. n thi work hunt inductor have been added to the cacode node, to aborb the paraitic capacitance at thi node and to eliinate the cacode econd pole, the ain drawback of cacode tae in -wave dein [87], [3]. The econd pole of a cacode tae depend on the ain of cacode (upper) tranitor and the total capacitance at the cacode coon node and i calculated a [86]: p (-3) Cd Cd C Cd Another way to overcoe thi drawback of cacode tae ha been addreed in [88], by placin an inductor in the ate of upper tranitor. By thi way very low power 6 GHz LNA ha been deined. Cobination of CS and cacode tae i ueful in -wave LNA dein. t ha been invetiated that CS confiuration in the firt tae and cacode confiuration in the econd tae incorporate ood noie perforance of CS tae and hih ain of cacode tae [89], [87]. A uary of recently publihed Q and Ka band CMOS LNA have been lited in Table -. (a) (b) Fi. -3 (a) CG tae ued in 60 GHz LNA [75] and (b) 60 GHz LNA with odified cacode tae [3]. 9

9 . Our LNA Circuit and it Analyi A entioned in ection..5., the bet topoloy for a two tae LNA i CS in the firt tae and cacode in the econd tae. The reaon i that cacode tae ha poor noie fiure in -wave band, due to capacitance and paraitic adittance in the cacode node, but ha ood ain and excellent revere iolation. Conequently, CS-Cacode topoloy interate ood noie perforance of CS tae, with excellent revere iolation. However, two tae LNA ha hih DC power conuption and hence i not uitable for our work, in which low power dein i an eential oal. So we have choen the inle tae cacode topoloy for our LNA, a in Fi. -4. Output atchin i perfored uin tandard T network [90] and variou input atchin will be dicued later. The deeneratin inductor ay be nelected in Fi. -4(b), however it i neceary if hih linearity i required. The analyi of the cacode LNA i preented in thi ection. Thi analyi i ued in developent of analytic input and output atchin. Then the reult will be ued in the next ection, in analytic dein and optiization of LNA. tel , verion - 8 Jan 00.. LNA Analyi The all inal odel of the cacode LNA in Fi. -4 ha been hown in Fi. -5. Baed on thi circuit, we will derive equation to calculate the perforance characteritic of the LNA.... nput pedance Analyi A) Conventional Method A iple equation i conventionally ued for calculation of the input ipedance of ( inl ) of thi equivalent circuit i a follow [3]: inl jl L jcl CL R (-4) TABLE - Recently publihed Q and Ka band CMOS LNA Ref. Topoloy Technoloy Freq. Power OP db P3 Gain NF Area ear (CMOS) (GHz) (W) (db) (db) (db) ( ) [86] -tae Cacode 90 n NA NA

10 tel , verion - 8 Jan 00 (a) Fi. -4. Scheatic of our inle tae cacode LNA, input atchin with erial (a) and parallel (b) inductor in the ate of input tranitor. L i the deeneratin inductor in the ource and R i the ate reitance of lower tranitor. Thi iple equation nelect C d feedback capacitance and drain-ource conductance, d. n contrat of it iplicity, it ha been ued in any old and recent work, ince can ive a ood ene about the effect of deeneratin inductance or other feed back in the drain current path [94], [55], [9]. Uin thi iple equation, one can dein the input atchin network of cacode or coon ource LNA. The conventional equation can be ued in frequencie up to few GHz. Scalin down the CMOS technoloie, the drain-ource conductance increae and atedrain capacitance becoe well coparable with ate-ource capacitance. Conequently, the iple equation of (-4) lo it accuracy in -wave circuit in odern CMOS technoloie. n [95] and [96] an accurate equation ha been preented to calculate the input ipedance to a CS or cacode tae: Where: L γ ( γ L d ) R L dl inl jcl C L C L γ R dl R dl d jl C And d (or d ) i the total load ipedance (or adittance) for the drain of CS tranitor. B) Our equation: ethod (b) (-5) Althouh equation (-5) calculate the input ipedance accurately, it i not uitable for input atchin proce. Conequently we have rewritten it with oe odification. To calculate inl in (-5), firt inu hould be calculated (ee the LNA of Fi. -4(a)). On the other hand, to calculate inu the value of output atchin network are neceary. Thi i the philoophy of iultaneou input and output atchin [97]. However, in thi tep we do not have the. Thi proble i due to the fact that in hih frequencie the revere iolation of the 93

11 tel , verion - 8 Jan 00 Fi. -5. Sall inal odel of the cacode LNA, with (a) and without (b) deeneratin inductance. Subcribe U and L denote for Upper and Lower tranitor, repectively. circuit i liited. n the econd tep of our dein we will ue optiization technique to perfor iultaneou input and output atchin. But in the firt tep we ue an approxiation. The adittance into the ource of upper tranitor i calculated a: ( )( y ) U du ddu du inu bu j CU (-5) yddu in which: y j C ddu du du dbu du However for iplicity, we aue that all of capacitance at the output node copletely aborbed by the inductor in the output atchin network (L t in Fi. -4). Alo we aue that the reitive coponent of the input ipedance to the drain of upper tranitor ( indu in Fi. -5) i alot equal to du. With thee auption the total load of lower tranitor i obtained a: U du d jcu Now for iplicity, we define: d G d B L jb d B bl ( / Q ) bu And we noralize all adittance to C : (-6) (-7) 94

12 tel , verion - 8 Jan 00 B C d dl dl L dn, BN, µ, η, τ (-8) CL CL CL L CL After tediou, but traihtforward calculation the real and iainary part of the input ipedance i calculated a: a B a B R N N inl C b BN b BN b 3 X inl C cb b B N N cb b B N N c b Where the coefficient a i, b i and c i are calculated a: a µ τ B dn τ τ a GdN µ 3 3 R ( η µ ηµ ) ( )( G B ) dn dn b dn dn dn µ τ τ ( µ ) ( G B ) ( η µη µ ) ( η µη µ ) G ( ) τ ( η µη µ ) η( ) B dn b µ b τ 3 η µ dn ( ) ( G dn B ) c dn dn dn dn c τ τ ( µ )( B G ) τ G η ( η µη µ ) η G ( µ ) τ B η µ dn ( µ ) η µη 3 τ η dn ( η )( µ ) ( B dn G ) c C) Our equation: ethod (-9) Althouh the input ipedance equation of (-5) i the ot accurate reported, it i poible to derive ore accurate equation. For thi purpoe, coniderin Fi. -5(b) we define: dd jb dl dd d dbl jc dl (-0) Where d ha been defined in (-9) and dbl i the adittance fro lower tranitor drain into the ubtrate. Now uin the notation in (-8), and after oe iplification, we obtain a atrix equation for the all inal equivalent circuit of Fi. -5(b): τ τ j µ jb jµ j jb jµ C ddn L jb ddn ( )( ) ( ) τ j ddn τ τ ( jb ) η jb j ( jb ) ddn ddn ddn LN ddn ddn ddn ddn τ η (-) 95

13 tel , verion - 8 Jan 00 Aain after tediou calculation we obtain the equation to calculate the real and iainary part of the input ipedance to the ate of lower tranitor: a B a B R N N inl C b BN b BN b 3 X inl C cb b B N N cb b B N N c b 3 3 for which the related coefficient a i, b i and c i are calculated a: τ a µ b τ a ddn R ( ) τ τ b ( ) ddn ddn ddn η µ µ bddn η b ddn ddn µ τ τ ( µ ) ( b ) µ µ ( ) ddn τ b µ ddn ddn ddn ddn µ b c c c τ ( µ )( b ) µ µ b ( η µη ) 4 ( ) τ τ τ b µ η ηµ b τ 3 µ ddn ddn 4 ddn ddn 3 ( µ )( b ) ddn τ τ ( µ )( b ) µ b ( µ η µη) τ µ ddn ddn ddn τ µ ddn ddn 4 τ τ τ ( ddn bddn ) ηµ η µ bddn ddn 4 ddn (-)... Our nput Matchin Method We have developed eparate atchin ethod for each of the input atchin circuit of Fi. -4(a), in which a erie inductor ha been ued in the ate, and Fi. -4(b), in which a parallel inductor and a erie capacitor have been ued for input atchin. The iportance of analytic equation to calculate atchin eleent i iplification of LNA dein and optiization. n the optiization proce, provided that they have ufficient accuracy, the analytic equation lead to reduction of oe optiization variable. A) Matchin Uin a Serie nductor in the Gate For conjuate atchin of the LNA in Fi. -4(a) we ut have: R RL RinL L X inl L i the atchin inductor in the ate and R L i calculated fro: R L (-3) L (-4) Q 96

14 tel , verion - 8 Jan 00 in which Q i the inductor quality factor. Now fro (-0) to (-) we obtain the analytic atchin dein equation: ABN BBN C 0 (-5) in which: A C B C C C ( R R ) ( R R ) ( R R ) c b Q c b Q c3 b3 Q τ a τ a The coefficient a i, b i and c i are calculated fro (-9) or (-). After calculatin B N fro (-5), the ource deeneratin inductor i calculated uin (-7) and (-8). Then the ate atchin inductor i calculated fro (-3), in conjunction with (-9) or (-). B) Matchin Uin a Parallel nductor in the Gate nput atchin uin erie inductor in ate ha oe liitation in -wave frequencie. By thi ethod, the deeneratin inductor value doe not have any freedo. Althouh in oe cae thi inductor i neceary to iprove the LNA linearity, it ha deined a all a poible, to avoid power ain deradation. The other proble i that erie inductor in the ate i not uitable for traniion line inductor. Becaue it i eaier to ue thi type of inductor in horted-end confiuration, to iplify the inductor dein proce and to reduce the paraitic effect of the inductor [90]. Here we decribe another way of input atchin, a in Fi. -4(b). n eneral the input atchin of Fi. -4(b) can be explained a in Fi. -6(a). Coniderin thi fiure we deduce: in jx G inl G G inl in j ( B B ) inl j X B inl ( ) ( ) B BinL GinL B BinL For conjuate atchin we ut have if if if R R R > G < G > G G inl inl BinL G inl inl BinL inl there in in i B * in R ( B ) in( B ) ( B ) in( B ) no repone and hence we deduce: inl inl (-6) (-7) n practice the reitive ter of the input ipedance to the ate of the lower tranitor i aller than R and hence the firt condition of (-7) hold. On the other hand the input ipedance to the ate of the lower tranitor i capacitive. Conequently B i an inductive eleent. Althouh theoretically the in of X ay be poitive or neative, baed on our experience, X i alot capacitive. So we ue the atchin network of Fi. -6(b) in our dein. Whenever the in of X i poitive, then the deiner can ue the equivalent inductor. 97

15 X C R in B inl R in L inl R L (a) (b) Fi. -6. General for of input atchin uin two atchin eleent in ate (a) and ipleentation with LC network (b) tel , verion - 8 Jan 00 Fro Fi. -6(b) we have: in jc jl R L G in jb in And uin the definition of quality factor for the atchin inductor we obtain: in jc G L jl Q After iplification we deduce: in jc L Q Q Q G in jb in LGin ( Q ) j( Q LBin ( Q ) ( QB ) L L ( Q )( G B ) in For conjuate atchin two below condition ut be coplied: R L Q Q G L C Q in Q LGin ( Q ) ( in QBin ) L L ( Q )( Gin Bin ) Q LBin ( Q ) Q( G QB ) L L ( Q )( G B ) in in in in in in (-8) (-9) (-0) (-) Auin that Q i independent of L, fro firt equation we derive a econd order equation to calculate the atchin inductor: A L BL C 0 (-) where: A B C Q ( Q ) ( Gin ( Gin Bin ) R ) Q( ( G QB ) R ) R in in So we can iply calculate the atchin inductor: (-3) B ± B 4A C L (-4) A 98

16 After calculatin L we can calculate C fro (-): ( in QBin ) L L ( Q )( Gin Bin ) Q L B ( Q ) Q Q G C L (-5) in Pleae reind that in thi cae we have freedo in chooin deeneratin inductor, ince the atchin proce i valid for each value of L. So we can calculate L a all a poible to coply the linearity requireent, with iniu power ain deradation. t ut be noted that in the above equation, we need to calculate the ubtrate adittance. The ubtrate adittance are layout-dependent and hence can not be calculated before layin out the tranitor. However in thi tep, the deiner can calculate the baed on hi/her experience, uin the ubtrate odel in Chapter, or ay iply replace it with the drain and ource junction capacitance. tel , verion - 8 Jan Output atchin Analyi For output atchin we ue the tandard T network, a in Fi. -7 (a). Fro thi fiure, to perfor the output atchin, we ut calculate the input ipedance to the drain of upper tranitor ( indu in Fi. -5). Uin Fi. -7 (b) we deduce: ( U du )( CU du CdU yu ) indu dbu yucu (-5) CdU ( jcdu du ) ( U du ) C where: y j C U U bu U U du U and U i the load at the ource of upper tranitor, equal to the u of ubtrate adittance at thi node ( bc in Fi. -5 ) and the input adittance to the drain of lower tranitor ( indl in Fi. -5). Uin Fi. -7 (c), the input adittance to the drain of lower tranitor i calculated a: indl where: y y L L dbl L jc ( CL dl CdL yl ) ( jc ) y ( jc ) ( ) bl L R L dl j L jc dl L jc dl L L L jc L L dl dl L C C y dl L L ( ) L jcdl L jc dl L y L (-6) L i the input adittance to the input atchin network, een fro the ate of lower tranitor, and L i the load at the ource of lower tranitor, equal to the u of ubtrate adittance at thi node ( bs in Fi. -5) and the deeneratin adittance of the ource. Now we can calculate the output atchin network eleent. Uin Fi. -6(b) the output ipedance of LNA i calculated a: out jc t L t Q Q Q G LtGindU ( Q ) j( Q Lt BindU ( Q ) ( QB ) L L ( Q )( G B ) indu indu t t indu indu (-7) 99

17 tel , verion - 8 Jan 00 Where Q i the quality factor of L t. For conjuate atchin two below condition ut be coplied: Q LtGindU ( Q ) ( indu QBindU ) Lt Lt ( Q )( GindU BindU ) Q Lt BindU ( Q ) ( QB ) L L ( Q )( G B ) Rload Lt Q Q G (-8) Lt Ct Q Q GindU indu t t indu indu Auin Q i independent of L, fro firt equation we obtain a econd order equation to calculate L t : A L BL C 0 (-9) in which: A C Q t B Q t ( Q ) ( G ( G B ) R ) ( ( G QB ) R ) R load indu indu indu indu indu load load after olvin the above equation we obtain: (-30) B ± B 4A C L t (-3) A After calculatin L t, we can calculate C t fro (-8). Fi. -7. The equivalent circuit to calculate the output atchin network (a) and the equivalent circuit to calculate the input ipedance to the drain of CG tae (b) and CS tae (c) 00

18 ...4 Power Gain Analyi Firtly we calculate the voltae ain of a inle tranitor coon ate and coon ource tae. Then the reult will be ued for calculation of a cacode tae power ain, a well a noie analyi in the later iue. tel , verion - 8 Jan 00 A) Sinle Tranitor Stae The inle tranitor tae ha been hown in Fi. -8. Uin the all inal odel of coon ource tae in Fi. -8(a) we can write two KCL equation: ( jc )( i ) d( d ) ( b ) 0 ( ) ( ) jc ( ) ( ) i d d d d And after oe calculation and definin: y y dd d we deduce: A di jc d i jc d d d db b ( )( jc ) y ( jc ) d y y dd d i ( ) d d d d db 0 Coniderin the effect of R in Fi. -7, we define another voltae ain: A (-3) i i inl R (-33) And finally: A A (-34) d A d di i And for the coon ate tae of Fi. -8(a) we can write: C ( ) jcd ( d ) 0 ( ) ( ) jc ( ) ( ) j d d Conequently we deduce: A d d n which: y y dd d jc y jc ( d ) jc ( jcd ) jcd ( jcd ) y ydd jc d d R d db d d d d db 0 (-35) (-36) i equal to the adittance into the input atchin network fro ate ide, in. f erie inductor i ued in input atchin network (ee Fi. -4 (a)), in i equal to: in R L ( j / Q ) L (-37) And if parallel inductor i ued in input atchin network (ee Fi. -4 (b)), in i equal to: in (-38) L / ( j / QL ) R jc 0

19 d d ( i ) ( d ) ( ) ( i ) ( d ) R C d db R C d db C v v ( ) d b C v v d b (a) (b) Fi. -8. Sall inal odel of coon ource (a) and coon ate (b) tae tel , verion - 8 Jan 00 B) Sinle Stae Cacode LNA For calculatin the LNA power ain, the circuit in Fi. -9 have been ued. Baed on thi fiure we ue a 5-tep voltae tranfer function to calculate the voltae ain and then the power ain. oltae tranfer function fro ource to the circuit input i calculated a: A in in (-39) in R oltae tranfer function for the input atchin network depend on the input atchin network topoloy. For input atchin with erie inductor, a in Fi. -4(a), uin Fi. - 9(a) we obtain: A in L inl L inl ( j Q ) L (-40) Where inl i calculated fro (-) and Q L i the quality factor of the atchin inductor. n the cae of input atchin of Fi. -4(b), uin Fi. -9(b) we obtain: A in j C L L ( j Q ) L ( j Q )( jc ) L inl (-4) Aain inl i calculated fro (-). To calculate the voltae tranfer function for the lower tranitor, we ue Fi. -9(d). So we can ue (-33) with the lower tranitor paraeter and after ubtitutin: L d inu / ( j Q ) L (-4) oltae tranfer function of the upper tranitor i calculated uin Fi. -9 (e). Coniderin that in the cae of upper tranitor ate node i rounded, fro (-35) we obtain: A du U du du (-43) U yddu A in (-35), y dd i calculated coniderin Fi. -9(e): 0

20 tel , verion - 8 Jan 00 ddu du Fi. -9. Circuit ued in calculation of cacode LNA power ain y j C (-44) du on dbu And on, adittance into the output atchin network fro drain ide, i calculated a: on (-45) L / t ( j / QLt ) Rload jct The voltae tranfer function of the output atchin network i calculated uin Fi. - 8(c). Coniderin thi fiure we can write: A on L du jct RL jc R t L Finally the total voltae ain of the cacode LNA i calculated: L A (-46) A Ain Ad Ad Aon (-47) The input power fro ource into the LNA i calculated a: P in ( ) in Re in (-48) R And the power ain (tranducer power ain) of the cacode LNA i obtained: R in L R L ( ) R Re( in ) in P G A (-49) P Re R in in L L When conjuate atchin hold in the input, the inal power into the input atchin network i: P in (-50) 8R 03

21 Conequently axiu available power ain, i.e. the power ain in conjually atched condition, i calculated a: G P R in in a Gt Gt (-5) Pin 4R Re( in ) tel , verion - 8 Jan Noie Analyi Different analytic equation have been derived for calculation of noie perforance of coon ource or cacode LNA [94], [7], [3]. Neverthele, in our knowlede the reported work have oe liitation that prevent an accurate noie perforance calculation in wave band. ery iple tranitor odel ha been ued. The noie contribution of upper tranitor ha been inored. Thi i a ood approxiation in lower frequencie, in which the ubtrate effect i not crucial and hence the upper tranitor noie i deenerated by it ource ipedance, i.e. the input ipedance into the drain of the lower tranitor. However in -wave rane the ubtrate adittance becoe well coparable with the nodal adittance of the cacode node and lower the noie deeneratin effect. Conequently the contribution of the upper tranitor noie in the total output noie increae. The ubtrate noie ha been inored. A explained, in -wave frequencie the ubtrate adittance increae and hence the ubtrate noie penetrate into the circuit. We have developed our analytic equation to calculate the noie perforance of cacode LNA by which the above liitation have been overcoe. The all inal noie equivalent circuit of cacode LNA ha been hown in Fi. -0. Note that in calculation of noie fiure, the load ipedance ha not any effect and hence for iplicity i ubtituted by hort circuit [3]. Different noie ource in thi fiure are defined a follow: nl and nu are ate induced noie of lower and upper tranitor, repectively. The induced ate noie i correlated with the drain theral noie and in our noie odel i calculated fro (-6). ndl and ndu are drain theral noie of lower and upper tranitor, repectively. The drain theral noie in our noie odel i calculated fro (-60). nbl, ndbl, nbu and ndbu are the ubtrate theral noie, due to the real part of the ubtrate adittance at the lower and upper tranitor ource and drain node, repectively. n i the theral noie due to the input inal ource reitance. nm and nm are the equivalent current noie ource of the input atchin network. nr i the theral noie due to the ate poly-ilicon reitance. Thi noie becoe iportant for all tranitor. nl i the theral noie due to the effective parallel reitance of the deeneratin inductor. Thi reitance i due to the liited quality factor of the inductor. Our noie calculation i baed on calculation of voltae noie in each node of the circuit in Fi. -0. For thi purpoe we ut calculate the nodal ipedance of all node. The nodal ipedance at the input of circuit i: R in ii (-5) in R The nodal ipedance at the ate of lower tranitor i: 04

22 tel , verion - 8 Jan 00 L inl in (-53) inl i calculated fro (-) and in i the input adittance to the input atchin network fro ate ide, hown in Fi. -0. The nodal ipedance at the internal ate of lower tranitor i: iil in R in inl R inl The nodal ipedance at the ource of lower tranitor i: L inl L ( j / Q ) L (-53) (-54) L i the deeneratin inductor. inl i the input adittance to the ource of lower tranitor and i calculated a: jc jc y d ( d )( jc ) y ( jc ) dd ( ) d d dd d C d C in jcd d dd d n which: y y y dd jc d jc db d jc jc C y y d ( jc ) y y C d d b d The nodal ipedance at the cacode node i calculated a: CC indl inu y (-55) (-56) indl and inu are calculated fro (-6) and (-5), repectively. After calculatin the nodal ipedance, we can calculate the noie voltae at each node, uin the noie current ource in Fi. -0. n thi fiure, if erie inductor i ued for input atchin (Fi. -4 (a)), nm and nm are calculated a: nm 4KT f R R R L L j L (-57) nm 0 And in the cae of parallel inductor in the input atchin network (Fi. -4 (b)) we have: nm 0 nm 4KT f R L R L L (-58) 05

23 tel , verion - 8 Jan 00 The noie voltae at the circuit input i calculated a: ( n nm ) ii (-59) ni The noie voltae at the ate of lower tranitor, due to the noie current enterin into thi node i calculated a: ( nr nm ) L (-60) nl The noie voltae at the internal ate of lower tranitor, due to the noie current enterin into thi node i calculated a: nil ( nl nr ) iil (-6) The noie voltae at the ource of lower tranitor, due to the noie current enterin into thi node i calculated a: nl ( nl nbl ndl nl ) L (-6) The noie voltae at the cacode node, due to the noie current enterin into thi node i calculated a: nc ( ndbl nbu ndl ndu nu ) CC (-63) Note that in the above equation, the noie voltae at each node due to other node ha not been included. To include the tranferred voltae, we can ue the voltae tranfer function, derived in previou ection. Doin thi, the total noie voltae at the cacode node i calculated a: nc ( ni Ain nl ) AiL nil AdiL nc AdL nl (-64) Where A dl, A in, A il and A dil are calculated fro (-36), (-40), (-33) and (-3), repectively. The tran-conductance fro the cacode node to the output i iply obtained fro Fi. -0: (-65) no G OC U nc du The total output noie current ( no in Fi. -0) i calculated: no ( U du ) nc ndu ndbu (-66) Subtitutin the equation (-59) to (-63) in (-64) we obtain: nc ( ) A ( ) ndbl nbu ndl ndu and then uin (-66) and reorderin the ter we deduce: no nu CC ( n nm ) ii Ain ( nr nm ) L AiL ( nl nr ) iil AdiL ( ) U du nii A nl A nr ndl in dl A il L dl ( ) nl nbl ( iil AdiL L AiL AdiL ) nl( iil AdiL AdL L ) ( A ) ( ) CC A dil dl ndbl L nm ii nbu A in CC nu A il A nbl ndu dil A dl CC ndl nm L nl L A L il A dil ndu ndbu (-67) 06

24 tel , verion - 8 Jan 00 Fi. -0. Sall inal circuit and noie odel of cacode LNA To analyze the noie perforance of LNA, the output noie power ut be calculated. Thi i accoplihed by calculatin the averae power of (-67). For iplicity we eparate different noie ource in (-66). The contribution of lower tranitor i: ( A A ) nl iil dil dl L ( ) ( ) nol U du (-68) ndl CC AdL L The noie contribution of upper tranitor i: nou ( U du )( nu ndu ) CC ndu (-69) The noie contribution of the inal ource i: no ( U du ) ii Ain AiL AdiL n (-70) The noie contribution of the ate reitance i: nor ( U du )( iil A dil L A il A dil ) nr (-7) The noie contribution of the input atchin network i: ( )( A A A A A ) nom U du nm ii in il dil nm -7) The noie contribution of the ubtrate i: nob L ( U du ) ( ndbl nbu ) CC nbl AdL L ndbu (-73) The noie contribution of the deeneratin inductor i: nol ( U du ) AdL L nl (-74) il dil A) Output Noie Power The output noie power i calculated a ean quare of the output noie current. nl and nu are correlated with ndl and ndu, repectively. Conequently their correlation coefficient, a in 07

25 tel , verion - 8 Jan 00 (-64) hould be conidered. Contribution of the lower tranitor in the noralized output noie power i calculated a: 4kT f nol ( ) U du A dl L CC γ d0l iil A dil A * ( iil AdiL AdL L )( AdL L CC ) c δ Lγ d L dl L δ L 0 (-75) A dl and A dl are voltae ain, defined in (-33) and (-35), repectively. The tranitor noie paraeter, c,, d0, δ and γ, have been defined in chapter, ection -. Contribution of the upper tranitor in the noralized output noie power i calculated a: ( U du ) CC ( ) nou γ d U CC δ 0 U 4kT f ( U du ) U du (-76) * CC CC c U d0 U U δ γ du Contribution of the inal ource in the noralized output noie power i calculated a: 4kT f no A A A ii in il dil ( ) R U du Contribution of the ate reitance in the noralized output noie power i calculated a: 4kT f nor A A A iil dil L il dil ( ) R U du Contribution of the input atchin network in the noralized output noie power i: nom nm A A A A A 4kT f 4 nm ii in il dil L il dil ( ) 4kT f kt f U du (-77) (-78) (-79) nm and nm are calculated fro (-57) and (-58), repectively. Contribution of the ubtrate in the noralized output noie power i calculated a: nob dbu ( ) CC GdbL GbU AdL L GbL 4kT f ( U du ) U du G ( ) (-80) Where G x i the real part of x. Contribution of the deeneratin inductor in the noralized output noie power i calculated a: nol L A 4kT f U du L dl L ( ) R L R (-8) B) Noie Factor The noie factor due to the lower tranitor i calculated a: nol F L (-8) no The noie factor due to the upper tranitor i calculated a: nou F U (-83) no 08

26 The noie factor due to the ate reitance i calculated a: nor F R (-84) no The noie factor due to the ubtrate i calculated a: nob F b (-85) no The noie factor due to the deeneratin inductor i calculated a: nol F L (-86) no Finally the total noie factor of LNA i obtained a: F ( F ) ( F ) ( F ) ( F ) ( F ) (-87) L U R b L tel , verion - 8 Jan Linearity Analyi Different analytic ethod have been developed to evaluate the linearity perforance of LNA circuit in MOS technoloy. Soe of the ue iple equation to etiate the P3 or one-db copreion point (PdB) of LNA [98], [70]. Soe other work have developed coplicated analyi [3], [7]. The ethod developed in [70] i baed on derivin analytic equation of tranitor a a function of ate-ource bia voltae. Then thi equation ha been ued for calculation of hiher order ter of in it Taylor expanion around the bia point, in different operation reion of tranitor. We have ued iilar approach, uin our analytic equation for of MOS tranitor, developed in Chapter. The lare inal tran-conductance of tranitor can be calculated a: G L (-88) Where i the aplitude of AC inal between ate and ource node and the derivative are calculated at bia point. i calculated fro (-4). To calculate P3, we ut drive the circuit with two in-band inal with ae aplitude, but all frequency difference. We denote the ate-ource voltae due to thee inal a: v jt jt ( t) ( e e ) jt jt ( t) ( e e ) v Then the reulted drain current i calculated uin lare inal tran-conductance: i ( t) G ( v ( t) v ( t) ) d (-89) (-90) Uin (-89) we deduce: (-9) d i ( t) ( v ( t) v ( t) ) ( v ( t) v ( t) ) ( v ( t) v ( t) ) 3 and ubtitutin (-88) in (-9) and nelectin out-of-band ter we obtain: 3 rd order nput ntercept Point 09

27 tel , verion - 8 Jan 00 i d jt jt jt jt ( t) ( e e e e ) j( ) t j( ) t j( ) t j( ) t ( e e e e ) Conequently the deired inal power at the output node i calculated a: (-9) de P RL (-93) And the power of 3 rd order inter-odulation ter at the output node i calculated a: M 3 9 P 6 R L (-94) 64 At the 3 rd order intercept point the inal power and the power of 3 rd order inter-odulation ter are equal. So ettin (-93) equal to (-94)we obtain: P3 3 (-95) 3 f deeneratin ipedance i ued at the ource node of tranitor, we have: (-96) Where i the ipedance at the ource node. The voltae at the circuit input i calculated a: in (-97) Ain n which A in i the voltae ain of the input atchin network, defined in (-4). Uin (-95), (-96) and (-97) we obtain: in P3 3 3 Ain (-98) Now iilar to (-48) we can calculate the input power to the LNA at 3 rd order intercept point: ( ) Re P 3 in (-99) P3 And finally: in in ( ) P3 3 Re in 6 in Ain (-00) The tran-conductance ( ), it econd derivative and ratio of over it econd derivative have been hown in Fi. -, for W30 u and different bia condition. Thi fiure how that the econd derivative croe zero. Baed on (-00) at thi point P3 oe toward 0

28 Second derivative of Ratio of over econd 0.5 derivative of tel , verion - 8 Jan Gate-ource voltae Fi. -. The tran-conductance ( ), it econd derivative and ratio of over it econd derivative, veru ate-ource bia voltae infinity. Thi point i the well known weet point of 3 rd order non-linearity. Alo thi fiure how that the linearity increae with increain..3 Our LNA Optiization Methodoloy ariou optiization technique for LNA circuit were dicued in ection..4. Siultaneou noie and power (ipedance) atchin i the ot preferred technique in CMOS LNA and ha been ued in analytic, nuerical or raphical optiization trateie. By thi technique the bet noie perforance i calculated analytically, nuerically or raphically, preervin the conjuate atchin in both input and output. We will purue thi technique in our analytic and nuerical optiization. We have developed 3-tep dein and optiization tratey in our work. The firt tep i baed on the analyi reult of previou ection, in which iple odel are ued for active device and paive and paraitic eleent. n the econd tep, we ue accurate -paraeter odel for active device, a well a an accurate odel for ubtrate and other paraitic effect. n thi tep, atheatical atrix equation are ued in calculatin atchin circuit and LNA perforance characteritic. Then raphical optiization i ued to optiize the dein paraeter. n the third tep, the layout i deined and final pot layout iulation and verification i perfored. All of our optiization and iulation are carried out by our dein tool, briefly preented in ection.4. Our dein tool will be copared in the lat ection of thi chapter, with Spectre RF and the attached foundry dein kit for STMicroelectronic 90 n Global Purpoe (GP) CMOS proce. Accuracy and perforance of our dein tool i better than paraitic-aware iulation in Spectre-RF and hence we have ued it in our dein and iulation. The optiization oal definition i an iportant iue in each optiization proble. The oal ut cover all of the deiner deired characteritic, with proper weiht. n the cae of LNA, four characteritic, i.e. noie factor, ain, linearity and band-width hould be included in the optiization oal. An tandard Fiure-of-Merit (FOM) that i conventionally ued in literature to copare different LNA dein, i defined a [99], [86], [6], [3]:

29 G P3 BW FOM P DC ( F ) (-0) G i the abolute value of power ain, P3 i the abolute value of 3 rd order input intercept point in illiwat, BW i the LNA band width in GHz, P DC i the LNA DC power conuption in illiwatt and F i the noie factor (abolute value). n oe cae P3 i replace by PdB. However we will ue contant-envelope odulation (See Chapter ) in our tranceiver dein and conequently linearity i of le iportance. So we have ued the below FOM to be axiized in our optiization: G P FOM P DC 3 4 BW ( F ) (-0) tel , verion - 8 Jan Step : Analytic Optiization Analytic optiization i baed on the analyi reult of the later ection. The optiization flow diara ha been hown in Fi. -. n thi flow chart we have ued iple earch ethod. However other nuerical optiization can be ued in conjunction with the analytic equation. Two flowchart have been hown in Fi. -. The firt i for input atchin with deeneratin inductor and erie inductor in the ate. Norally with thi atchin, the LNA ha ood linearity. Neverthele there i no freedo to control the linearity. The econd flowchart i applied for LC atchin network. n thi condition the deeneratin inductor ha freedo to control the linearity. The dein tep are a follow: Fi. -. Cacode LNA optiization flowchart, baed on analyi reult, for input atchin with erie inductor (a) and input atchin with LC network (b)

30 A) nput Matchin Uin Serie nductor in Gate a) Calculate approxiated value of inu fro (-6) b) Calculate the coefficient a i, b i and c i n the cae of conventional atchin ethod, thee coefficient are not defined n the cae of our firt atchin ethod, ue (-9) n the cae of our econd atchin ethod, ue (-) c) Calculate the deeneratin inductance, L n the cae of conventional atchin ethod, ue (-4) n the cae of our atchin ethod, ue (-5) d) Calculate the ate inductor, L n the cae of our firt atchin ethod, ue (-9) n the cae of our econd atchin ethod, ue (-) tel , verion - 8 Jan 00 B) nput Matchin Uin Parallel nductor in Gate Thi atchin circuit i not applicable in the cae of conventional input atchin ethod. a) Calculate the deeneratin inductance, L, uin (-7) b) Calculate accurate value of inl n the cae of our firt atchin ethod, ue (-9) n the cae of our econd atchin ethod, ue (-) c) Calculate the atchin inductor, L uin (-) d) Calculate the atchin capacitance, C uin (-5) C) Output Matchin After deinin the input atchin network, the output atchin network i deined. a) Calculate accurate value of indl, uin (-6) b) Calculate accurate value of indu, uin (-5) c) Calculate the atchin inductor, L t uin (-3) d) Calculate the atchin capacitance, C t uin (-8) D) Power ain analyi a) Calculate inu uin (-5) b) Calculate accurate value of inl, uin (-) c) Calculate the voltae ain of the input atchin network n the cae of erie inductor for input atchin, ue (-36) n the cae of parallel inductor for input atchin, ue (-37) e) Calculate the voltae ain of the lower tranitor, with ubtitutin (-37) in (-33) f) Calculate the voltae ain of the upper tranitor, uin (-39) ) Calculate the voltae ain of the output atchin network, uin (-4) h) Calculate the total voltae ain of cacode fro (-4) i) Calculate the tranducer power ain fro (-44) j) Calculate the available power ain fro (-45).3. Step : -Paraeter Optiization After analytic dein and optiization proce, a dicued in the previou ection, we ue -Paraeter analyi to optiization of the LNA circuit. n thi tep 4*4 atrix, developed in Chapter i ued a MOS tranitor odel. n the cae of paive eleent and paraitic, 3*3 and * -Paraeter odel are ued. The detail will be iven in the next ection, in pot-layout iulation. 3

31 tel , verion - 8 Jan Paraeter analyi Bai Our -Paraeter analyi i baed on two-port network analyi and converion fro - Paraeter to S-Paraeter. However, a decribed, we encounter with 3-Port and 4-Port odel, that can not be anipulated uin -Port -Paraeter equation. For iplicity, we have ued a iple tranfor to convert all odel to two-port odel. Conider the 4-Port network of Fi. -, decribed by a 4*4 atrix and terinated to 3 and 4, in 3 ed and 4 th port, repectively. Siply we can write: Now we can write: n which, inv( ) and: (-03) (-04) (-05) So we have; And finally we obtain the equivalent two-port -Paraeter odel: (-06) (-07) 4*4 3 * 4 Fi. -3. Terinated 4-Port network and it equivalent -port odel 4

32 .3.. nput Matchin and Gain Calculation The input atchin with deeneratin inductor in ource and erial inductor in ate can be perfored uin -Matrix analyi, without need for nuerical optiization. The detail have been reported in our paper [00]. Thi ethod reduce one optiization variable and thi lead to le coplicated optiization proce. However thi ethod i not ueful for other input atchin network. The power ain and ipedance analyi, the LNA circuit i tranlated into a et of -Port cacaded network, uin the equation of the previou ection. tel , verion - 8 Jan Noie Perforance Calculation We have developed a eneral ethod to convert any noiy ulti-port network to an equivalent noie-le network plu tandard current and voltae noie at the input port. Repreentin all of the internal noie ource a current noie, eneral noiy ulti-port can be explained a a cobination of a noie-le ulti-port and oe current noie at the port, a depicted in Fi. -4 (a). Without lo of enerality, we ain the input and output port to the port and, repectively. Then the equivalent tandard ulti-port network will be a in Fi. -4 (b). The proble i to find the equivalent current and voltae noie ource at the input port. Decribin the network by atrix we have: M N M N N N M NN Now we define a new atrix: 3 M N 3 33 M N N 3N M NN Then the equivalent current and voltae noie in Fi. -4 (b) i calculated a: n n n n n n3 L L N nn N, nn (-08) (-09) (-0) Where ij and ij are the deterinant of the adjoint atrix of ij th eleent of atrix in (- 08) and in (-09), repectively. After calculatin the tandard equivalent input noie ource, the noie paraeter of the ulti-port network are calculated [0]. n eneral n and n in Fi. -4 (b) are correlated. f the correlation coefficient i denoted a c: c * (-) n n We can divide n into two ter, one of the i correlated to n and the other i un-correlated: (-) n nc nu We can write: 5

33 tel , verion - 8 Jan 00 * n n ( ) nc * nc n nu * n Then the correlation adittance i defined a: (-3) nc c Gc jbc (-4) n And hence it calculated a: c c (-5) n Equivalent noie reitance i defined a: n Rn (-6) 4kTB Equivalent noie conductance i defined a: G u n c nu n nc n (-7) 4kTB 4kTB 4kTB Fi. -4. Noiy ulti-port (a) and it equivalent noie-le ulti-port network, with equivalent current and voltae noie ource at the input (b) 6

34 tel , verion - 8 Jan 00 To derive the equation above we have ued: nu c n (-8) n The optiu ource adittance for iniu noie factor i calculated a: _ opt G c n n G R B u n c jb jb Miniu noie fiure i calculated a: F c c ( G G ) (-9) Gu Rn Sopt c in (-0) GSopt And finally, the noie factor of the ulti-port i calculated a: F Gu Rn S c (-) G S.3.3 Step : Pot Layout Siulation The ain difference between pot layout iulation and -Paraeter analyi in the next ection i in the odelin of traniion line and paive device. Note that all of the MOS tranitor paraitic effect are included in -Paraeter analyi, a well a in pot layout iulation. Pot layout iulation i perfored in two tep. n the firt tep our dein tool i ued for final refineent of circuit paraeter, to eliinate the deviation in the circuit characteritic, due to the accurate paive eleent odelin. The final tep i perfored in the foundry dein kit, after includin all paive odel and paraitic effect, to final verify the dein. The circuit cheatic in the pot-layout iulation ha been hown in Fi. -4. Parallel inductor in ate ha been ued for input atchin, a in Fi. -4 (b). 3-type of ditributed eleent have been ued: traniion line, line-type inductor and T-connector. n addition, A luped odel i ued for odelin RF pad. The detail of RF pad odelin will be iven in Chapter. MM capacitor and all reitor are accurately odeled in the dein kit, coniderin couplin to the ubtrate. LNE-TPE NDUCTOR [ *] LNE-TPE NDUCTOR [ *] LNE-TPE NDUCTOR [ *] Fi. -5. Pot-layout odel of cacode LNA, with parallel inductor in input atchin network. Metal-nulator-Metal 7

35 .4 Practical Dein and Fabrication Firt tep of dein i chooin proper circuit and it topoloy and confiuration. Thi i accoplihed baed on the deiner experience and the requireent of the yte under dein, in which the LNA will be ued. The next tep i deterinin the DC power conuption of the LNA. DC power i deterined baed on the yte requireent and the deiner experience and invetiatin the iulation reult. A we explained, our dein flow i a power- contrained optiization proce and hence, a in all power-contrained LNA optiization technique, the deiner hould etiate or chooe the proper DC power conuption. We will do the DC power election baed on a loical invetiation uin our dein tool. Thi dein tool ha the ability of analyi (iulation) and optiization (ynthei) of cacode LNA with variou confiuration. Both of iulation and ynthei ay be accoplihed in two way: one way i baed on the analytic equation derived in ection.. and the other i baed on the nueric ethod, explained in ection.3.. MOS tranitor odel, decribed in Chapter, i ued in the dein tool. Traniion line, RF pad, inductor, paraitic eleent and other paive eleent are odelled a developed in Chapter. Captured view of the dein tool ha been hown in Fi. -6. tel , verion - 8 Jan Dein Proce.4.. Circuit Topoloy and pleentation ue A dicued in ection -, cacode LNA i ot uited for low power application, ince it enable the deiner to obtain ood perforance uin a inle tae LNA. So we ue cacode topoloy in our dein, a depicted cheatically in Fi. -4. ea,s ea,s ea,s Frequency (GHz) Fi. -6. Captured view of our dein tool 8

36 tel , verion - 8 Jan 00 nput and output atchin network ay ipleented in three way: Matchin uin luped eleent (Spiral inductor and luped capacitor) Matchin with traniion line Matchin uin luped capacitor and line-type inductor ariou ipleentation have been copared in [66]. Matchin uin luped eleent i uitable for low frequency application, althouh it ha been advied and reported in recent year for -wave application [93], [74], [7]. Main proble of thi ethod i difficultie with dein of piral inductor in -wave frequencie. Matchin with traniion line i conventionally ued in dicreet RF circuit dein. Thi technique alo ha widely been ued in -wave interated circuit [74], [83], [85]. Traniion line ay be ipleented a Coplanar Traniion Line (CPTL) or icro-trip line. CPTL ha the advantae of le unwanted couplin fro adjacent line and hiher ipedance [87], [79]. However icrotrip line have narrow line that can be iply eandered and hence are area efficient. The ot advantae of traniion line are preventin the couplin to the ubtrate that i eential in CMOS technoloy, for which the ubtrate ha low reitivity and caue coniderable lo in hih frequency. Fro thi ene, icro-trip line are ore efficient than CPTL [85]. n eneral atchin uin traniion line lead to very lare chip area and hence it avoided, a lon a poible. Matchin uin luped capacitor and line-type inductor cobine the benefit of luped eleent and traniion line atchin ipleentation. By thi way very copact and hih quality factor atchin network i obtained [90], [89]. We will ue thi ipleentation in our dein. Cobination of piral and line-type inductor can be ueful in cae that all and lare inductor are ued in the ae circuit [89], []. Baed on Fi. -4, the output atchin network i accoplihed uin an tandard T network. However for input atchin, we have two option. One i Fi. -4(a), in which a erie inductor ha been ued in ate, a in conventional cacode confiuration [3], [94]. The econd option i uin hunt inductor in ate [90], [60]. To copare thee two option, we invetiate the practical ipleentation iue of atchin inductor. A dicued, we will ue line-type inductor. Line-type inductor can be deined a erie or hunt inductor, a hown in Fi. -7. A thi fiure how, hunt inductor ake poible to ue a hort-ended line-type inductor that ha oe advantae over erie inductor. Shunt inductor lead to ore copact layout, but if erie inductor i ued, the layout will be very lare in one dienion and very all in other one. On the other hand hunt inductor i le uceptible for paraitic effect that can not be accurately odelled in dein tep [90]. Another iportant advantae of hunt inductor over erie inductor i the ipedance tranforation property of hunt inductor that relaxe the input atchin offer freedo to chooe the deeneratin inductor. By thi way the deeneratin inductor i conidered to coply with the linearity requireent and hence aller deeneratin inductor i needed, in coparion with erie inductor atchin. Uin deeneratin inductor reduce the ain and hence i a challene in -wave LNA [79]. Baed of the above uetion, we have choen the parallel inductor in the input atchin network and hence our dein will be iilar to Fi. -4(b)..4.. DC Power Conuption The econd tep of our dein i etiatin the required DC power conuption. Thi i accoplihed baed on the deiner experience and the requireent of the yte under dein, in which the LNA will be ued. Thank with our fat dein tool that ake poible very fat dein and optiization of cacode LNA, we exained any DC power conuption to find the bet value of DC power conuption. For thi purpoe we optiized our LNA with variou DC power and 9

37 Fi. -7. Two different uin of line-type inductor: (a)serial and (b) hunt confiuration. tel , verion - 8 Jan 00 then we copared the reulted axiu FOM of (-0) for each value of DC power conuption. The reulted coparion ha been hown in Fi. -8. Fro thi fiure, 3-W DC power i the bet choice and hence i choen in our dein. t ut be noted that thi reult ha been obtained uin the lat verion of our dein tool that ue coplete and accurate odel of tranitor. n the earlier verion, we had ipler odel and different optiization tratey. Conequently we deined our firt LNA (the fabricated LNA) for DC power of 4-W Optiization and erification After chooin the circuit confiuration and DC power conuption, The LNA can be optiized uin our dein and iulation tool. A explained, the firt tep in thi way i analytic optiization. Then an accurate nuerical optiization i perfored around the optiization variable value, obtained fro analytic optiization. Finally the perforance of deined LNA i verified uin iulation with frequency weep. The perforance of the deined LNA have been depicted in Fi. -9 to Fi. -. S- Paraeter have been hown in Fi. -9. Thi fiure how that iniu value of S and S are lihtly different fro the deined center frequency, i.e. 30 GHz. Thi i due to the FOM DC Power Conuption (W) Fi. -8. Fiure-of-Merit of our cacode LNA with different DC power conuption 0

38 tel , verion - 8 Jan 00 effect of the quality factor of inductor that are odelled ore accurately in iulation ode. Fro thi fiure, axiu power ain i 4.5 db and iolation i well acceptable in all of the band. Fi. -0(a) how the operatin power ain (G), in coparion with the available power ain (G a ). Fro thi fiure, at the center frequency G i equal to G a. Thi iplie ood input and output atchin dein. Noie fiure (NF) and iniu noie fiure (NF in ) have been hown in Fi. -0(b). Thi fiure how that at the center frequency NF ha the allet difference fro iniu noie fiure. Note that NF in i achieved if the optiu noie atchin i atified in the input, that i contradictory with power atchin and hence carify the power ain. Two characteritic in Fi. -0, i.e. equal G and G a, in addition with cloet NF to NF in prove the effectivene of our optiization tratey. Linearity perforance of the LNA ha been depicted in Fi. -. Althouh P3 equal to -.5 db i not very ood linearity, it i ufficient for our application, in which contant-envelope odulation will be ued. FOM defined in (-0) ha been hown in Fi., fro which deduced that the axiu FOM ha been achieved at frequency lihtly hiher than the center frequency. However FOM at the center frequency i not o lower than the axiu value. One iple way to obtain axiu FOM at the center frequency i to hift the dein frequency lihtly lower than the deired center frequency. By thi way axiu FOM i obtained, in expene of a little reduction of power ain and atchin perforance. S-Paraeter(dB) db S S S S Frequency (GHz) Fi. -9. S-Paraeter of 3-W, 30 GHz deined LNA Power Gain (db) Noie Fiure Operatin Power ain Available Power ain NF 5 NFin db.4 db db Frequency (GHz) Fi. -0. Power ain and noie fiure of 3-W, 30 GHz deined LNA

39 0 5 P3 FOM db Frequency (GHz) Fi. -. P3 and FOM, defined in (-0), for 3-W, 30 GHz deined LNA.4. LNA Layout and Pot Layout Siulation tel , verion - 8 Jan Layout Dein Layout dein i very iportant in -wave circuit and ay reatly affect the perforance of the dein. n the cae of our work, thi iue i very ever, ince the available dein kit for our work i a lobal purpoe CMOS dein kit that doe not have any layout library or layout dein uideline for RF device and eleent. The catatrophe i that the extraction tool provided by the foundry dein kit i not ueful for our frequency band of interet. Conequently ot of the layout dein effort and odelin layout effect ut be accoplihed by the deiner. The layout dein can be divided into two cateorie: Active device and paive eleent. The layout iue of MOS tranitor wa invetiated in Chapter and the layout iue of inductor, traniion line and RF pad were conidered in Chapter. The layout and layout odel of MM capacitor and different type of reitor are available in the dein kit library and are enouh accurate to be ued in our dein. The layout of other device and eleent were deined and odeled by ourelve. We have contructed an individual library of required device and eleent a Paraetric Cell (PCELL) in irtue layout dein environent of CADENCE oftware, to which the foundry dein kit ha been attached. PCELL dein provide the poibility of dein of library eleent with paraeterized apect and dienion and each paraeter can be redefined in each intantiation of the library part. All of the layout dein rule, provided by the foundry a the Dein Rule Manual (DRM) ut be coplied for all layout eleent. The ot annoyin rule in our dein wa the denity rule for active, poly-ilicon and etal layer. Denity rule oriinate fro technoloical point of view and each etal (or active or poly-ilicon) layer have their individual axiu and iniu denity liit, defined for different denity calculation criteria. n a eneral purpoe (diital or low frequency conventional analo dein) the deiner ue the dein kit layout library, for which all of the layout dein rule have been coplied and in pecial cae that one want to ue hi/her individual layout, the only proble i to atify the axiu denity liit. The reaon i that the iniu denity liit are coplied by the autoatic duy inertion tool, provided in the foundry dein kit. Unfortunately duy etal perturb the perforance of device and eleent in RF dein and hence autoatic duy inertion can not be ued in RF and pecially in wave dein. The only olution i that the layout be deined anually in accordance with all

40 tel , verion - 8 Jan 00 of the dein rule and the RF area of the layout be covered with no-duy loical layer that prevent autoatic duy inertion. Wide round line of traniion line and inductor can not be routed a inle wide line. ntead the tructure iilar to Fi. -(a) hould be ued. Thi fiure how the top and ide cro ection view. Reind that each round line i actually a 3-dientional tructure, copoed of tacked etal layer, each layer connected to the precedin layer by any via. The via dein i a coplicated proce and we have ued PCELL dein technique to correct intantiation of ufficient nuber of via eleent, a well a routin error-le etal line to contruct a round line with deired lenth and width. To layin out hih ipedance traniion line, incorporated in line-type inductor, we have ued the tructure hown in Fi.(b). By thi way the line capacitance increae, but the line inductance reain alot unchaned. Conequently the reduction of the line ipedance due to duy eleent i iniized. We have developed oe atheatical procedure to analytical dein of etal piece in round line, duy pat and RF pad. Denity rule are ore ever in the cae of RF pad. Pad dein i an iportant and very coplicated iue in layout dein. Different type of pad have their individual requireent. Norally different type of pad are preented a library eleent in foundry dein kit, with different feature like optiu routin poibility, electrotatic dichare (ESD) protection, inal or power handlin. A coon requireent of all type of pad i echanical trenth. Thi i neceary to ake the pad iune aaint the echanical preure due to probin or contactin. Conequently pad have their individual dein rule that are ore tihten that that of other ection. Due to vat area of pad, it ha hih couplin with ubtrate and hence Fi... Top view and cro ection of wide round line (a) and hih ipedance traniion line with pecial duie, deined to iniize the line ipedance reduction due to duie. 3

41 the pad available in the dein kit layout library are not ueable for our dein. So we have deined our RF pad to iniize the couplin and eanwhile atifyin the pad dein rule. A iple repreentation of RF pad ha been hown in Fi..3. To reduce the ubtrate lo, the RF pad i urrounded by a round rin of tacked etal line, a in Fi. -(a). More detail can be found in Chapter. Beide denity rule, the rule related to iniu pace of etal line and via are very iportant and any frequently caue dein rule check error, if do not accurately conidered. Metal line branche ut be routed only in 900 or 450. Thi caue liitation in oe cae. There i a cla of pecial dein rule, referred a Antenna dein rule. Thi cla of rule ha been intended to conider the current denity of etal line and via and to prevent the daae due to electro iration. Fortunately thee rule are not iportant in our dein, ince the current line are of enouh width, very hiher than the antenna rule liit. Actually thee rule are iportant in very dene diital or low frequency dein. The final layout of deined LNA ha been hown in Fi..4. tel , verion - 8 Jan 00 Fi. -3. (a) Layer tack (vertical cro ection) and (b) top view of RF pad Fi..4. Layout of deined LNA. The vide area outide of LNA core will be field with duie by autoatic duy inertion proce 4

42 tel , verion - 8 Jan Pot Layout Siulation Pot layout iulation of the deined LNA wa perfored reardin Fi..5. n thi iulation, coplete MOS odel and related paraitic, developed in Chapter wa ued. Accurate odellin of paraitic effect and extraction of related paraeter wa perfored with full wave iulation uin Anoft HFSS. For thi purpoe, we developed pecial prora to contruct very coplicated 3-dienional tructure in HFSS environent. The detail have been explained in Chapter. The traniion line ection have been optiized uin quai-tatic odel of traniion line, T-junction and line-type inductor, developed in Chapter. n pot layout iulation, the traniion line and inductor wa replaced with their quai-tem odel. RF pad were odelled uin the pad tructure of Fi..3, coniderin the urroundin round rin, a in the final layout of Fi..4. The detail have been preented in Chapter. The inductance and quality factor of the inductor in the input and output atchin network have been hown in Fi..5. Due to effect of RF pad, traniion line and T-branche it i neceary to do oe triin in the lenth of line-type inductor, to obtain better perforance. S-paraeter of the LNA, obtained fro pot layout iulation after triin, have been hown in Fi..6. For coparion, S of pre-layout iulation, hown in Fi..9, ha been included in thi fiure. Bandwidth of pot layout reult i le than that of pre-layout iulation. Thi can be jutified uin the inductance and quality factor line-type inductor in Fi..5. Actually and inductor never act a an ideal inductor in hih frequencie. Each inductor ha a reonance frequency at which the quality factor of inductor decreae to zero. Beyond thi frequency, the inductor act a a capacitor. A the workin frequency near to the reonance frequency, the inductance and the quality factor ha ore harp variation veru frequency and thi i why the bandwidth in pot layout iulation i narrower that pre-layout iulation, in which the reonance of inductor ha not been conidered. The input and output atchin are hold iultaneouly at the center frequency and hence the axiu power ain i achieved at the center of band. Fi..7 how the noie fiure, obtained fro pot layout iulation, in coparion with pre-layout iulation. The noie fiure i lihtly wort in the pot layout iulation and the bet noie fiure i achieved at the frequency lihtly hiher than the center frequency. Linearity and tability of the LNA, obtained fro pot layout iulation ha been hown in Fi..8. Rollett tability factor i defined a [0]: nductance (ph) Quality Factor OMN nductor MN nductor 0 OMN nductor MN nductor Frequency (GHz) Fi..5. nductance and quality factor of line-type inductor in the input atchin network (MN) and output atchin network (OMN). 5

43 K f Where: S S (-) S S S S SS f K f >, the circuit i unconditionally table. Hiher value of K f iplie hiher tability. Fro Fi..8 our dein i unconditionally table in all of the frequency below 60 GHz. Perforance of deined LNA ha been tabulated in Table tel , verion - 8 Jan 00 S-Paraeter (db) S S S S (pre-layout) S Frequency (GHz) Fi..6. Pot layout iulation of optiized 3-W LNA after triin of inductor lenth. S of pot layout iulation ha been copared with pre-layout iulation. Noie Fiure db NF NF (pre-layout) NFin Frequency (GHz) Fi..7. Noie fiure of pot layout iulation, in coparion with pre-layout iulation TABLE -3 Perforance of the deined LNA at 3GHz, fro pot layout iulation P DC (W) S (db) S (db) S (db) S (db) G a (db) NF (db) P3(dB) Kf FOM * * FOM ha been defined in (-0) 6

44 60 50 Stability Factor (Kf) P3 (db) Kf P3-0.5 db Frequency (GHz) Fi..8. Linearity and tability of the LNA, obtained fro pot layout iulation.4.3 Fabricated LNA and the Meaureent Reult tel , verion - 8 Jan Dein and Siulation n 006 we copleted the dein of the firt verion of our LNA in the STMicroelectronic 90n Global Purpoe (GP) CMOS proce. A explained, thi wa the fit experience in the MEP laboratory in bulk CMOS technoloy, in 30GHz band. Conequently we wa obliated to develop a fraework, conitin circuit dein and optiization tool and layout facilitie for -wave dein in bulk CMOS foundry dein kit. The layout of the deined LNA wa copleted in May 006 and wa ent to be fabrication by STMicroelectronic. Baed on our iulation, we found that 4-W i the bet choice for our work, in which power conuption i very iportant. Thi wa baed on the firt verion of our dein tool. A we explained in ection.4.., we deined the lat verion of our LNA for 3-W DC power conuption. The nap hot of the layout ha been hown in Fi..9. Pot layout iulation reult of the fabricated LNA have been hown in Fi..30. Unfortunately due to a itake in layout of the input atchin network, the perforance of LNA wa corrupted, a hown in Fi..3. Since our layout proce doe not have the ability Fi. -9. The nap hot of the fabricated 4-W LNA layout 7