A Novel CMOS Model Design for 2.4 GHz Narrowband LNA input matching using inductive Degenerated Topology

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1 IOS Journal of VLSI and Signal Proceing (IOS-JVSP) Volue 4, Iue, Ver. I (Jan. 04), PP 0-5 e-issn: , p-issn No. : A Novel CMOS Model Deign for.4 GHz Narrowband LNA input atching uing inductive Degenerated opology M.aana eddy, Dr. N.S Murthy Shara, Dr. P. Chandra Sekhar At. Profeor Dept. of ECE,CBI Hyderabad Profeor & HeadDept. of ECESVC College of Engg(E.G) Head & Aoc. ProfeorDept. of ECEOania Univerity, Hyd Abtract:.5 GHz narrow band inductive degenerated (LNA) low noie aplifier ipleented in a 0.8 µ F CMOS proce which i ued in particularly telecoand yte for atellite and alo for WSN (Wirele enor network. he aplifier provide a forward gain (S ) of 6 db with a noie figure of S db. While drawing of 0 w fro.8v Supply by uing inductive coupled degenerated LNA. General er: LNA, Noie figure, gain, linearity. Keyword:F CMOS, VLSI Deign, Wirele Counication I. Introduction Preent day the wirele deign uffer fro face noie,atching and ignal detection.hi i a new challenge for FIC deigner[][].aong the any block of the wirele deign the crucial block i the low noie aplifier. he purpoe of thi block i to atch the antenna input with reaining circuitry.o ipleent the different topologie of the ulti tandard traniion are recognied [9]. Due to low econoy higher integration caling technology the CMOS the copetitor for the ipleentation of radio tranceiver for variouwirele counication yte.one of the priary advantage of uing the CMO i eae of integration with digital ection on the ingle chip. he deign of the low noie aplifier for the atellite i ued in wirele teleetry counication yte. It i divided into any ubyte of nuber of enor and actuator. One of the ubyte i the ater tranponder which i facing earth and then it counicate with the earth tation.eaining ubyte are acceed by thi ater unit. By teleetry unit(mmase)the gathered inforation fro the different ubyte are relayed to earth tation(cmase).[9] elecoand unit i one which,the earth tation end the coand to control the variou ubyte.however the take place through repective ater unit.dve to the advantage like le weight of atellite the counication ut be through wirele. It i baed on IEEE tandard. he firt block of receiver i low noie aplifier(lna).depending on noie figure and gain the overall perforance of receiver i utained. he deign of low noie aplifier i uch that it ut preent iniu noie figure and then gain with ufficient linearity.o terinate the unknown length of the traniion line that deliver the ignal fro antenna to aplifier.iip3 provide the 50Ωinput noie aplifier even a good input atch i ore enitive to the quality of the point of terinating ipedance.he ain reaon of the deign of low noie aplifier which i aied at low power conuption becaue the tandard that i ued for ipleentation of counication yte i at low rate.[9]. LNA equireent:. Gain (0-0 db) to aplify the received ignal and to reduce the input referred noie of the ubequent tage..good linearity: Handling large undeired ignal without uch ditortion. 3. Low noie for high enitivity 4. Maxiu power gain 50 terination for proper operation and can route the LNA to the antenna which i located an unknown ditance away without worrying about the length of the traniion line [].. Baic opologie. Wide band LNA input atching topologie (a) eitive terination (b) coon gate (c) reitive hunt feedback.. Narrow band LNA input atching topologie (a) inductive degenerated (b) reitive terinated []. 0 Page

2 A Novel CMOS Model Deign for.4 GHz Narrowband LNA input atching uing inductive.3 Inductive degenerated LNA: Fig: Inductive degenerated low noie aplifier Fro Figure we can ay that Input ipedance behave like a erie LC circuit, due to the addition of L g in the circuit[3][5]. gl...() Zin (L g L ) Cga Cg atching occur when: gl Z j, and ωl in o o L L C C L can be elected by: L Cg to artificially reduce ω ] [3][5] g g if thi value i too all to be practical, a capacitor can be inerted in hunt with g Z in Lg L ωl Lg g L g,nqs () C g ω L Fignon-idealite of input ipedence. poly, hw n L g,nqs 5g Z jω L () in 0 Lg g L g,nqs 0 (L g L )( Cg / / ) inductance lo Lg :offetz in ; LS : offet Z in and ω 0 ;Gate reitance g:offetz in ;NQS gate reitance g ;NQS:offetZ in ; Q-booting [5]: at reonance we get Q booting effect: L Fig.3. Q-Booting Fig.4.equalent circuit for Aplifier input ignoring C g D Page

3 A Novel CMOS Model Deign for.4 GHz Narrowband LNA input atching uing inductive at reonance we get Q booting effect: Q Lω Cgω0 C g 0 (3) V g =Qxv I d =g v =Qg v G v 0 G Need to watch out for linearity a vg i Q tie larger than the input ignal. Short channel device operating in velocity aturation regie (i.e., large overdrive voltage) are ore forgiving a their g i relatively contant.[3] Equivalentinput network: Fro the ource, the aplifier input (ignoring C gd ) i equivalent to: At reonance, the coplete circuit i a fig4: Noie Analyi: fro fig5, he output noie current due to and g i iply calculated by ultiplying the voltage noie ource by G.[3] he calculation of output noie current due to drain noie i ore involved:i d flow partly into the ource of the device, it activate the g. Output Noie current i d Output noie current: [8] + + (4) Fig.5. Coplete circuit at eonance Fig.6. Q-Booting Noie Analyi Fig.7. Q-Booting Noie Analyi-Drain Noie G o Drain Noie: he noie coponent flowing into the ource i given by the current divider: Page

4 A Novel CMOS Model Deign for.4 GHz Narrowband LNA input atching uing inductive g id (6) ( gg id ) X jl jl jlg X jc jc g g g g jl (5) g d g i X at reonance X jc g jl here we are not including g in the all ignal odel. otal Output Noie: Let' firt ignore the correlation of the gate noie and drain current noie. Notice only one forth of the drain noie flow to output. i G V V i 4 (7) no g d G o i no g o F =+ g G V (8) Note that the Noie figure at reonance i the ae a CS aplifier w/o inductive degeneration. Inductive degeneration did not raie F in but atched the input.if we conider the correlation of the gate noie and drain current noie then one can how. + g F g o (9) (0) L ( QL ) cq 5 5 Q (L L ) 0 g L QC () g 0Cg Optial Noie figure happen for a particular Q L. Poible to obtain a noie and power atch.[4] OptialQ L : If we try to optiize the noie figure while power diipation i kept contant then: i.q L,opt will be independent fro the frequency and around 4.5 ii. F in i not too enitive to Q L and only change by le than 0.dB for Q L between 3.5 and 5.5 iii. Saller Q L reult in larger bandwidth and aller inductor, while a larger Q L reult in narrower bandwidth and larger inductor. Linearity: Linearity of a MOS tranitor in aturation region:[3][4][5] IIP3 i independent of W V VIIP, 4Veff 8Veff Veff Veff trongmos Veff Vg Vth E L Eat V / for L IIP3 LNA 3 Po at, V 6 P D 3 (3) 3 Vat Eat Veff Po VDD o Effect of L on input atch: We ignored the effect of load ipedance on input ipedance in previou derivation. It can be hown that[3] 3 Page

5 A Novel CMOS Model Deign for.4 GHz Narrowband LNA input atching uing inductive ( ) Z r L o S IN jls [ LSS ] jcgs ro L jls ro ro jl S [ Lw r] jc r GS o L (4) L can be large and it can drop the real part of the input ipedance when we ue reonator at output. Notice that the output ipedance influenced the input ipedance even in the abence of C g d Deign ecipe for Inductive degenerated of LNA: Step: Chooe Q L for optial[3] Step: Deterine the current I d fro power budget. Step3: Fro W & I d Width(W) Step4: Fro g and V eff andf in Step5: Select L and L g for the input network NF C g Width(W) QL OC S GS L Lg L 0C g Deign ecipe Iteration: If NF i not low enough, increae by increaing I d (with fixed device ize) and for a fixed current denity, increaing Q will reduce device ize thu reduce total power and hence NF will increae. If the Linearity doe not eet, reduce Q, burn ore current and apply proper linearization technique. If we need to increae gain, chooe larger Q L,Larger g and larger Load (Z L ) [3][]. II. Siulation eult Analyi Calculated Siulated M 0 /0.8 0 /0.8 M 0 /0.8 0 /0.8 L g 3nH 0nH L 0.4nH 0.8nH I d 9A 8.6A Z L.4 6 ABLE-. PAAMEES Spec Siulation Frequency.4Ghz.4Ghz S -0dB - 3 db S 6 db 5.7dB NF db 0.6dB IIP3 0dB -6.85dB Current 0A 8.6A Supply.8V.8V ABLE-. PEFOMANCE he deign wa iulated uing the ADS and alo cadence tool provided for the 8F CMOS proce. he following graph how S,S, noie figure, IIP3, tability factor of inductive degenerated LNA 4 Page

6 A Novel CMOS Model Deign for.4 GHz Narrowband LNA input atching uing inductive Fig 8(a)S paraeter(b)noie figure and (c)s paraeter. III. Concluion he deign of receiver upporting 4G wirele application in all band preent any challenge. Soe of the characteritic of the receiver are ulti band ulti tandard operation, MIMO upport, low power and low cot. By applying atheatical decription for key perforance paraeter of LNA i required 4G front end. hi paper ha preented the deign of gain S 6dB with a noie figure db while drawing 0W power fro.8 volt upply by uing inductive coupled degenerated LNA topology. A leon learned in thi deign i the iportance of intuitive undertanding of reonance and circuit theory when deigning LNA uing wirele teleetry telecoand yte and alo for wirele enor network. eference [] B. azavi, "CMOS technology characterization for analog and F deign, "IEEE J. Solid-State Circuit, vol.34, pp.6876, Mar,999. [].H. Lee, "5-GHz CMOS low noie aplifier", IEEE Journal of Solid State Circuit, Vol.3, May,997. [3] D. Shaeffer,. Lee, "A.5V,.5 GHz CMOS low noie aplifier", IEEE Journal of Solid State Circuit, Vol.3, May 997. [4] N.H. Noh, and.z.a, Zulkifli "Coparative Studie of the folded Cacode, Current-reue and the PCSNIM LNA opologie for W-CDMA Direct Converion eceiver" in proceeding of the international conference on obotic Viio, inforation and ignal proceing ovip 007 Penong, Malia, Noveber, 007. [5] Paul, Weter "ecent rend in CMOS LOW Noie Aplifier" IEEE ECE 37, Analog Electronic-II [6] Maxiu Dall Sei conducter "rippe/dual/single-mode CDMA, LNA/Mixer application note" [7] P. Litanuen, P.IK Aluniern, K. Haloven "A 0HHz Subicron CMOS LNA and down converion ixer" exu intruent Inc..F. Wirele Deign 998 IEEE. [8] P.. Gray, P.J. Hart, S.H. Lewi, and.g Mayor, "Analyi and deign of analog integrated circuit", verion 4th Edn.,Newyork, wielly 00. pp [9] A.4 GHz LNA i 0.8/icron CMOS echnology "International Conference on VLSI counicationandintruentation ICUCI 0 Proceeding publihed by International Journal of Coputer Application (IJCA). [0] PM Webite (online available (ranitor) [].Lee, "he deign of radio frequency integrated circuit " econd edition, cabridge 998. [] Agilent echnologie, Web. [3] ECEN 665 (ESS) F Counication Circuit and Syte. [4] D.K. Shaeffer,.H. Lee, A.5V.5GHz CMOS Low Noie Aplifier, JSSC, Vol. 3, No. 5. May Page