22-NM CMOS DESIGN LIMITS

Transcription

1 EMCA report 22-NM CMOS DESIGN LIMITS Céline MATHIAS, 4th year in Automatic control and electronic systems engineering Year

2 22-NM CMOS DESIGN LIMITS Abstract: This project, supervised by Etienne SICARD professor at INSA Toulouse, relies on the study of 22-nm CMOS design compared with largest technologies CMOS. This report relates the different research that allowed me to better apprehend the CMOS technology and draw up a slideshow to explain how to make a good design. This project report will lead to an application note of the software Microwind, used for designing CMOS cells. «If we knew what we were doing, it wouldn't be called research, would it?» Albert Einstein ( ) 22-NM CMOS DESIGN LIMITS Page 2

3 Contents Contents Introduction... 5 Part 1: Back on the theory Mask and design result The origins of the variations between the original layout and its resulting design... 7 Part 2: Optical Proximity Corrections Introduction to OPC Examples... 8 Part 3: How to improve nano-cmos design Conclusion References NM CMOS DESIGN LIMITS Page 3

4 Table of figures Table of figures Figure 1. 1 : Example of a two-dimensional layout (left) and its resulting design (right). Several variations are visible Figure 1. 2: The illumination device... 7 Figure 2. 1: Example of a two-dimensional layout (top left) and its resulting design (top right). Several distortions are visible. OPC : hammer heads (bottom left) and the corrected design (bottom right)... 8 Figure 2. 2: Example of a two-dimensional layout (top left) and its resulting design (top right). Several distortions are visible. OPC : inner and outer corner rounding(bottom left) and the corrected design (bottom right)... 9 Figure 2. 3: Example of a two-dimensional layout (top left) and its resulting design (top right). Several distortions and a problem of electrical contact are visible. OPC : inner and outer corner rounding(bottom left) and the corrected design (bottom right)... 9 Figure 3. 1: example of design optimization in the case of a transistor Figure 3. 2 : the most important rules to better design NM CMOS DESIGN LIMITS Page 4

5 Introduction Introduction Complementary metal oxide semiconductor (CMOS) is a technology for constructing integrated circuits which is used in many fields like microprocessors, microcontrollers or image sensors [1]. In order to create chips ever smaller and efficient, scientists have to face physical problems to make possible the design. Indeed, below the micron scale, the rules of geometrical optics are no longer applicable. In the following paragraphs, I am going to introduce the various problems that can be encountered before putting forward the solutions that have been made. 22-NM CMOS DESIGN LIMITS Page 5

6 Part 1 : Back on the theory Part 1: Back on the theory In this fist part, I am going to present briefly some of the origins of the design problems under the micron scale by relying on an example. 1.1 Mask and design result Original layout Imaging result Figure 1. 1 : Example of a two-dimensional layout (left) and its resulting design (right). Several variations are visible. This figure highlights some of the various effects that can happen when the design is realized below the micron scale. In the following paragraph, some of the reasons of these differences are going to be explained. 22-NM CMOS DESIGN LIMITS Page 6

7 Part 1 : Back on the theory 1.2 The origins of the variations between the original layout and its resulting design Below the micron scale, the light used during the photolithography process has a wavelength whose order of magnitude is the same as the dimensions of the layout. Consequently, during the illumination phase (cf. Figure 1.2), the diffraction phenomenon causes significant variations like the lost of the image edges. [2] In order to optimize the design and to correct the distortions, the mask is modified until obtaining a result close to the desired pattern. These modifications are made according to specific rules based Optical Proximity Corrections (OPC). Other techniques of corrections based on iterative algorithms won t be detailed in this report.[3] However, it should be noted that on this scale of work, other factors may influence the achievement of design like the wafer quality or the converging lens. Thereby, only OPC may not always improve the result. 1 Figure 1. 2: The illumination device 1 Image source : [3] p NM CMOS DESIGN LIMITS Page 7

8 Part 2: Optical Proximity Corrections (OPC) Part 2: Optical Proximity Corrections In this part, the various rules based on OPC will be introduced before being applied on some simple examples. 2.1 Introduction to OPC In order to compensate the distortions, corrections are applied on an area of the layout. However, they could interfere with the adjacent patterns and then generate a catastrophic result. The principle of OPC is based on: -an assessment of proximity effects for the various patterns -an assessment of the interactions between the corrections Thereby, the nano-cmos get closer to the desired layout.[3] 2.2 Examples Design Problems: - branch width - branch length Characterization of process nonlinearities Solutions: - compensate by fitting the pattern - extend the pattern OPC Performance after correction Figure 2. 1: Example of a two-dimensional layout (top left) and its resulting design (top right). Several distortions are visible. OPC : hammer heads (bottom left) and the corrected design (bottom right) 22-NM CMOS DESIGN LIMITS Page 8

9 Part 2: Optical Proximity Corrections (OPC) Problems: - overflows at the corners - branch length Solutions: - reduce the width at the corners - extend the pattern Problems: - overflows at the corners causing an electrical contact - branch width - branch length Solutions: - reduce the width at the corners - compensate by fitting the pattern - extend the pattern 22-NM CMOS DESIGN LIMITS Page 9

10 Part 3: How to improve nano-cmos design Part 3: How to improve nano-cmos design 3.1.a : Bad design Reasons : Length too short 3.1.b : Good design Figure 3. 1: example of design optimization in the case of a transistor The following figures can illustrate the most important rules regarding good design. Bad design Good design 3.2.a Rule 1 : Not use the minimum size of width and length Bad design Good design 3.2.b Rule 2 :Take care of the distances in a corner 22-NM CMOS DESIGN LIMITS Page 10

11 Part 3: How to improve nano-cmos design Bad design Good design 3.2.c Rule 3 : Take care about the distances to limit the risks Figure 3. 2 : the most important rules to better design 22-NM CMOS DESIGN LIMITS Page 11

12 Conclusion Conclusion This report relates the various researches I have made concerning 22-NM CMOS DESIGN LIMITS. It is part from the course about Study and modeling of active components. I think this project allowed me to deepen my knowledge on microelectronics with an interesting way: to contribute in a research work. Contrary to usual practical work, a project involves us more. We gain autonomy while maintaining a certain structure. 22-NM CMOS DESIGN LIMITS Page 12

13 References References [1] Complementary metal oxide semi-conductor [Online]. In : Wikipedia. Available on : (last access on 03/04/2011) [2] WONG Ban P., et al. Nano-CMOS Circuit and Physical Design. Published by John Wiley & Sons, Inc. (2005). (IBSN ) [3] VEVE, Caroline. Optique pour la Microélectronique : du capteur au traitement de l image. [Online] Université Paul Cézanne-Aix Marseille III, 2009, 86p. Available on : (Last access on 28/04/2011) [4] WONG Ban P., et al. Nano-CMOS Design for Manufacturability. Published by John Wiley & Sons, Inc. (2009). (IBSN ) 22-NM CMOS DESIGN LIMITS Page 13