CMOS circuit design Simulator in hands

Transcription

1 Deep-submicron CMOS circuit design Simulator in hands Etienne Sicard Sonia Delmas Bendhia Version /04/03

2 Acknowledgements Jean-Pierre Schoellkopf, Joseph-Georges Ferrante, Amaury Soubeyran, Thomas Steineke, Lesia team, Chen Xi, Jianwen Huang, Fabrizio Battaglia, Bernard Courtois, Hubert Delori, Jean-Louis Noullet, Antonio Rubio, Kozo Kinoshita, Jean-Francois Habigand, Jean Buxo, Gert Voland. Our families, our parents. About the authors ETIENNE SICARD was born in Paris, France, in June He received a B.S degree in 1984 and a PhD in Electrical Engineering in 1987 both from the University of Toulouse. He was granted a Monbusho scholarship and stayed 18 months at the University of Osaka, Japan. Previously a professor of electronics in the department of physics, at the University of Balearic Islands, Spain, E. Sicard is currently professor at the INSA Electronic Engineering School of Toulouse. His research interests include several aspects of design of integrated circuits including crosstalk fault tolerance, and electromagnetic compatibility of integrated circuits. Etienne is the author of several educational software in the field of microelectronics and sound processing. Sonia DELMAS BENDHIA was born in Toulouse, April 1972, She received an engineering diploma in 1995, and the Ph.D. in Electronic Design from the National Institute of Applied Sciences, Toulouse, France, in Sonia Bendhia is currently a senior lecturer in the INSA of Toulouse, Department of Electrical and Computer Engineering. Her research interest include signal integrity in deep sub-micron CMOS Ics, analog design and electromagnetic compatibility of systems. Sonia is the author of technical papers concerning signal integrity and EMC. Etienne Sicard INSA-DGEI 135, Av de Rangueil TOULOUSE Cedex 4, FRANCE Tel : Fax: etienne.sicard@insa-tlse.fr web page: Sonia DELMAS BENDHIA INSA-DGEI 135, Av de Rangueil TOULOUSE Cedex 4, FRANCE Tel : Fax: sonia.bendhia@insa-tlse.fr web page: In memory of John Uyemura, died february 2003 "I have been learning the Microwind program, and are having a fun time-it is an excellent piece of work. I would encourage you two to complete the writing on your book as I think that it will receive a warm reception", John Uyemura, October /04/03

3 Chapter 1 Introduction Technology scale down Frequency Improvement Increased layers Reduced power supply Page 2 The MOS device The MOS Logic simulation of the MOS MOS layout Vertical aspect of the MOS Static MOS characteristics Dynamic MOS behavior Analog simulation Mos options Transmission gate: the perfect switch Layout considerations 3 MOS modeling The MOS model 1 The MOS model 3 The model BSIM4 Temperature effects on the MOS High frequency behavior of the MOS 4 The Inverter The logic Inverter The CMOS inverter (Power, supply, frequency) Layout design (plasma, latchup) Simulation of the inverter Views of the process Buffer 3-state inverter Analog behavior of the inverter Ring oscillator Temperature effects 3 05/04/03

4 5 Interconnects Signal propagation Capacitance load Resistance effect Inductance effect Buffers Clock tree Supply routing 6 Basic Gates Introduction From boolean expression to layout NAND gate (micron, sub-micron) OR3 gate XOR Complex gates Multiplexors (Mux-demux) Pulse generator 7 Arithmetics Data formats: unsigned, signed fixed Half adder gate Full adder gate 4-bit adder Comparator Multiplier ALU Low power arithmetics 8 Latches RS latch D-Latch Edge-trigged latch Latch optimization (conso, speed, fanout) Counter Project: programmable pulse generator 9 FPGA Goals Mux for FPGA Configurable logic block Look-up table Interconnection Programmable Interconnection Points Propagation delay 10 MEMORIES The world of Memories Static RAM memory (4T, 6T) Decoder (low power) Dynamic RAM memory Embedded RAM Sense ampli ROM memory 4 05/04/03

5 EEPROM memory FRAM memory 11 Analog Cells Diode connected MOS Voltage reference Current Mirror Amplifiers (Class) Voltage regulator Wide range amplifier Charge pump Noise 12 RF Analog Cells Osc illators Inductors Sample & Hold Mixers Voltage-controlled Oscillators PLL project Power amplifiers 13 Converters Introduction Converter parameters Sample hold ADC DAC 14 Input/Output Interfacing Level shifter Pad stucture Input pad (schmidt, protect, buffer) Output pad (log, analog, multi drive) Pad ring Packages IBIS LVDS High performance Ios 15 SOI Layout improvements 2D aspects SOI model Simulation Issues 16 Future & Conclusion Appendix A Design rules Appendix B List of commands Microwind Appendix C List of commands Dsch Appendix D Appendix E Quick Reference Sheet Microwind-Dsch CMOS technology reference Sheet 0.8µm 0.6µm 0.35µm 0.25µm 5 05/04/03

6 Appendix F 0.18µm 0.12µm 90nm Answer to exercises 6 05/04/03

7 INTRODUCTION TO DEEP SUBMICRON CMOS DESIGN 1. Introduction Glossary Back-End CMOS Deep technology Front-End MOS submicron Interconnect fabrication steps. Complementary - Metal - Oxide - Semi-conductor. Basic name for the technology used to fabricate N-channel and P-channel MOS transistors. Lithography lower than 0.5 µm, including the 0.35µm process (1996), 0.25µm (1998) and 0.18 µm (1999). MOS device fabrication steps. Abbreviation for Metal - Oxide - Semiconductor, representing the elementary transistor. The MOS exists in two versions: one with N channel, one with P channel. The early metal gate has been replaced by polysilicon. 1 Logic level considered as 1. In CMOS design, a logic level 1 is a voltage significantly higher than VDD/2. 0 Logic level considered as 0. In CMOS design, a logic level 0 is a voltage significantly lower than VDD/2. Lithography SOI Ultra Deep submicron technology The smallest fabricated pattern. This dimension is roughly the distance between the drain and source of the transistor. It is also call the «technology». For example, the Pentium III is fabricated in 0.18µm technology, that is a lithography of around 0.18µm. Silicon on Insulator. Very promising technological enhancement, featuring important speed improvement and compact cell layout. Lithography lower than 0.18 µm, including the 0.12µm process (2000), 0.10µm (2002) and 0.07 µm (2004). VDD Power supply. Never stops decreasing with technology. VDD is 2.5V in 0.25µm technology. VSS TBD 7 05/04/03

8 INTRODUCTION TO DEEP SUBMICRON CMOS DESIGN 1. Introduction MULTIPLIERS Value Name Standard PETA P EXA E TERA T 10 9 GIGA G 10 6 MEGA M 10 3 KILO K MILLI m 10-6 MICRO u 10-9 NANO n PICO p FEMTO f ATTO a ZEPTO z Notation PHYSICAL CONSTANTS & PARAMETERS Name Value Description? e -14 Farad/cm Vacuum dielectric constant? r SiO Relative dielectric constant of SiO 2? r Si 11.8 Relative dielectric constant of silicon? r ceramic 12 Relative dielectric constant of ceramic k 1.381e -23 J/ K Bolztmann s constant q 1.6e -19 Coulomb Electron charge? n 600 V.cm -2 Mobility of electrons in silicon? p 270 V.cm -2 Mobility of holes in silicon? al S/m Aluminum conductivity? si 4x10-4 S/m Silicon conductivity n i 1.02x10 10 cm -3 Intrinsic carrier concentration in silicon at 300 K? al ?.µm Aluminum resistivity? cu 58x10 6 S/m Copper conductivity? cu ?.µm Copper resistivity? tungstène (W) ?.µm Tungsten resistivity? or (Ag) ?.µm Gold resistivity? e -6 H/m Vacuum permeability T 300 K (27 C) Operating temperature 8 05/04/03

9 INTRODUCTION TO DEEP SUBMICRON CMOS DESIGN 1. Introduction Preface The present book introduces the design and simulation of CMOS integrated circuits, in an attractive way thanks to user-friendly PC tool Microwind2 given in the companion CD-ROM of this book. The chapters of this book have been summarized below. Chapter One describes the technology scale down and the major improvements given by deep sub-micron technologies. Chapter Two is dedicated to the presentation of the single MOS device, with details on the device modeling, simulation at logic and layout levels. Chapter Three presents the CMOS Inverter, the 2D and 3D views, the comparative design in micron and deep-submicron technologies. Chapter Four concerns the basic logic gates (AND, OR, XOR, complex gates), Chapter Five the arithmetic functions (Adder, comparator, multiplier, ALU) and describes a student project concerning a 4-bit binary to Decimal adder. The latches and memories are detailed in Chapter Six. As for Chapter seven, analog cells are presented, including voltage references, current mirrors, operational amplifiers and phase lock loops. Chapter eight concerns analog-to-digital and digital to analog converter principles. Chapter Nine deals specifically with interconnect, with information on the propagation delay and crosstalk effects. The input/output interfacing principles are illustrated in Chapter 10. The detailed explanation of the design rules is in appendix A. The program operation and the details of all commands are given in appendix B. A quick reference sheet is reported in appendix C. Sonia DELMAS-BENDHIA, Etienne SICARD Toulouse, June /04/03

10 INTRODUCTION TO DEEP SUBMICRON CMOS DESIGN 1. Introduction 10 05/04/03