Hard Disk Drive Industry Driving Areal Density and Lithography
|
|
- Kory Wade
- 5 years ago
- Views:
Transcription
1 Hard Disk Drive Industry Driving Areal Density and Lithography September 18, 2008 Paul Hofemann Molecular Imprints
2 Global Demand for Digital Storage Worldwide population penetration Internet at 20% PC at 13% Cell phone at 13% Density demands growing 10 6 X s average 10 KB each Movies reaching 10 GB each China and India s middle class to grow 7-10X to 1.6 billion by 2020 Source: Samsung Presentation August 2008
3 HDD Offers the Best Capacity, Cost, Density Source: Samsung, August 2008, Santa Clara, CA
4 HDD Areal Density Industry Roadmap Areal Density (Gbit/in 2 ) 10,000 1, GMR - Longitudinal Recording TMR Today CPP Perpendicular Recording DTM BPM Heat Assisted Patterned media using imprint lithography TFH and PMR using evolutionary process equipment
5 The Road to 1 Tb/in 2 Areal Density and Beyond 10,000 BPM 25nm Pillars Areal Density (Gbit/in 2 ) 1, DTR 35nm Track Width
6 What is Different About This Transition? Requires lithography beyond the most aggressive International Technology for Semiconductors (ITRS) roadmap Introduces processes (e.g., litho and etch) that are not currently in the disk media production fabs Requires unprecedented collaboration and coordination amongst suppliers and customers
7 HDD Leading the ITRS Lithography Resolution Roadmap HDD TFH NAND FLASH Today Patt. Media and must accomplish this at less than 1/10 th the cost! Sources: ITRS Roadmap (FLASH) ; Tom Coughlin Assoc. May 08 (TFH)
8 Proposed Lithography Roadmap for Patterned Media A trillion bit features/in 2 must be printed at low cost in high volume manufacturing in a few short years!
9 Introduction to Molecular Imprints: S-FIL Imprint Lithography Molecular Imprints Imprio HD2200 Sub-20nm resolution today Limited by template resolution Double-sided at high throughput Imprint head modules can be clustered to scale to >1,000 dph Low cost of ownership Inkjet dispensed resist with ~zero waste Technology supports areal densities beyond 1 Tb/in 2
10 S-FIL Technology Inkjet Dispense
11 S-FIL Technology Template Contacts Resist
12 S-FIL Technology Capillary Forces Fill Template
13 S-FIL Technology Resist Exposure
14 S-FIL Technology Template Separation
15 15 Thin Uniform Residual Layer Thickness for Superior Etch Process Yield
16 Patterned Media Imprint Examples DTR - 50nm half pitch Servo Patterns BPM - 25nm half pitch Resist Pillars
17 High Throughput Double-Sided Patterning Robot Cassettes Process Module Templates Process Module GUI Imprio HD2200 Pilot-line Capable Note: Timing and sequencing is an illustration only
18 Molecular Imprints PM Lithography Roadmap Areal Density (Gb/In 2 Production) Imprio HD1100 R&D 60 dph single-sided sided system Early development Imprio HD2200 Pilot 180 dph double-sided system Improved system robustness High Volume Manufacturing Production 360 dph base system with cluster configurations for scalable throughput beyond 1,000 dph Improved yields, automation, RLT performance
19 Master and Working Replicate Templates Standard 6-inch round fused silica substrate Rotary e-beam generates master patterned template Imprint lithography transfers pattern to working replicates Commercial mask shops ideally suited for this role
20 Master and Working Replicate Templates One Master 10,000 Template Replicates 100 million disks Rotary E-beam Writer MII Template Replicator Imprio HD2200 One master by rotary-stage e- beam writer Replicate master into working replicas Each working replica template imprints 10,000 disks 20
21 How Small Can Imprint Lithography Print? Imprint lithography resolution is ultimately determined by the resolution on the template 2.4nm carbon nanotube is adhered to a template Imprint clearly shows the replication of the CNT feature Source J. A. Rogers F. Hua, Y. Sun, A. Gaur, M. A. Meitl, L. Bilhaut, L. Rotkina, J. Wang, P. Geil, M. Shim, and, Nanoletters, Vol. 4, No. 12, , 2004
22 Disk Media Manufacturing Process Flow Wash Sputter COC Lube Burnish Flight Test Manufacturing Flow Wash Planarization Imprint Coating Resist Strip Imprint Etch Today s Unpatterned Media: $4 to $6/disk Patterned Media Added Cost: $1 to $2/disk
23 Unprecedented Industry Coordination and Collaboration is Required Template Supply Other Materials Supplier Interaction Yield Mgmt New chemicals Std cassettes Std SMIF pods Automation protocol Coupled processes: Imprint coating Imprint lithography Etch Defect detection & classification gaps Implementation strategy (i.e., binning, process monitoring)
24 Unprecedented Industry Coordination and Collaboration is Required HDD Industry Must Standardize When Possible The industry cannot afford 7 dramatically different manufacturing solutions for 7 media manufacturers!
25 Opportunities for Industry Coordination Non-proprietary template pattern for process integration and tool development Advanced Pitch DTR, Skewed Servo Tracks Test Template Substrate handling Automation/material WIP protocols (i.e., template RFID tracking) Cassettes and SMIF pods Disk Carrier Template SMIF Yield management Identify and close tool gaps in defect detection and classification Optimized process tool specifications (perfection is expensive)
26 Next Year s Pilot Lines Will Be Busy! Many OEMs will be shipping 1 st generation process tools Process refinement and integration will require close collaboration Increased focus on integration, cost of ownership and yield More manufacturing personnel are getting involved good sign! HDD manufacturers picking areal density points for first pattern media products New litho/etch talent will be appearing in media fabs
27 Patterned Media Industry Adoption Forecast
28 Hard Disk Drive Industry Driving Areal Density and Lithography! Global demand for digital storage will continue to motivate the HDD industry s areal density progress Patterned media provides technical roadmap beyond 1 Tb/in 2 Imprint lithography enables remarkable sub-20nm resolution at extraordinary low cost Unprecedented collaboration and coordination will be necessary for a timely and efficient patterned media transition
From Possible to Practical The Evolution of Nanoimprint for Patterned Media
From Possible to Practical The Evolution of Nanoimprint for Patterned Media Paul Hofemann March 13, 2009 HDD Areal Density Industry Roadmap 10,000 Media Technology Roadmap Today Areal Density (Gbit/in
More informationUV Nanoimprint Stepper Technology: Status and Roadmap. S.V. Sreenivasan Sematech Litho Forum May 14 th, 2008
UV Nanoimprint Stepper Technology: Status and Roadmap S.V. Sreenivasan Sematech Litho Forum May 14 th, 2008 Overview Introduction Stepper technology status: Patterning and CD Control Through Etch Alignment
More informationPERPENDICULAR FILM HEAD PROCESSING PERSPECTIVES FOR AREAL DENSITY INCREASES
PERPENDICULAR FILM HEAD PROCESSING PERSPECTIVES FOR AREAL DENSITY INCREASES R. E. Fontana, Jr., N. Robertson, M.C. Cyrille, J. Li, J. Katine San Jose Research Center Hitachi Global Storage Technologies
More informationProgresses in NIL Template Fabrication Naoya Hayashi
Progresses in NIL Template Fabrication Naoya Hayashi Electronic Device Operations Dai Nippon Printing Co., Ltd. Contents 1. Introduction Motivation NIL mask fabrication process 2. NIL mask resolution improvement
More informationPerpendicular Media - Metrology and Inspection Challenges. Sri Venkataram KLA-Tencor Corporation Sept 19, 2007
Perpendicular Media - Metrology and Inspection Challenges Sri Venkataram KLA-Tencor Corporation Sept 19, 2007 Agenda Perpendicular Media Adoption PMR Metrology & Inspection Implementation Solutions Review
More informationHDD Technology Trends
R e s e a r c h HDD Technology Trends Dr. Richard New Director of Research Hitachi Global Storage Technologies HDD Technology Challenges Storage Technology Capabilities Storage Usage Requirements Storage
More informationTemplates, DTR and BPM Media
Complete Metrology Solutions Imprint Technology Templates, DTR and BPM Media Simultaneous and Non-Destructive Measurements of Depth Top and Bottom CD Residual Layer Thickness, RLT DLC Thickness Side Wall
More information450mm patterning out of darkness Backend Process Exposure Tool SOKUDO Lithography Breakfast Forum July 10, 2013 Doug Shelton Canon USA Inc.
450mm patterning out of darkness Backend Process Exposure Tool SOKUDO Lithography Breakfast Forum 2013 July 10, 2013 Doug Shelton Canon USA Inc. Introduction Half Pitch [nm] 2013 2014 2015 2016 2017 2018
More informationTWINSCAN XT:1950i Water-based immersion taken to the max Enabling fast, single-exposure lithography at sub 40 nm
TWINSCAN XT:1950i Water-based immersion taken to the max Enabling fast, single-exposure lithography at sub 40 nm SEMICON West, San Francisco July 14-18, 2008 Slide 1 The immersion pool becomes an ocean
More informationStrategies for low cost imprint molds
Strategies for low cost imprint molds M.P.C. Watts, Impattern Solutions, 9404 Bell Mountain Drive Austin TX 78730 www.impattern.com ABSTRACT The Cost of ownership (COO) due to the mold can be minimized
More informationPart 5-1: Lithography
Part 5-1: Lithography Yao-Joe Yang 1 Pattern Transfer (Patterning) Types of lithography systems: Optical X-ray electron beam writer (non-traditional, no masks) Two-dimensional pattern transfer: limited
More informationElectron Multi-Beam Technology for Mask and Wafer Direct Write. Elmar Platzgummer IMS Nanofabrication AG
Electron Multi-Beam Technology for Mask and Wafer Direct Write Elmar Platzgummer IMS Nanofabrication AG Contents 2 Motivation for Multi-Beam Mask Writer (MBMW) MBMW Tool Principles and Architecture MBMW
More informationHolistic View of Lithography for Double Patterning. Skip Miller ASML
Holistic View of Lithography for Double Patterning Skip Miller ASML Outline Lithography Requirements ASML Holistic Lithography Solutions Conclusions Slide 2 Shrink Continues Lithography keeps adding value
More informationDevelopment of Nanoimprint Mold Using JBX-9300FS
Development of Nanoimprint Mold Using JBX-9300FS Morihisa Hoga, Mikio Ishikawa, Naoko Kuwahara Tadahiko Takikawa and Shiho Sasaki Dai Nippon Printing Co., Ltd Research & Development Center Electronic Device
More informationHigh Throughput Jet and Flash* Imprint Lithography for semiconductor memory applications. Abstract
High Throughput Jet and Flash* Imprint Lithography for semiconductor memory applications Wei Zhang, Brian Fletcher, Ecron Thompson, Weijun Liu, Tim Stachowiak, Niyaz Khusnatdinov, J. W. Irving, Whitney
More informationLecture 7. Lithography and Pattern Transfer. Reading: Chapter 7
Lecture 7 Lithography and Pattern Transfer Reading: Chapter 7 Used for Pattern transfer into oxides, metals, semiconductors. 3 types of Photoresists (PR): Lithography and Photoresists 1.) Positive: PR
More informationTECHNOLOGY ROADMAP 2006 UPDATE LITHOGRAPHY FOR
INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2006 UPDATE LITHOGRAPHY THE ITRS IS DEVISED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND IS WITHOUT REGARD TO ANY COMMERCIAL CONSIDERATIONS PERTAINING
More informationNANOELECTRONIC TECHNOLOGY: CHALLENGES IN THE 21st CENTURY
NANOELECTRONIC TECHNOLOGY: CHALLENGES IN THE 21st CENTURY S. M. SZE National Chiao Tung University Hsinchu, Taiwan And Stanford University Stanford, California ELECTRONIC AND SEMICONDUCTOR INDUSTRIES
More informationExhibit 2 Declaration of Dr. Chris Mack
STC.UNM v. Intel Corporation Doc. 113 Att. 5 Exhibit 2 Declaration of Dr. Chris Mack Dockets.Justia.com UNITED STATES DISTRICT COURT DISTRICT OF NEW MEXICO STC.UNM, Plaintiff, v. INTEL CORPORATION Civil
More informationCost of Ownership Analysis for Patterning Using Step and Flash Imprint Lithography
Cost of Ownership Analysis for Patterning Using Step and Flash Imprint Lithography S.V. Sreenivasan 1, C.G. Willson 2, N.E. Schumaker 3, D.J. Resnick 4 1 Mechanical Engineering, University of Texas at
More informationApplications of Maskless Lithography for the Production of Large Area Substrates Using the SF-100 ELITE. Jay Sasserath, PhD
Applications of Maskless Lithography for the Production of Large Area Substrates Using the SF-100 ELITE Executive Summary Jay Sasserath, PhD Intelligent Micro Patterning LLC St. Petersburg, Florida Processing
More informationHigh-performance wire-grid polarizers using jet and Flash imprint lithography
High-performance wire-grid polarizers using jet and Flash imprint lithography Se Hyun Ahn Shuqiang Yang Mike Miller Maha Ganapathisubramanian Marlon Menezes Jin Choi Frank Xu Douglas J. Resnick S. V. Sreenivasan
More informationEnabling Areal Density Growth
Shrinking the Magnetic Spacing for Advanced PMR Heads Diskcon Asia 2007 Enabling Areal Density Growth Shrinking the magnetic spacing remains one of the biggest levers for areal density growth! Areal Density
More informationSMART LASER SENSORS SIMPLIFY TIRE AND RUBBER INSPECTION
PRESENTED AT ITEC 2004 SMART LASER SENSORS SIMPLIFY TIRE AND RUBBER INSPECTION Dr. Walt Pastorius LMI Technologies 2835 Kew Dr. Windsor, ON N8T 3B7 Tel (519) 945 6373 x 110 Cell (519) 981 0238 Fax (519)
More informationEvaluation of the Imprio 100 Step and Flash Imprint Lithography Tool
Evaluation of the Imprio 100 Step and Flash Imprint Lithography Tool Kathleen A. Gehoski, David P. Mancini, Douglas J. Resnick Microelectronics and Physical Sciences Laboratories, Motorola Labs, Tempe,
More informationISMI 450mm Transition Program
SEMATECH Symposium Taiwan September 7, 2010 Accelerating Manufacturing Productivity ISMI 450mm Transition Program Scott Kramer VP Manufacturing Technology SEMATECH Copyright 2010 SEMATECH, Inc. SEMATECH,
More informationAdvanced Patterning Techniques for 22nm HP and beyond
Advanced Patterning Techniques for 22nm HP and beyond An Overview IEEE LEOS (Bay Area) Yashesh A. Shroff Intel Corporation Aug 4 th, 2009 Outline The Challenge Advanced (optical) lithography overview Flavors
More informationIntel Technology Journal
Volume 06 Issue 02 Published, May 16, 2002 ISSN 1535766X Intel Technology Journal Semiconductor Technology and Manufacturing The Intel Lithography Roadmap A compiled version of all papers from this issue
More informationDefect inspection of imprinted 32 nm half pitch patterns
Defect inspection of imprinted 32 nm half pitch patterns Kosta Selinidis, Ecron Thompson, Ian McMackin, Joseph Perez, S.V. Sreenivasan, Douglas J. Resnick Molecular Imprints, Inc., 1807 West Braker Lane,
More informationMultiple Patterning for Immersion Extension and EUV Insertion. Chris Bencher Distinguished Member of Technical Staff Applied Materials CTO group
Multiple Patterning for Immersion Extension and EUV Insertion Chris Bencher Distinguished Member of Technical Staff Applied Materials CTO group Abstract Multiple Patterning for Immersion Extension and
More informationLithography. Development of High-Quality Attenuated Phase-Shift Masks
Lithography S P E C I A L Development of High-Quality Attenuated Phase-Shift Masks by Toshihiro Ii and Masao Otaki, Toppan Printing Co., Ltd. Along with the year-by-year acceleration of semiconductor device
More information450mm silicon wafers specification challenges. Mike Goldstein Intel Corp.
450mm silicon wafers specification challenges Mike Goldstein Intel Corp. Outline Background 450mm transition program 450mm silicon evolution Mechanical grade wafers (spec case study) Developmental (test)
More information(Complementary E-Beam Lithography)
Extending Optical Lithography with C E B L (Complementary E-Beam Lithography) July 13, 2011 4008 Burton Drive, Santa Clara, CA 95054 Outline Complementary Lithography E-Beam Complements Optical Multibeam
More informationIt s Time for 300mm Prime
It s Time for 300mm Prime Iddo Hadar Managing Director, 300mm Prime Program Office SEMI Strategic Business Conference Napa Valley, California Tuesday, April 24, 2007 Safe Harbor Statement This presentation
More informationCompetitive in Mainstream Products
Competitive in Mainstream Products Bert Koek VP, Business Unit manager 300mm Fabs Analyst Day 20 September 2005 ASML Competitive in mainstream products Introduction Market share Device layers critical
More informationLow-Cost Nanostructure Patterning Using Step and Flash Imprint Lithography
Low-Cost Nanostructure Patterning Using Step and Flash Imprint Lithography S.V. Sreenivasan 1, C.G. Willson 2, N.E. Schumaker 3, D.J. Resnick 4 1 Mechanical Engineering, University of Texas at Austin 2
More informationProspects of Optical Recording in Tera Era. Han-Ping D. Shieh
Prospects of Optical Recording in Tera Era Han-Ping D. Shieh Inst. of Electro-Optical Engineering Nat l Chiao Tung University Hsinchu, Taiwan 30010 e-mail: hpshieh@cc.nctu.edu.tw Disk Storage Roadmap $/MB
More informationCMOL: Hybrid of CMOS with Overlaid Nanogrid and Nanodevice Structure. John Zacharkow
CMOL: Hybrid of CMOS with Overlaid Nanogrid and Nanodevice Structure John Zacharkow Overview Introduction Background CMOS Review CMOL Breakdown Benefits/Shortcoming Looking into the Future Introduction
More informationCRITICAL DIMENSION CONTROL, OVERLAY, AND THROUGHPUT BUDGETS IN UV NANOIMPRINT STEPPER TECHNOLOGY
CRITICAL DIMENSION CONTROL, OVERLAY, AND THROUGHPUT BUDGETS IN UV NANOIMPRINT STEPPER TECHNOLOGY S.V. Sreenivasan 1, 2, P.D. Schumaker 2, B.J. Choi 2 1 Department of Mechanical Engineering University of
More informationInkjet resist inks. Krishna Balantrapu
Inkjet resist inks Krishna Balantrapu OUTLINE Conventional Vs. Inkjet-Cost Savings Inkjet Material Design Inkjet Equipment-Lunaris Future work 2 DOW-R&D DRIVERS FOR NEW PRODUCT DEVELOPMENT Technology Need
More informationIMPACT OF 450MM ON CMP
IMPACT OF 450MM ON CMP MICHAEL CORBETT MANAGING PARTNER LINX CONSULTING, LLC MCORBETT@LINX-CONSULTING.COM PREPARED FOR CMPUG JULY 2011 LINX CONSULTING Outline 1. Overview of Linx Consulting 2. CMP Outlook/Drivers
More informationISSCC 2003 / SESSION 1 / PLENARY / 1.1
ISSCC 2003 / SESSION 1 / PLENARY / 1.1 1.1 No Exponential is Forever: But Forever Can Be Delayed! Gordon E. Moore Intel Corporation Over the last fifty years, the solid-state-circuits industry has grown
More informationINSPECTION AND REVIEW PORTFOLIO FOR 3D FUTURE
INSPECTION AND REVIEW PORTFOLIO FOR 3D FUTURE This week announced updates to four systems the 2920 Series, Puma 9850, Surfscan SP5 and edr-7110 intended for defect inspection and review of 16/14nm node
More informationA process for, and optical performance of, a low cost Wire Grid Polarizer
1.0 Introduction A process for, and optical performance of, a low cost Wire Grid Polarizer M.P.C.Watts, M. Little, E. Egan, A. Hochbaum, Chad Jones, S. Stephansen Agoura Technology Low angle shadowed deposition
More informationPlan Optik AG. Plan Optik AG PRODUCT CATALOGUE
Plan Optik AG Plan Optik AG PRODUCT CATALOGUE 2 In order to service the high demand of wafers more quickly, Plan Optik provides off the shelf products in sizes from 2 up to 300mm diameter. Therefore Plan
More informationNano-imprinting Lithography Technology
Nano-imprinting Lithography Technology Agenda Limitation of photolithograph - Remind of photolithography technology - What is diffraction - Diffraction limit Concept of nano-imprinting lithography Basic
More informationChanging the Approach to High Mask Costs
Changing the Approach to High Mask Costs The ever-rising cost of semiconductor masks is making low-volume production of systems-on-chip (SoCs) economically infeasible. This economic reality limits the
More informationBank of America Merrill Lynch Taiwan, Technology and Beyond Conference
Bank of America Merrill Lynch Taiwan, Technology and Beyond Conference Craig De Young Vice President Investor Relations Taipei, Taiwan March 12, 2013 Forward looking statements Slide 2 Safe Harbor Statement
More informationLecture: Integration of silicon photonics with electronics. Prepared by Jean-Marc FEDELI CEA-LETI
Lecture: Integration of silicon photonics with electronics Prepared by Jean-Marc FEDELI CEA-LETI Context The goal is to give optical functionalities to electronics integrated circuit (EIC) The objectives
More informationMarket and technology trends in advanced packaging
Close Market and technology trends in advanced packaging Executive OVERVIEW Recent advances in device miniaturization trends have placed stringent requirements for all aspects of product manufacturing.
More informationHolographic Drive and Media Developments at InPhase Technologies
Holographic Drive and Media Developments at InPhase Technologies Tom Wilke InPhase Technologies 2000 Pike Road, Longmont, Colorado 80501 Phone: 303-684-3631 FAX: 720-494-7432 E-mail: tomwilke@inphase-tech.com
More informationThe Development of the Semiconductor CVD and ALD Requirement
The Development of the Semiconductor CVD and ALD Requirement 1 Linx Consulting 1. We create knowledge and develop unique insights at the intersection of electronic thin film processes and the chemicals
More information32nm High-K/Metal Gate Version Including 2nd Generation Intel Core processor family
From Sand to Silicon Making of a Chip Illustrations 32nm High-K/Metal Gate Version Including 2nd Generation Intel Core processor family April 2011 1 The illustrations on the following foils are low resolution
More informationThe Future for Printed Electronics
The Future for Printed Electronics Jon Helliwell National Centre for Printable Electronics 24 October, 2013 Copyright CPI 2013. All rights reserved What is Printed Electronics? Organic and printed electronics
More informationCorrelation of Wafer Backside Defects to Photolithography Hot Spots Using Advanced Macro Inspection
Correlation of Wafer Defects to Photolithography Hot Spots Using Advanced Macro Inspection Alan Carlson* a, Tuan Le* a a Rudolph Technologies, 4900 West 78th Street, Bloomington, MN, USA 55435; Presented
More informationInspection of templates for imprint lithography
Inspection of templates for imprint lithography Harald F. Hess, a) Don Pettibone, David Adler, and Kirk Bertsche KLA-Tencor 160 Rio Robles, San Jose, California 95134 Kevin J. Nordquist, David P. Mancini,
More informationCorrecting Image Placement Errors Using Registration Control (RegC ) Technology In The Photomask Periphery
Best Paper of EMLC 2012 Correcting Image Placement Errors Using Registration Control (RegC ) Technology In The Photomask Periphery Avi Cohen 1, Falk Lange 2 Guy Ben-Zvi 1, Erez Graitzer 1, Dmitriev Vladimir
More informationNewer process technology (since 1999) includes :
Newer process technology (since 1999) includes : copper metalization hi-k dielectrics for gate insulators si on insulator strained silicon lo-k dielectrics for interconnects Immersion lithography for masks
More informationScaling of Semiconductor Integrated Circuits and EUV Lithography
Scaling of Semiconductor Integrated Circuits and EUV Lithography ( 半導体集積回路の微細化と EUV リソグラフィー ) December 13, 2016 EIDEC (Emerging nano process Infrastructure Development Center, Inc.) Hidemi Ishiuchi 1 OUTLINE
More informationClosed Loop Registration Control (RegC ) Using PROVE as the Data Source for the RegC Process
Invited Paper Closed Loop Registration Control (RegC ) Using PROVE as the Data Source for the RegC Process Erez Graitzer 1 ; Avi Cohen 1 ; Vladimir Dmitriev 1 ; Itamar Balla 1 ; Dan Avizemer 1 Dirk Beyer
More informationAdvanced Plasma Technology. High precision film thickness trimming for the TFH industry. Roth & Rau AG September 2009
Advanced Plasma Technology High precision film thickness trimming for the TFH industry Roth & Rau AG September 2009 Product Overview IonScan Equipment for ultra-precise Surface Processing IonScan 800 Wafer
More informationCore Business: Semiconductor-related Inspection Equipment
Core Business: Semiconductor-related Inspection Equipment Lasertec manufactures unique inspection and measurement systems that incorporate the cutting-edge technologies of applied optics and offers them
More informationIDeAL program : DSA activity at LETI. S. Tedesco R. Tiron L. Pain
IDeAL program : DSA activity at LETI S. Tedesco R. Tiron L. Pain Outline Why DSA for microelectronics The IDeAL progam Graphoepitaxy of BCP Contact hole application 300 mm pilot line in LETI Conclusion
More informationG450C. Global 450mm Consortium at CNSE. Michael Liehr, General Manager G450C, Vice President for Research
Global 450mm Consortium at CNSE Michael Liehr, General Manager G450C, Vice President for Research - CNSE Overview - G450C Vision - G450C Mission - Org Structure - Scope - Timeline The Road Ahead for Nano-Fabrication
More informationMask Fabrication For Nanoimprint Lithography
Mask Fabrication For Nanoimprint Lithography Doug Resnick Canon Nanotechnologies 1807C W. Braker Lane Austin, TX 78758 * dresnick@cnt.canon.com Template (Imprint Mask) Fabrication: Outline E-beam and Etch
More informationMAPPER: High throughput Maskless Lithography
MAPPER: High throughput Maskless Lithography Marco Wieland CEA- Leti Alterative Lithography workshop 1 Today s agenda Introduction Applications Qualification of on-tool metrology by in-resist metrology
More informationChallenges of EUV masks and preliminary evaluation
Challenges of EUV masks and preliminary evaluation Naoya Hayashi Electronic Device Laboratory Dai Nippon Printing Co.,Ltd. EUV Mask Workshop 2004 1 Contents Recent Lithography Options on Roadmap Challenges
More informationEUV Supporting Moore s Law
EUV Supporting Moore s Law Marcel Kemp Director Investor Relations - Europe DB 2014 TMT Conference London September 4, 2014 Forward looking statements This document contains statements relating to certain
More informationEMERGING SUBSTRATE TECHNOLOGIES FOR PACKAGING
EMERGING SUBSTRATE TECHNOLOGIES FOR PACKAGING Henry H. Utsunomiya Interconnection Technologies, Inc. Suwa City, Nagano Prefecture, Japan henryutsunomiya@mac.com ABSTRACT This presentation will outline
More informationLithography. International SEMATECH: A Focus on the Photomask Industry
Lithography S P E C I A L International SEMATECH: A Focus on the Photomask Industry by Wally Carpenter, International SEMATECH, Inc. (*IBM Corporation Assignee) It is well known that the semiconductor
More informationPhotoresists & Ancillaries. Materials for Semiconductor Manufacturing A TECHCET Critical Materials Report
2018-19 Photoresists & Ancillaries Materials for Semiconductor Manufacturing A TECHCET Critical Materials Report Prepared by Ed Korczynski Reviewed and Edited by Lita Shon-Roy TECHCET CA LLC PO Box 3814
More informationThe future of lithography and its impact on design
The future of lithography and its impact on design Chris Mack www.lithoguru.com 1 Outline History Lessons Moore s Law Dennard Scaling Cost Trends Is Moore s Law Over? Litho scaling? The Design Gap The
More informationISMI Industry Productivity Driver
SEMATECH Symposium Japan September 15, 2010 Accelerating Manufacturing Productivity ISMI Industry Productivity Driver Scott Kramer VP Manufacturing Technology SEMATECH Copyright 2010 SEMATECH, Inc. SEMATECH,
More informationIn pursuit of high-density storage class memory
Edition October 2017 Semiconductor technology & processing In pursuit of high-density storage class memory A novel thermally stable GeSe-based selector paves the way to storage class memory applications.
More informationPublic. Introduction to ASML. Ron Kool. SVP Corporate Strategy and Marketing. March-2015 Veldhoven
Public Introduction to ASML Ron Kool SVP Corporate Strategy and Marketing March-2015 Veldhoven 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012
More informationASML Market dynamics. Dave Chavoustie EVP Sales Analyst Day, September 30, 2004
ASML Market dynamics Dave Chavoustie EVP Sales Analyst Day, September 30, 2004 Agenda! Market Overview! Growth Opportunities! 300mm Market! Asia Overview / Slide 2 ASML Unit Market Share Trend 60% 12 &
More informationCLUSTERLINE RAD VERSATILE DYNAMIC SPUTTER SYSTEM OPTOELECTRONICS, MEMS, PHOTONICS, WIRELESS
CLUSTERLINE RAD VERSATILE DYNAMIC SPUTTER SYSTEM OPTOELECTRONICS, MEMS, PHOTONICS, WIRELESS CLUSTERLINE RAD Enabling your roadmap in thin film deposition The combination of Evatec s process know-how and
More informationLecture 0: Introduction
Lecture 0: Introduction Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): bucketloads! Complementary Metal Oxide Semiconductor Fast, cheap, low power
More information(a) (d) (e) (b) (c) (f) 3D-NAND Flash and Its Manufacturing Process
3D-NAND Flash and Its Manufacturing Process 79 (d) Si Si (b) (c) (e) Si (f) +1-2 (g) (h) Figure 2.33 Top-down view in cap oxide and (b) in nitride_n-2; (c) cross-section near the top of the channel; top-down
More informationTECHNOLOGY ROADMAP 2011 EDITION LITHOGRAPHY FOR
INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2011 EDITION LITHOGRAPHY THE ITRS IS DEVISED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND IS WITHOUT REGARD TO ANY COMMERCIAL CONSIDERATIONS PERTAINING
More informationINTERNATIONAL TECHNOLOGY ROADMAP SEMICONDUCTORS 2001 EDITION LITHOGRAPHY FOR
INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2001 EDITION LITHOGRAPHY TABLE OF CONTENTS Scope...1 Difficult Challenges...1 Lithography Technology Requirements...3 Potential Solutions...14 Crosscut
More informationIon beam etch and deposition systems
Ion beam etch and deposition systems The Business of Science Ion beam systems Ion beam technology offers unique abilities in etch and deposition Oxford Instruments offers a single tool, allowing the flexibility
More informationGLOBAL MARKETS, TECHNOLOGIES AND MATERIALS FOR THIN AND ULTRATHIN FILMS
GLOBAL MARKETS, TECHNOLOGIES AND MATERIALS FOR THIN AND ULTRATHIN FILMS SMC057C August Margareth Gagliardi Project Analyst ISBN: 1-62296-338-5 BCC Research 49 Walnut Park, Building 2 Wellesley, MA 02481
More information2010 IRI Annual Meeting R&D in Transition
2010 IRI Annual Meeting R&D in Transition U.S. Semiconductor R&D in Transition Dr. Peter J. Zdebel Senior VP and CTO ON Semiconductor May 4, 2010 Some Semiconductor Industry Facts Founded in the U.S. approximately
More informationNoel Technologies. Provider of Advanced Lithography and Semiconductor Thin Film Services
Noel Technologies Provider of Advanced Lithography and Semiconductor Thin Film Services Noel Technologies Keith Best Biography Over the last 27 years, Keith Best has held a variety of semiconductor processing
More informationLithography Roadmap. without immersion lithography. Node Half pitch. 248nm. 193nm. 157nm EUVL. 3-year cycle: 2-year cycle: imec 2005
Lithography Roadmap without immersion lithography Node Half pitch 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 250 nm 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 248nm 193nm 157nm EUVL 3-year cycle: 2-year cycle:
More informationDUV. Matthew McLaren Vice President Program Management, DUV. 24 November 2014
DUV Matthew McLaren Vice President Program Management, DUV 24 Forward looking statements This document contains statements relating to certain projections and business trends that are forward-looking,
More informationHigh-Risk Technology Development
High-Risk Technology Development Co-Funded by The Advanced Technology Program (ATP) 1 Purabi Mazumdar, Program Manager Advanced Technology Program purabi.mazumdar@nist.gov 301-975-4891 NIST s mission is
More informationCustom & OEM Filter Design
Custom & OEM Filter Design Custom & OEM Benefits Latest coating technologies Competitive pricing Fast, on-time deliveries All filters manufactured in Vermont View of Coating Hall Custom & OEM Filter Design
More informationInnovative Technologies for RF & Power Applications
Innovative Technologies for RF & Power Applications > Munich > Nov 14, 2017 1 Key Technologies Key Technologies Veeco Market Focus Advanced Packaging, MEMS & RF Lighting, Display & Power Electronics Lithography
More informationCritical Dimension and Image Placement Issues for Step and Flash Imprint Lithography Templates
Critical Dimension and Image Placement Issues for Step and Flash Imprint Lithography Templates Kevin J. Nordquist 1, David P. Mancini 1, William J. Dauksher 1, Eric S. Ainley 1, Kathy A. Gehoski 1, Douglas
More informationUsed Semiconductor Manufacturing Equipment: Looking for Sales in All the Right Places. Study Number MA108-09
Study Number MA108-09 August 2009 Copyright Semico Research, 2009. All rights reserved. Reproduction in whole or part is prohibited without permission of Semico. The contents of this report represent
More informationClean Room Technology Optical Lithography. Lithography I. takenfrombdhuey
Clean Room Technology Optical Lithography Lithography I If the automobile had followed the same development cycle as the computer, a Rolls Royce would today cost $100, get a million miles per gallon, and
More information450mm and Moore s Law Advanced Packaging Challenges and the Impact of 3D
450mm and Moore s Law Advanced Packaging Challenges and the Impact of 3D Doug Anberg VP, Technical Marketing Ultratech SOKUDO Lithography Breakfast Forum July 10, 2013 Agenda Next Generation Technology
More informationLithography in our Connected World
Lithography in our Connected World SEMI Austin Spring Forum TOP PAN P R INTING CO., LTD MATER IAL SOLUTIONS DIVISION Toppan Printing Co., LTD A Broad-Based Global Printing Company Foundation: January 17,
More informationCD-SEM for 65-nm Process Node
CD-SEM for 65-nm Process Node 140 CD-SEM for 65-nm Process Node Hiroki Kawada Hidetoshi Morokuma Sho Takami Mari Nozoe OVERVIEW: Inspection equipment for 90-nm and subsequent process nodes is required
More informationHOW TO CONTINUE COST SCALING. Hans Lebon
HOW TO CONTINUE COST SCALING Hans Lebon OUTLINE Scaling & Scaling Challenges Imec Technology Roadmap Wafer size scaling : 450 mm 2 COST SCALING IMPROVED PERFORMANCE 3 GLOBAL TRAFFIC FORECAST Cloud Traffic
More informationAcknowledgements. o Stephen Tobin. o Jason Malik. o Dr. Dragan Djurdjanovic. o Samsung Austin Semiconductor, Machine Learning
Semicon West 2016 Acknowledgements o Stephen Tobin o Samsung Austin Semiconductor, Machine Learning o Jason Malik o Samsung Austin Semiconductor, Metrology o Dr. Dragan Djurdjanovic o University of Texas,
More informationInstitute of Solid State Physics. Technische Universität Graz. Lithography. Peter Hadley
Technische Universität Graz Institute of Solid State Physics Lithography Peter Hadley http://www.cleanroom.byu.edu/virtual_cleanroom.parts/lithography.html http://www.cleanroom.byu.edu/su8.phtml Spin coater
More informationMICROSTRUCTURING OF METALLIC LAYERS FOR SENSOR APPLICATIONS
MICROSTRUCTURING OF METALLIC LAYERS FOR SENSOR APPLICATIONS Vladimír KOLAŘÍK, Stanislav KRÁTKÝ, Michal URBÁNEK, Milan MATĚJKA, Jana CHLUMSKÁ, Miroslav HORÁČEK, Institute of Scientific Instruments of the
More information