EDA for IC System Design, Verification, and Testing

Transcription

1 EDA for IC System Design, Verification, and Testing Edited by Louis Scheffer Cadence Design Systems San Jose, California, U.S.A. Luciano Lavagno Cadence Berkeley Laboratories Berkeley, California, U.S.A. Grant Martin Tensilica Inc. Santa Clara, California, Taylor &. Francis Taylor &. Francis Group Boca Raton London New York A CRC title, part of the Taylor & Francis imprint, a member of the Taylor & Francis Group, the academic division of T&F Informa plc.

2 Contents SECTIONI Introduction 1 Overview Luciano Lavagno, Grant Martin, and Louis Scheffer 1-1 Introduction to Electronic Design Automation for Integrated Circuits 1-2 System Level Design 1-6 Micro-Architecture Design 1-8 Logical Verification 1-8 Test 1-9 RTL to GDS-II, or Synthesis, Place, and Route 1-9 Analog and Mixed-Signal Design 1-11 Physical Verification 1-11 Technology Computer-Aided Design The Integrated Circuit Design Process and Electronic Design Automation Robert Damiano and Raul Camposano Introduction Verification Implementation Design for Manufacturing 2-11 SECTION II System Level Design 3 Tools and Methodologies for System-Level Design Shuvra Bhattacharyya and Wayne Wolf Introduction Characteristics of Video Applications Other Application Domains Platform Characteristics 3-3

3 3.5 Models of Computation and Tools for Model-Based Design Simulation Hardware/Software Cosynthesis Summary System-Level Specification and Modeling Languages Joseph T. Bück Introduction A Survey of Domain-Specific Languages and Methods Heterogeneous Platforms and Methodologies Conclusions SoC Block-Based Design and IP Assembly John Wilson 5_1 5.1 The Economics of Reusable IP and Block-Based Design Standard Bus Interfaces Use of Assertion-Based Verification Use of IP Configurators and Generators The Design Assembly and Verification Challenge The SPIRIT XML Databook Initiative Conclusions Performance Evaluation Methods for Multiprocessor System-on-Chip Design Ahmed Jerraya and Iuliana Bacivarov Introduction Overview of Performance Evaluation in the Context of System Design Flow MPSoC Performance Evaluation Conclusion System-Level Power Management Naehyuck Chang, Enrico Macii, Massimo Poncino, and Vivek Tiwari Introduction Dynamic Power Management Battery-Aware Dynamic Power Management Software-Level Dynamic Power Management Conclusions Processor Modeling and Design Tools Prabhat Mishra and Nikil Dutt Introduction Processor Modeling Using ADLs ADL-Driven Methodologies Conclusions Embedded Software Modeling and Design Marco Di Natale Introduction Synchronous vs. Asynchronous Models Synchronous Models Asynchronous Models 9-16

4 9.5 Research on Models for Embedded Software Conclusions Using Performance Metrics to Select Microprocessor Cores for IC Designs Steve Leibson Introduction The ISS as Benchmarking Platform Ideal Versus Practical Processor Benchmarks Standard Benchmark Types Prehistoric Performance Ratings: MIPS, MOPS, and MFLOPS Classic Processor Benchmarks (The Stone Age) Modern Processor Performance Benchmarks Configurable Processors and the Future of Processor-Core Benchmarks Conclusion Parallelizing High-Level Synthesis: A Code Transformational Approach to High-Level Synthesis Gaurav Singh, Sumit Gupta, Sandeep Shukla, and Rajesh Gupta Introduction Background and Survey of the State of the Art Parallelizing HLS The SPARKPHLS Framework Summary SECTION III Micro-Architecture Design 12 Cycle-Accurate System-Level Modeling and Performance Evaluation Marcello Coppola and Miltos D. Grammatikakis Introduction System Modeling and Design Methodology Back-Annotation of System-Level Modeling Objects Automatic Extraction of Statistical Features Open System-Level Modeling Issues Micro-Architectural Power Estimation and Optimization Enrico Macii, Renu Mehra, and Massimo Poncino Introduction Background Architectural Template Micro-Architectural Power Modeling and Estimation Micro-Architectural Power Optimization Conclusions Design Planning Ralph H.J.M. Otten Introduction Floorplans Wireplans A Formal System For Trade-Offs 14-17

5 SECTION IV Logical Verification 15 Design and Verification Languages Stephen A. Edwards Introduction History Design Languages Verification Languages Conclusions Digital Simulation John Sanguinetti Introduction Event- vs. Process-Oriented Simulation Logic Simulation Methods and Algorithms Impact of Languages on Logic Simulation Logic Simulation Techniques Impact of HVLs on Simulation Summary Using Transactional-Level Models in an SoC Design Flow Alain Clouard, Frank Ghenassia, Laurent Maillet-Contoz, and Jean-Philippe Strassen Introduction Related Work Overview of the System-to-RTL Design Flow TLM A Complementary View for the Design Flow TLM Modeling Application Programming Interface Example of a Multimedia Platform Design Flow Automation Conclusion Assertion-Based Verification Erich Marschner and Harry Foster Introduction History State of the Art Hardware Acceleration and Emulation Ray Turner and Mike Bershteyn Introduction Emulator Architecture Overview Design Modeling Debugging Use Models The Value of In-Circuit Emulation Considerations for Successful Emulation Summary 19-20

6 20 Formal Property Verification Limor Fix and Ken McMillan Introduction Formal Property Verification Methods and Technologies Software Formal Verification Summary SECTION V Test 21 Design-For-Test Bernd Koenemann Introduction The Objectives of Design-For-Test for Microelectronics Products Overview of Chip-Level Design-For-Test Techniques Conclusion Automatic Test Pattern Generation Kwang-Ting (Tim) Cheng and Li-C. Wang Introduction Combinational ATPG Sequential ATPG ATPG and SAT Applications of ATPG High-Level ATPG Analog and Mixed Signal Test Bozena Kaminska Introduction Analog Circuits and Analog Specifications Testability Analysis Fault Modeling and Test Specification Catastrophic Fault Modeling and Simulation Parametric Faults, Worst-Case Tolerance Analysis, and Test Generation Design for Test An Overview Analog Test Bus Standard Oscillation-Based DFT/BIST PLL, VCO, and Jitter Testing Review of Jitter Measurement Techniques Summary Index Index-1