PLATEFORME SYSTEMES EMBARQUES
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1 PLATEFORME SYSTEMES EMBARQUES &
2 & CEA. All rights reserved DACLE Division V1,0» employees» 10 research centers» 4 regional extensions» Budget of 4.3 billion» 650 patents/year» 4000 publications/year» 50 Joint Research Laboratory» 150 startup creations in 30 years Cliquez CEA: pour from modifier Research le style to Industry titre Defense Security Military Applications Division Direction Nuclear Energy Nuclear Energy Division Key Enabling Technologies Technology Paris Saclay Fontenay-aux-Roses Nantes DAM- IdF Le Ripault Valduc Grenoble Bordeaux Cesta Gramat Marcoule Cadarache Gardanne Fundamental research Materials Sciences Division Life Sciences Division Science Toulouse
3 CEA Tech: bringing competitiveness to our customers Cliquez pour modifier le style du titre Pump Priming 25% (5-10 ans) Technology Transfer 75% (1-3 ans) Knowloedge Market & CEA. All rights reserved DACLE Division V1,0
4 CEA Tech: unique technology platforms over Europe Cliquez pour modifier le style du titre & CEA. All rights reserved DACLE Division V1,0 4
5 CEA Tech: KETs for a broad range of industries Cliquez pour modifier le style du titre Example: nanoelectronics 5 & CEA. All rights reserved DACLE Division V1,0
6 Models Emulation IP From an application to an embedded system Cliquez pour modifier le style du titre Algo/Archi matching Architecture design Silicon integration C++ IC Embedded System Platform Design Platform Test Platform The Valley of Death Our approach Advanced technologies & HW/SW expertise Reusable building blocks Turned toward market s system needs Evaluate usage scenario at system level Offer an adapted technology Progress on Technology Readiness Level (TRL) & CEA. All rights reserved DACLE Division V1,0
7 & CEA. All rights reserved DACLE Division V1,0 Cliquez Integrated pour modifier Systems le style Platforms du titre NanoInnov Applications Embedded Systems Components & IC Design Emulation, Simulation Hard/Soft Integration System in Package Miniaturization Integrated Components Technologies & Tests Minatec
8 Cliquez pour Embedded modifier System le style Platform du titre Equipment & Human Resources Emulation Tools Eve-Synopsis Zebu : 5M ports capacity Mentor Veloce2 : 200M gates multicore emulator Simulation Tools (SESAM, ArchC) 40 permanent researchers Methodologies System exploration Architecture exploration and design Electronic System prototyping Embedded application exploration Hardware/Software coherence Middleware development Embedded System fault tolerance, reliability & security Veloce2 Emulator & CEA. All rights reserved DACLE Division V1,0
9 & CEA. All rights reserved DACLE Division V1,0 Cliquez pour modifier le style du titre COTS ANALYSIS
10 & CEA. All rights reserved DACLE Division V1,0 Programming single vs multi-core architectures Cliquez pour modifier le style du titre Single-core programming Democratic programming Fairly good abstraction Fairly good performance Multi-core programming Expert programming Dedicated language No performance portability (yet) C C++ fortran Java OpenCL CUDA OpenMP MPI HMPP compilation Compilations ARM Intel powerpc... AMD Nvidia Archi // #1 Archi // #2
11 Speedup & CEA. All rights reserved DACLE Division V1,0 Efficacité énergétique Temps d exécution 1 e 3 Cycles / frames Frames/Joule Higher is better Lower is better Apps Kernel/hotpoints Extraction Best choices: - Architectures - Parallelization methods Benchmarking of Cliquez pour modifier le Parallel style Architectures du titre Empirical Knowledge Database Semi-auto statistical methodology Working on COTS parallel architecture benchmarking To improve benchmarking objectivity To improve productivity when performing parallel ports on embedded systems On-going and future research ARM-based systems benchmarking and dimensioning methodology and rules Benchmarks suites for I/Os intensive applications 1,E+7 arm 1,E+6 i7 tilera P2012 1,E ,6 0,4 0,2 arm i7 tilera COTS platform Parallelisation degree Degré de parallélisation P2012 (estim.)
12 & CEA. All rights reserved DACLE Division V1,0 mj Cliquez pour modifier Example le conclusions style du titre Parallel programming and parallel architectures Push programming complexity way beyond sequential programming Re-introduces a lot of human intervention in design flows Harms the average-developer as much as the expert-one Energy spent for pedestrian detection arm i7 tilera P2012 New methodology introduced, combining empirical experimentations with analytic analysis to allow fast architecture benchmarking and parallelization model analysis Results demonstrate small deviation (<10%) between prediction and measures Impact of programming style (50% performance) Impact if code optimization (8 factor between naïve and optimized implementations)
13 & CEA. All rights reserved DACLE Division V1,0 Cliquez pour modifier le style du titre MODELING
14 & CEA. All rights reserved DACLE Division V1,0 Cliquez pour modifier le style du SESAM titre Processor modeling and integration Architecture & SW Exploration Functional or CA ISS ArchC 2.0, GenIssLib, OVP Mips32, STXP70, Sparcv8 NXP BSP CoolFlux MPSoC Modeling Parameter files +250 parameters +300 statistics Reliability, power MPSoC Simulation High-level modeling SystemC C/C++ AT TLM Cosimulation VHDL / Verilog Asymetric multiprocessors Up to 1-10 MIPS (8 PE) +90% of accuracy NFS server Automatic spreadsheet
15 Real execution time (hours) Tool acceleration Cliquez SW & pour HW modifier prototypes le style comparison du titre Maximum error deviation between SW & HW prototypes +/- 7% Acceleration of simulation speed x Functional RTL Post-synthesis RTL on EVE SESAM 0 & CEA. All rights reserved DACLE Division V1,0
16 & CEA. All rights reserved DACLE Division V1,0 Cliquez pour modifier le style du titre EXPLORATION VIRTUAL PROTOTYPING
17 & CEA. All rights reserved DACLE Division V1,0 Cliquez pour modifier le style Highlights du titre Architecture sizing, design and diffusion taking into account Performance, Thermal, Power and HW/SW configuration. An end-to-end HW/SW development Rapid Architecture sizing in SESAM Environment : Components on the Shelf (COTS) evaluation, based on performances, cost and applications High level system modeling & simulation Thermal/Power effects are analyzed with DOCEA and ATRENTA frameworks Hardware dependent Software is configured and customized for application with MAGILLEM Tools FPGA ARM DSP Example : a 3D-Vision driver assistance system
18 & CEA. All rights reserved DACLE Division V1,0 Cliquez pour modifier Optimization le style process du titre High performance and flexible computing board for applications of real time and actual embedded geolocalization applications Design of a Multi-CPU, Multi-FPGAs board <167ms Pure SW execution 48ms Match 5ms Pose 34/ 1512ms Local Bundle Adjustment or 3D recons. 55ms POI extractor 25ms Descriptor Parallel Board execution X86 Host CPU SW Embedded CPU HW accelerators 2ms 15 ms SIMD, MT and Multi-frame Parallelism RT-SW & HW Dedicated HW acceleration: >10 <15ms
19 Automobile Aéronautique Ferroviaire Cliquez pour modifier le APPLICATIONS style du titre Conception des systèmes embarqués et de circuits intégrés DiagnoBoard DiagnoChip GMR PsyC, OS PharOS Chaine de Compilation Localisation 8X plus précise et 30x plus rapide que la puce Livewire Applicati on Validation et Intégration des OS temps réel Modèles d architecture (ex Boléro, Leopard) Norme et Standards (DO168, AUTOSAR) Développement OS sur Architecture virtualisée Dimensionnement d architectures Simulation Environnement de prototypage virtuel Emulation Evaluation de performances Puissance de calcul X2 à même surface & CEA. All rights reserved DACLE Division V1,0
20 Cliquez pour modifier A Business le style Model du titre Bridging the gap to transfer IP & know-how Pilot line Mass production Fundamental research Applied Research 4P To the industry & CEA. All rights reserved DACLE Division V1,0
21 & CEA. All rights reserved DACLE Division V1,0 End-to-end Embedded System Design Partner Cliquez pour modifier le style du titre Emulation Full control Design flow Characterization & test Front-End Back-end Functional Validation Modeling HW/SW Co-design Architectures Logic Synthesis Functional modeling Electrical modeling Circuit Simulations Placement/routing Verification Post-Layout Bench labs Industrial test on pre-series Overcome skills partitioning, a condition for innovation A single partner along product maturation
22 CEA-Tech Offer for our customers competitiveness Cliquez pour modifier le style du titre A UNIQUE offer Platforms and extensive patent portfolio A COMPETITIVE and INNOVATIVE offer Key Enabling Technologies as innovation driver World-class knowledge and methods A PROTECTED offer Confidentiality and data protection A MULTI-INDUSTRY offer For all industries: from traditional to high-tech A CUSTOMIZED offer Personal service at every stage of your innovation project Customized collaboration (contract, industrial transfer, local support) 22 & CEA. All rights reserved DACLE Division V1,0
23 All inquiries Centre de Grenoble 17 rue des Martyrs Grenoble Cedex Centre de Saclay Nano-Innov PC Gif sur Yvette Cedex
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