EE382V: Embedded System Design and Modeling

Transcription

1 EE382V: Embedded System Design and - Introduction Andreas Gerstlauer Electrical and Computer Engineering University of Texas at Austin gerstl@ece.utexas.edu : Outline Introduction Embedded systems System-level design Course information Administration Topics Materials Policies Projects EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 2 (c) 2010 A. Gerstlauer 1

2 Embedded Systems Systems that are part of a larger system Application-specific Diverse application areas Tight constraints Real-time, performance, power, size Cost, time-to-market, reliability Ubiquitous Far bigger market than generalpurpose computing (PCs, servers) $46 billion in 04, >$90 billion by 2010, 14% annual growth 4 billion devices in 04 98% of processors sold [Turley02, embedded.com] EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 3 System Design is hard EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 4 (c) 2010 A. Gerstlauer 2

3 and getting harder Growing system complexities Increasing application demands Networked and distributed Cyber-physical integration Increasingly programmable & customizable Technological advances Multi-Processor System-On-Chip (MPSoC) 10, ,000 Logic transistors per chip (in millions) 1, IC capacity Productivity Gap 10, Productivity (K) Trans./Staff-Mo Source: SEMATECH; Courtesy of: T. Givargis, F. Vahid. Embedded System Design, Wiley EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 5 General-Purpose Computing Reaching physical limits of technology scaling Power/utilization/ walls and dark silicon Efficiency/optimality vs. flexibility/generality Opportunity and need for specialization Heterogeneous multi-core / Asynchronous CMP GP-GPUs EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 6 (c) 2010 A. Gerstlauer 3

4 Processor Implementation Options Source: T. Noll, RWTH Aachen, via R. Leupers, From ASIP to MPSoC, Computer Engineering Colloquium, TU Delft, 2006 EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 7 Multi-Processor System-on-Chip (MPSoC) System Memory Memory Controller CPU GPU Local RAM Frontside Bus DSP DSP RAM Hardware Accelerator Bridge DSP Bus Shared RAM Hardware Accelerator Video Front End Local Bus EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 8 (c) 2010 A. Gerstlauer 4

5 MPSoC Challenges Complexity High degree of parallelism at various levels High degree of design freedom Multiple optimization objectives design constraints Applications Programming Model? Heterogeneity Of components Processors, memories, busses Of design tasks Architecture, mapping, scheduling EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 9 Abstraction Levels Move to higher levels of abstraction [ITRS07, itrs.net] Electronic system-level (ESL) design Level Number of components System System level level 1E0 1E1 Algorithm RTL 1E2 1E3 1E4 Abstraction Accuracy Gate 1E5 1E6 Transistor 1E7 Source: R. Doemer, UC Irvine EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 10 (c) 2010 A. Gerstlauer 5

6 System-Level Design From specification Functionality, behavior Application algorithms Constraints To implementation Architecture Spatial and temporal order Components and connectivity Across hardware and software ARM MP3 Jpeg Requirements, constraints Proc Proc M1 stripe Proc Proc System Design DSP Enc Dec Proc HW Codebk MBUS Design automation at the system level and simulation Synthesis Verification Arbiter1 M1Ctrl BUS1 (AHB) IP Bridge DMA DCTBus DCT DCT TX BUS2 (DSP) I/O1 I/O2 I/O3 I/O4 SI BO BI SO Implementation (HW/SW synthesis) EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 11 A model: Abstraction of physical reality Mathematical formula, drawing/blueprint, data Core of any design process Specification Define (formally!) desired characteristics, golden reference Exploration Validate design choices Analysis and evaluation Static analysis Simulation/experiments Predict before the system is built Contract of what to build Detect problems early (and cheaply) Stimuli Model Simulator Results Correctness of model? Accuracy vs. simplicity EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 12 (c) 2010 A. Gerstlauer 6

7 System Specification Capture requirements (what) Functional Free of any implementation details (not how) Non-functional Quality metrics Performance constraints Natural language Ambiguous Incomplete Formal representation Models of computation Objects and compositions Concurrency and time Executable Analysis or simulation Application development Precise description of desired system behavior Complete and umabgious EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 13 System Architecture Processing elements (PEs) Processors General-purpose, programmable Digital signal processors (DSPs) Application-specific instruction set processor (ASIP) Custom hardware processors Intellectual property (IP) Memories Arbiter CPU P1 CPU Bus P2 HW P3 P4 C1, C2 Mem Bridge IP Bus C1, C2 P5 IP Communication elements (CEs) Transducers, bus bridges I/O peripherals Busses Communication media Parallel, master/slave protocols Serial and network media Application mapping Allocation Partitioning Scheduling EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 14 (c) 2010 A. Gerstlauer 7

8 System Implementation Hardware Microarchitecture Register-transfer level (RTL) CPU Software binaries Application object code Real-time operating system (RTOS) Hardware abstraction layer (HAL) Interfaces Pins and wires Arbiters, muxes, interrupt controllers (ICs), etc. Bus protocol state machines Specification for further manufacturing Logic synthesis Layout EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 15 System-Level Design Flow CPU Mem B1 B2 v1 Computation & Communication Arbiter Bridge C1 C2 HW Platform library IP System Synthesis Front-End B3 Application specification B4 System-Level Design Languages (SLDLs) Instruction-Set Simulator (ISS) Transaction-Level Models TLM n C/C++ code Software // Hardware Synthesis Back-End C-based RTL Software Object Code Hardware VHDL/Verilog EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 16 (c) 2010 A. Gerstlauer 8

9 System-On-Chip Environment (SCE) Specification Spec Design Decisions System Design (Specify-Explore-Refine) PE/CE/Bus Database Compile onto platform TLM n TLMn TLMi System models Arch n Archn TLMn RTL DB Hardware Synthesis Software Synthesis SW DB Synthesize target HW/SW HWn.v HWn.v HWn.v RTLn RTLn RTLn ISSn ISSn ISSn Implementation Model CPUn.bin CPUn.bin CPUn.bin Commercial derivative for for Japanese Aerospace Exploration Agency Impl Impl n Impln n EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 17 UT ECE Courses CPU Mem B1 B2 v1 Computation & Communication Arbiter Bridge HW IP Platform library EE382V: Embedded System Design & System Synthesis Front-End C1 B3 C2 Application specification B4 EE382N-4: Adv. Adv. System Architecture Instruction-Set Simulator (ISS) Software Object Code System-Level Design Languages (SLDLs) Transaction-Level Models TLM n C/C++ code Software // Hardware Synthesis Back-End EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 18 C-based RTL EE382V: System-on-Chip Design Design Hardware VHDL/Verilog (c) 2010 A. Gerstlauer 9

10 : Outline Introduction Embedded systems Abstraction levels, design flow System-level design Design tasks, challenges and tools Course information Administration Topics Materials Policies Projects EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 19 Class Administration Schedule Lectures: TTh 3:30-5pm, ENS109 Instructor Prof. Andreas Gerstlauer Office: ACE Office hours: W 2:00-4:00pm or after class Information Web page: Announcements, assignments, grades: Blackboard Questions, discussions: Blackboard EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 20 (c) 2010 A. Gerstlauer 10

11 Course Topics System-level design Methodologies, design flow, models System-level design languages (SLDL): SpecC, SystemC Functional modeling System specification and validation concepts Formal Models of Computation (MoC) Architecture modeling Computation and communication refinement Virtual platform prototyping, transaction-level modeling System synthesis Profiling, analysis and estimation tools Design space exploration algorithms Prerequisites Software: C/C++ (algorithms and data structures) Hardware: VHDL/Verilog (digital design) Embedded systems and embedded software EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 21 Textbooks (1) Main textbook D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner, Embedded System Design:, Synthesis, Verification, Springer, 2009 ( orange book ) Optional books A. Gerstlauer, R. Doemer, J. Peng, D. Gajski, System Design: A Practical Guide with SpecC, Kluwer, 2001 ( yellow book ) Practical, example-driven introduction using SpecC EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 22 (c) 2010 A. Gerstlauer 11

12 Textbooks (2) Optional books (cont d) T. Groetker, S. Liao, G. Martin, S. Swan, System Design with SystemC, Kluwer, 2002 ( black book") Reference for SystemC language and methodology F. Vahid, T. Givargis, Embedded System Design: A Unified Hardware/Software Introduction, Wiley, John & Sons, 2001 Background about embedded systems in general Additional reading material posted on class webpage EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 23 Policies Grading Homeworks: 15% Labs: 20% Midterm: 25% Project: 40% No late submissions! Academic dishonesty Homeworks Discuss questions and problems with others Turn in own, independent solution Labs and project Teams of up to 3 students One report and presentation EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 24 (c) 2010 A. Gerstlauer 12

13 Project Project goals Independent research or development project System design example/case study System design research problem Literature survey on system design research area Literature review, proposal, implementation Final report and presentation in publishable quality Project timeline Abstract: October 1 Proposal, literature survey: October 21 (tentative) Presentations: last week of classes (Nov. 30 & Dec 2) Report: finals week (Dec. 9) EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 25 Some Possible Projects Design projects (Embedded) system design example Specify, model, simulate, explore, synthesize using SCE Research projects Specification modeling Model-based design: LabView/Matlab/Powerpoint to chip» Translation of MoCs into SpecC/SystemC for synthesis Platform modeling Component modeling, e.g. bus TLM or ISS (QEMU) integration OS modeling (multi-core schedulers, OS-internal timing) Reliability modeling and simulation Assertion-based verification Synthesis (Statistical) power, performance, reliability estimation Machine learning for mapping (allocation, partitioning, scheduling) Hardware or software synthesis and optimization EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 26 (c) 2010 A. Gerstlauer 13

14 Successful Past Projects A. Pedram, C. Craven, T. Amimeur, Cache Effects at the Transaction Level, IESS 2009 (best paper runner-up) A. Banerjee, Transaction Level of Best Effort Channels for Networked Embedded Devices, IESS Exploration J. Lin, A. Srivatsa, Heterogeneous Multiprocessor Mapping for Real-Time Streaming Systems, EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 27 (c) 2010 A. Gerstlauer 14