Hybrid System Level Power Consumption Estimation for FPGA-Based MPSoC

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1 Hybrid System Level Power Consumption Estimation for FPGA-Based MPSoC Santhosh Kumar RETHINAGIRI, Rabie BEN ATITALLAH, Smail NIAR, Eric SENN, and Jean-Luc DEKEYSER INRIA Lille Nord Europe, Université de Lille1, Lille, France and LAMIH, Université de Valenciennes et du Hainaut Cambrésis, Valenciennes, France and LAB-STICC Université de Bretagne Sud, Lorient, France Abstract This paper proposes an efficient Hybrid System Level (HSL) power estimation methodology for FPGA-based MPSoC. Within this methodology, the Functional Level Power Analysis (FLPA) is extended to set up generic power models for the different parts of the system. Then, a simulation framework is developed at the transactional level to evaluate accurately the activities used in the related power models. The combination of the above two parts lead to a hybrid power estimation that gives a better trade-off between accuracy and speed. The proposed methodology has several benefits: it considers the power consumption of the embedded system in its entirety and leads to accurate estimates without a costly and complex material. The proposed methodology is also scalable for exploring complex embedded architectures. The usefulness and effectiveness of our HSL methodology is validated through a typical mono-processor and multiprocessor embedded system designed around the Xilinx Virtex II Pro FPGA board. Our experiments performed on an explicit embedded platform show that the obtained power estimation results are less than 1.2% of error when compared to the real board measurements and faster compared to other power estimation tools. I. INTRODUCTION Due to the ongoing nano-miniaturisation in chip production, estimation of power consumption is becoming a critical predesign metric in complex embedded systems such as Multi- Processor System-on-Chip (MPSoC) in FPGA s. In such architectures, processors come with high computation rates while the reconfigurable logic offers high performance per watt and adaptability to the application constraints. In current industrial and academic practices, power estimation using low level CAD tools is still widely adopted, which is clearly not suited to manage the complexity of modern embedded systems. Recently, the ITRS [8] and HiPEAC 1 roadmaps promote power defines performance and power is the wall. Facing this issue, designers should calculate the power consumption as early as possible in the design flow to reduce the time-tomarket and the development cost. Today, system level power estimation is considered a vital premise to cope with the critical design constraints. However, the development of tools for power estimation at the system level is in the face of extremely challenging requirements such as the efficient power 1 modeling methodology, the rapid system prototyping, and the accurate power estimates. At the system level, the power estimation process is centered around two correlated aspects: the power model granularity and the system abstraction level. The first aspect concerns the granularity of the relevant activities on which the power model relies. It covers a large spectrum that starts from the fine-grain level such as the logic gate switching and stretches out to the coarse-grain level like the hardware component events. In general, fine-grain power estimation yields to a more correlated model with data and to handle technological parameters, which is tedious for system level designers. On the other hand, coarse-grain power models depend on microarchitectural activities that cannot be determined easily. The second aspect involves the abstraction level on which the system is described. It starts from the usual Register Transfer Level (RTL) and extends up to the algorithmic level. In general, going from low to high design level corresponds to more abstract description and then coarser activity granularity. The power evaluation time increases as we go down through the design flow and the accuracy depends on the extraction of each relevant activity and the characterization methodology to evaluate the related power cost. In order to have an efficient power estimation methodology, we should find a better tradeoff between these two aspects. To answer the above challenges, we propose a new Hybrid System Level (HSL) power consumption estimation methodology for complex embedded systems. A key word in our contribution is hybridization between abstraction levels. Almost all the previous studies focus on power estimation for a given abstraction level without overcoming the wall of speed/accuracy trade-off. The idea here is to build up a hybrid power estimation tool that combines Functional Level Power Analysis (FLPA) for hardware power modeling and Transactional Level Modeling (TLM) simulation technique for rapid system prototyping and fast power estimation. Basically, the FLPA is used for processor power modeling. In the frame of this work, it will be extended to cover the other hardware components used in the MPSoC such as the memory and the reconfigurable logic. After that, we go further in terms of scalability to target heterogeneous multiprocessor /11/$ IEEE 239

2 architectures. The functional power estimation part is coupled with a fast SystemC [13] simulator in order to obtain the needed micro-architectural activities for power models, which allows us to reach a superior bargain between accuracy and speed. This paper is organized as follows. Section II presents the related works, section III exposes the proposed HSL power estimation methodology. In Section IV, the power modeling methodology is applied to a typical MPSoC designed around Virtex II Pro FPGA board. To evaluate our approach in terms of accuracy, speed and scalability, experimental results are presented in Section V. Fig. 1. Hybrid System Level (HSL) power estimation methodology II. RELATED WORKS Among the developed tools for power consumption estimation at the system level, we quote tools based on microarchitectural cycle-level simulation such as Wattch [5] and Simplepower [16]. They define fine-grain power models by characterizing component features such as a set of instructions or functional blocks using analytic power laws. The contributions of the internal unit activities are calculated and added together during the execution of the program on the micro-architectural simulator. This approach needs low-level description of the architecture that are often difficult to obtain and with a least significant amount of simulation time. In an attempt to reduce simulation time, recent efforts have been done to build up fast simulators using Transaction Level Modeling (TLM) [4]. SystemC [13] and its TLM 2.0 kit have become a de facto standard for the system-level description of Systems-on-Chip (SoC) by the means of offering different coding styles. Nevertheless, power estimation at the TLM level is still under research and is not well established. In [11] and [12], a methodology is presented to generate consumption models for peripheral devices at the TLM level. Relevant activities are identified at different levels and granularities. The characterization phase is however done at the gate level: from where they deduce the activity and power consumption for the higher level. Using this approach for recent processors and systems is not realistic. Dhawada et al. [6] proposed a power estimation methodology for a monoprocessor PowerPC and CoreConnect-based system at the TLM level. Their power modeling methodology is based on a fine-gsrain activity characterization at the gate level, which needs a huge amount of development time. Due to a high correlation with data, a power estimation inaccuracy of 11% is achieved. Compared to the previous works, our proposed methodology for power estimation also partially uses SystemC/TLM simulation with coarse grain power models. In addition, our methodology is applied for heterogeneous multiprocessor architectures. For the functional level, Tiwari et al. [15] have introduced the concept of Instruction Level Power Analysis (ILPA). They associate a power consumption model with instructions or instruction pairs. The power consumed by a program running on the processor can be estimated using an Instruction Set Simulator (ISS) to extract instruction traces, and then adding up the total cost of the instructions. This approach suffers from the high number of experiments required to obtain the model. In addition, it can be applicable only for processors. To overcome this drawback the Functional Level Power Analysis (FLPA) was proposed [10] [9], which relies on the identification of a set of functional blocks that influence the power consumption of the target component. The model is represented by a set of analytical functions or a table of consumption values which depend on functional and architectural parameters. Once the model is build, the estimation process consists of extracting the appropriate parameter values from the design, which will be injected into the model to compute the power consumption. Based on this methodology, the tool SoftExplorer [7] has been developed and included in the recent toolbox CAT [14]. It includes a library of power models for simple to complex processors. Only a static analysis of the code, or a rapid profiling is necessary to determine the input parameters for the power models. However, when complex hardware or software is involved, some parameters may be difficult to determine with precision. This lack of precision may have a non-negligible impact on the final estimation accuracy. In order to refine the value of sensible parameters with a reasonable delay, we propose to couple SystemC/TLM simulation with functional power modeling technique. Thus, by this way a reasonable trade-off between estimation speed and accuracy will be reached. III. HYBRID SYSTEM LEVEL POWER ESTIMATION METHODOLOGY This section exposes our proposed HSL power estimation methodology that is divided into two parts as shown in Fig. 1. The first part concerns the power model elaboration for the system hardware components. In our framework, the FLPA methodology is used to develop generic power models for different target platforms. The main advantage of this methodology is to obtain power models, which rely on the functional parameters of the system with a reduced number 240

3 Fig. 2. HSL power estimator tool functioning of experiments. As explained in the previous section, FLPA comes with few consumption laws, which are associated to the consumption activity values of the main functional blocks of the system. The generated power models have been adapted to system level design, as the required activities can be obtained from a system level environment. For a given platform, the generation of power model is done at once. To estimate the power consumption of an MPSoC system, the first step is to divide the architecture into different functional blocks and then to cluster the components that are concurrently activated when the code is running. There are two types of parameters: algorithmic parameters that depend on the executed algorithm (typically the cache miss or instruction per cycle rates for a processor and area utilization for a hardware accelerator) and architectural parameters that depend on the component configuration set by the designer (typically the clock frequency). For instance, Table I presents the common set of parameters of our generic power model. These sets of parameters are defined for a general class of MPSoC. Additional parameters can be identified for complex processors based-architecture such as Superscaler or VLIW (Very Long Instruction Word). The second step is the characterization of the embedded system power consumption when the parameters vary. These variations are obtained by using some elementary assembly programs (called scenario) or built in test vectors elaborated to stimulate each block separately. Characterization can be performed by measurements on real boards. Finally, a curve fitting of the graphical representation will allow us to determine the power consumption models by regression. The analytical form or a table of values expresses the obtained power models. This power modeling approach was proven to be fast and precise. In our work, this approach has been applied to model power TABLE I GENERIC POWER MODEL PARAMETERS Algorithmic Name Description τ External memory access rate γ Cache miss rate for a processor β Instruction per cycle rate α area utilization for a HW accelerator Architectural F processor Frequency of the processor F bus Frequency of the bus N Number of processors consumption for processor, memory, reconfigurable hardware, and I/O peripherals. The second part of the methodology defines the architecture of our HSL power estimator that includes the functional power estimator and fast SystemC simulator as shown in Fig.1. The functional power estimator evaluates the consumption of the target system with the help of the elaborated power models from the first part. It takes into account the architectural parameters (e.g. the frequency, the number of processors, the processor cache configuration, etc.) and the application mapping. It also requires the different activity values on which the power models rely. In order to collect accurately the needed activity values, the functional power estimator communicates with a fast SystemC simulator at a TLM level. The combination of the above two components described at different abstraction levels (functional and TLM) leads to a hybrid power estimation that gives a better trade-off between accuracy and speed. The vital function of system level power estimation is to offer a detailed power analysis by the means of a complete simulation of the application. This process is initiated by the functional power estimator through the data and task interface (Fig. 2). In this way, the mapping information is transmitted to the fast TLM SystemC simulator. Our simulator consists 241

4 of several hardware components which are instantiated from the SoCLib [2] library in order to build a virtual prototype of the target system. We highlight that processors are described using Instruction Set Simulator (ISS) that sequentially executes the instructions and has no notion of concurrency of microarchitecture. In our previous framework [3], we presented an accurate TLM simulation technique that allows to evaluate the heterogeneous MPSoC performances. In the power estimation step, the simulator collects the activities that are influenced by the application and the input data. At the end of the simulation, the values of the activities are transmitted to the power consumption models or power estimator kernal using the activity counter interface in order to calculate the global power consumption as illustrated in Fig. 2. As we have stated before, the following section will discuss the first part i.e., the elaboration of the power model for the Xilinx Virtex II Pro FPGA platform by using FLPA methodology. IV. POWER MODEL ELABORATION In order to prove the usefulness and the effectiveness of the proposed power estimation methodology, we used a PowerPC 405-based architectures implemented into the Xilinx Virtex II Pro FPGA (XupV2Pro) platform. The Virtex II Pro FPGA contains two PowerPC 405 processors that have a 16KB, 2-way set associative instruction and data caches. In addition, this FPGA has a large number of configurable logic blocks (CLB) for implementing hardware accelerators. Each processor has access to the on-chip memory (BRAM) and the off-chip memory (SDRAM) via the Processor Local Bus (PLB). We used the JPEG (Joint Photographic Experts Group) application as a benchmark. The JPEG application consists of 4 main tasks: conversion RGB (Red, Green and Blue) to YUV (luminance, blue chrominance, and red chrominance components), Discrete Cosine Transform (DCT), Quantization, and Huffman coding. We also used the H.264/AVC baseline profile decoder that supports intra and inter-coding, and entropy coding with Context-Adaptive Variable-Length Coding (CAVLC). This section presents the power model elaboration which is the first part of our methodology. As explained above, we used the FLPA methodology to generate generic power models for the target system. As a first step, we divided the architecture into different functional blocks such as the processor, the memory system, the reconfigurable logic, etc. Then, we started the characterization of each component in order to extract the related power consumption models. Processor power model: Table II shows the power consumption models for the PowerPC405 processor and its memory system. These models predict consumption of the processor kernel and the I/Os parts separately, since distinct supplier devices power them with constant voltage: 1.5V for the processor and 2.5V for the SDRAM and I/Os respectively. The obtained power models shown in the Table II depend also on the memory mapping. For this reason, there are different power models for on-chip memory (BRAM) and for external memory (SDRAM). The input parameters on which the power models rely are the frequency of the processor (F processor (MHz)), bus frequency (F bus (MHz)), and the cache miss rate (0 < γ < 100 (%)). The system designer chooses the frequency of the processor and bus while cache miss rate is considered as an activity of the processor, which could be extracted from the simulation environment. According to these power models, the static consumption is dominant which is a drawback of the FPGA technology. For this reason, the latest FPGA circuits come with an optimized static power factory setting. TABLE II CONSUMPTION MODELS FOR THE POWERPC 405 PLATFORM Mapping Voltage Power laws BRAM 1.5V P(mW) = 0.40 F processor F bus V P(mW) = 5.37 F bus SDRAM 1.5V P(mW) = 0.38 F processor F bus V P(mW) = 4.1γ + 6.3F bus The elaborated power model for the PowerPC405 is simple due to the corresponding scaler architecture. However, new generation FPGAs such as Xilinx Virtex 7 come with more performance integrated processors such as the ARM 2 processor family. To demonstrate the usefulness of our power modeling approach in the context of complex processor, we elaborate the power model for the ARM Cortex A8 (P A8 ) which has a Superscaler architecture. The obtained power model (equation 1) includes the IPC (Instruction Per Cycle) parameter and separates the cache miss rates of the Level-1 (γ1) and Level-2 (γ2) caches. P A8 = 0.79 f IPC (γ1 + γ2) (1) FPGA power model: A power model has been built for the reconfigurable part of the FPGA component on the XupV2Pro board. For a given FPGA the parameters that can be extracted from the high-level specification are the frequency F, the switching rate β, and the utilized area α of the targeted FPGA. Using a high-level architecture synthesis tool such as GAUT [1], these parameters can be predicted with a good estimates. According to the experimental results, the model does not come as a multi-linear equation of the above-mentioned parameters. For this reason, a 3 entries table of consumption values is used. The power is estimated by interpolation of these 3 input parameters. For instance, Fig 3 illustrates the variation of the FPGA power consumption according to area utilization and the switching activity with an operating frequency set to 100 MHz. Extrapolation for heterogeneous multiprocessor architectures: The above developed power models will be used in the framework of system level estimation of heterogeneous multiprocessor architectures that may contain several processors and hardware accelerators. This approach is mandatory in the design flow for two reasons. First, system level estimation can be achieved with acceptable accuracy of x faster than the physical level. Second, it allows exploring architectures that cannot be implemented due to the hardware resource

5 Fig. 3. FPGA power consumption with 100 MHz frequency limitation or the unavailability of the target component. For instance, we cannot exceed two PowerPC based architecture using our XupV2Pro platform. Thus, it is important to have a scalable approach to address the complex system power/energy estimation issue. The equation 2 will be considered for the total system power (P total ) estimation. In addition to the processor (P pi ) and the hardware accelerators (P HwAcc ), the equation involves the power consumption of the synchronization part (P sync ) required to access the shared memory (P mem ) and the shared I/O resources (P I/O ). We mention here that it is necessary to compute the total energy (E total ) of the system before the deduction of the total power consumption in order to compare the proposed HSL methodology energy with the real board performance. P total = i E total = i P pi + P mem + P sync + P I/O + P HwAcc (2) j E pi + E mem + E sync + E I/O + E HwAcc (3) j In our XupV2Pro platform, synchronization between parallel tasks running on different processors or hardware accelerators is performed by a call to a hardware mutex. Several experiments have been conducted to evaluate the additional power cost of this hardware component. This study includes three parameters which are the number of masters, and the processor & bus frequencies. Experimental results show that the mutex power consumption depends mainly on the PLB frequency. V. SYSTEM LEVEL POWER ESTIMATION RESULTS A. Monoprocessor architecture For the second part of our HSL power estimation methodology, a system level prototype of a PowerPC based architecture has been developed. This prototype uses different SystemC models especially the ISS for the target processor. Furthermore, the cache parameters and the bus latencies are set to emulate the real platform behaviour. A set of counters are injected into the simulator to determine the occurrences of the main activities. For the PowerPC processor, the following counters are used for different cache miss rates: read data miss, write data miss and read instruction miss. For the example of ARM cortex A8 processor, additional counters should be defined for IPC and Level-2 cache miss rates computing. Fig. 4 shows the detailed results of the activities fetched by the fast SystemC simulator for each task of the JPEG application. From these results several remarks can be drawn. First, we can notice that instruction cache miss rates and read data miss rates are very low when compared with write data miss rates. This is due to the reduced task kernel and data pattern sizes that are very low compared to the cache size (16 KB), which decreases the access to the external memory and thus having a minimal effect on the dynamic power consumption. However, with the new submicron technologies the effect of the static power consumption cannot be neglected. For this reason, a softcore processor such as the Microblaze comes with reconfigurable cache size to fit with the application requirements. Second, the data write miss rates have a high impact on the total power consumption of the system. This is because of the algorithm structure, which does not favour the reuse of data output arrays and the usage of write-through cache policy. Therefore, the statistics collected in Fig. 4 could help in tuning the application structure for a better optimization of the system power consumption. In the next step, we estimated the total power consumption of each task using the power models shown in Table II (SDRAM mapping). Fig. 5 illustrates the results and shows the comparison between the proposed HSL methodology, SoftExplorer tool introduced in Section II, and the real board measurements. First, our power estimator has a negligible average error equals to 1.59%, which offers better accuracy than SoftExplorer which presents an average error of 4.32%. The average error obtained here is negligible due to the dominance of static power. For this reason, we calculate again the average error without taking into account the static power. Our methodology produces an average error of 4.3% and the SoftExplorer gives around 9.4% in comparison with real board measurement. This study offers a detailed power analysis for each task in order to help designers to detect peaks of consumption and thus to propose efficient mapping or optimization techniques. In order to evaluate the accuracy of our tool, we carried out power estimation on several image & signal processing benchmarks. Fig. 6 illustrates the power estimation results by showing the comparison between the proposed HSL power estimation methodology, SoftExplorer and the real board measurements. Our proposed methodology has a negligible average error of 1.24%, which offers better accuracy than SoftExplorer with an average error of 6.34% when compared to the real board measurements. This is due to better accuracy of the captured activities in the simulator rather than the static analysis or rapid profiling of the C or 243

6 Fig. 4. JPEG application cache miss rates Fig. 5. Power estimation accuracy for the JPEG application assembly code in SoftExplorer. B. Homogeneous multiprocessor architecture The second study involves an homogeneous architecture with identical processors to run the JPEG application. To evaluate the impact of the number of processors on the execution time and total energy/power consumption, we executed the JPEG on systems with 1 to 8 processors. The PowerPC frequency was set to 300MHz and the PLB frequency to 100MHz. All the processors execute the same workload but on different image macroblocs. Fig. 7 reports the execution time in ms and the total energy consumption in mj and Fig. 8 shows the power estimation of multimedia benchmarks for homogeneous multiprocessor (two PowerPC) architecture. Compared to real board energy measurements, our HSL estimator achieved an error of 0.79% and 3.49% for one and two processors respectively. This accuracy is obtained because of three main reasons. First, power models are extracted from real board measurements. Second, our methodology considers the synchronization part while using multiprocessor system. Finally, additional activities that are intrinsic in parallel processing such as shared data communication overheads are accurately evaluated by using our SystemC simulator. The 244

7 Fig. 6. Comparison of power estimation accuracy of HSL tool vs SoftExplorer (monoprocessor architecture) Fig. 7. Execution time and energy variation according to the number of processors Fig. 8. Power estimation of homogeneous multiprocessor (two PowerPC) architecture above mentioned reasons encourage us to consider architectures with a higher number of processors in the context of exploring new complex MPSoC. Fig. 7 shows that, for the implemented JPEG parallel application, adding processors to the system decreases the execution time, which improves the system performance. This variation is not linear because the processors share resources, which generates conflicts at some times, and reduces the speed-up as waiting cycles are added to the processors execution. In terms of energy consumption, we observe that until a certain number of processors, the total system energy consumption decreases as the number of execution cycles is reduced, and then it tends to stabilize as the system performance improves. But increasing the number of processors over a certain limit tends to be ineffective, as it just adds new conflicts at the bus level, leading to more waiting cycles. From Fig. 8, we are able to conclude that proposed HSL methodology is accurate and efficient in terms of scalability of application and processor with its negligible average error of 0.89% when compared to the real board measurements. C. Heterogeneous multiprocessor architecture In this part, we emphasize the benefit of our estimation methodology in the context of heterogeneous architecture. In general, the choice of a hardware accelerator is driven principally by the performance requirements of the application and the processor usage of each task. For the JPEG application, the DCT is the most time consuming task. Thus, it is selected to be implemented as a hardware accelerator. Various tradeoffs can be done between the amount of consumed hardware resources, the execution time, and the power consumption. The DCT task is highly regular and has large repetition spaces in its multiple hierarchical levels. Such large repetition spaces allow us to fully exploit the existing partitioning in VHDL. We selected a configuration, which is about 200 times faster than a software execution with a PowerPC processor running at 100 MHz. The synthesized hardware occupies 18% of the XupV2Pro. According to the FPGA power model, the power consumption of the chosen hardware DCT is around 300mW offering 40% of power saving compared to the software execution and 25% of reduction in execution time. 245

8 D. Estimation speed comparison In this section, we will compare the efficiency of the proposed methodology in term of estimation speed with the SoftExplorer and SimplePower tools introduced in Section II. This comparison is for the quantification of our proposed methodology to the state of art power estimation tools used in current industrial and academic practices. SoftExplorer and our proposed methodology are executed on a PC (Intel, 1.8 GHz, 2 Go of RAM), whereas SimplePower on a Workstation (Ultra Sparc T2+, 1.6 GHz, 2 Go of RAM). In order to compare the result, computer benchmarking has been done to confirm that the workstation is always faster compared to the PC for all kind of applications. Power estimation has been carried out with a set of image & signal processing applications and also with SPEC benchmarks. Fig. 9. Comparison of estimation time for HSL, SoftExplorer, and Simple- Power tools From Fig. 9, we can notice that SoftExplorer has an average estimation time of 5 seconds, which is faster when compared to the SimplePower s average estimation time of 20 seconds. Our proposed HSL methodology has a average estimation time of 4 seconds, which is faster compared to the other tools. Our HSL methodology works by running the application on the fast SystemC TLM simulator thereby collecting the dynamic activities. SimplePower uses cycle accurate specifications to collect the necessary power data, whereas SoftExplorer realizes a static profiling of the code, which results in reduced execution time by this way power consumption estimation time is low. Static profiling of the C code is not sufficient to determine the average execution time and the global energy consumption, for this reason we need to run the application on the Fast SystemC simulator in order to collect the activities accurately and efficiently. Experimental results prove that our proposed methodology is efficient and accurate. VI. CONCLUSION This paper presents a hybrid system level estimation methodology for MPSoC power-aware design. Indeed, 3 power/energy constraints are considered as a major challenge when the system runs on batteries. Thus, designers must take these constraints into account as early as possible in the design flow. First, a power modeling methodology has been defined to address the global system consumption that includes processors, memory, reconfigurable hardware, and etc. Secondly, the functional power modeling part is coupled with a fast SystemC simulation technique to obtain the needed micro-architectural activities for the power models, which allows us to reach accurate estimates. With such proposed methodology, the designer can explore several implementation choices: monoprocessor, homogeneous and heterogeneous multiprocessor. The future works of this project will focus on more complex heterogeneous platforms. Furthermore, in order to obtain more accurate power estimations, some power model refinements must be realized. This is the case for the data exchanges between hardware and software tasks respectively executed on hardware resource and on processor which are currently estimated at high level of abstraction. REFERENCES [1] The Gaut Website. [2] The Soclib Website. [3] R. B. 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