Bus-Switch Encoding for Power Optimization of Address Bus

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1 May 2006, Volume 3, No.5 (Serial No.18) Journal of Communication and Computer, ISSN , USA Haijun Sun 1, Zhibiao Shao 2 (1,2 School of Electronics and Information Engineering, Xi an Jiaotong University, Xi an , China ) Abstract: This paper presents a novel encoding technique to minimize the switch activities on the highly capacitive memory address bus so as to reduce power dissipation of bus. This technique is based on the temporal locality and spatial locality of instruction address. The experimental results based on an instruction set simulator and SPEC2000 benchmarks show that the presented encoding technique can reduce signal transitions on the address bus by 83.8%, and the actual overhead of the encoder circuit is estimated after encoder has been designed and synthesized with 0.18-µm CMOS technology. The results show that our technique well outperforms specialized low-power encoding schemes presented in the past. Key words: Bus; Encoding; Switching Activity; Low Power 1. Introduction Power dissipation is increasing continually and has become an important challenge in deep submicron chip design. With the increasing number of transistors on a chip and the rising operation frequency, power dissipation is increasing rapidly, causing cooling, packaging and reliability problems [1]. Meanwhile, many systems are becoming portable and wireless, the functioning of the power provided by a battery pack with a limited energy supply. In these situations, to achieve low power dissipation has become an important objective in the chip design. Nowadays, a large fraction of the total power dissipation on a chip is typically due to clock, memory, and datapath [2,3]. Heavily loaded wires in these design areas need special attention since the dynamic switch power because high capacitive loading on the wires can dominate the total power dissipation of chip. 1 Haijun Sun (1973- ), male, PhD candidate; main research fields: VLSI design. 2 Zhibiao Shao (1941- ), male, professor; main research fields: VLSI design. Low-swing buses are extensively used to reduce power dissipation. As memory address bus has high capacitance, power dissipation per address bus access is quite high, which limits the power efficiency of the overall system. Many low power techniques have been proposed to reduce the power of the address bus [4-8]. In this paper, a new address bus encoding method is presented to reduce bus power dissipation. Since the addresses are sequential except when control flow instructions are encountered or exceptions occur, signal transitions can be easily reduced by bus encoding method. We present a novel encoding technique in this paper, which is called Offset-Reorder-SM (ORS). And it is based on the adaptive reordering of the modified offset address bus lines with high toggling probability. The sorting index book is used to transmit the optimal sorting. ORS encoding gives more power reduction compared with other previous bus encoding methods. In section 2, we outline some related researches in this field. In section 3, ORS encoding method is presented. Bus is frozen when addresses are sequential. Otherwise, the modified offset address is transmitted after adaptive reordering of bus lines. The optimal sorting that minimizes the switching activity on the address bus lines is transmitted with the sorting index book. The experimental results based on an instruction set simulator and SPEC2000 benchmarks are given. ORS encoding is superior to the previous encoding methods in terms of signal transition reduction on the address bus, and the signal transition is reduced to 16.2%. The actual overhead of the encoder circuit is estimated after encoder is 86

2 designed and synthesized with 0.18-µm CMOS technology. Section 4 draws conclusions. 2. Previous Works In this section we review previous related works. There are a lot of techniques for low power bus and some of them are reviewed below. code [4] was proposed by L. Benini, et al. This encoding method achieves transition activity reduction in sequential addresses by using an extra bit line along with the address bus. The extra bit line is set when the addresses on the bus are sequential. In that case the data on the address bus is not altered. If the addresses are not sequential, the actual address will be put on the address bus. An average 60% of reduction in address bus switching activity is achieved by code. In addition, another encoding method based on the combination of bus invert encoding and encoding was proposed as -BI encoding [5]. In reference [6], Su, Tsui and Despain proposed using Gray code to implement the program counter of a microprocessor so as to minimize the switching activit ies of sequential memory accesses. Gray code is asymptotically optimal among all irredundant codes. Other codes include Pyramid code [7] and data ordering-based code [8,9]. In reference [10], -XOR code was proposed. The encoder works as follows: B (t) =b (t) (b (t-1) +S) B (t-1) where B (t) is the encoded value on the bus at time t, b (t) is the address value at time t, S is the stride between two successive addresses. It works the same as encoding when address increases uniformly. In other cases, the signal transitions are reduced compared to encoding because the offset address between before and after JUMP operation is usually small. In the same work, the authors proposed another encoding technique, which is called Offset-XOR code. It works as follows: B (t) =(b (t) -b (t-1) ) B (t-1) Usually the number of offsets is small and the XOR of previous bus value and offset has a small number of transitions. In reference [11] a new coding technique called the Beach Solution was proposed. In this method, the address trace of software is profiled, and possible correlation between different signals of the profiled trace is extracted. This information is subsequently used to define encoding functions that reduce the total switching activities. However, this method is only applicable to systems where the application programs are fixed and known prior since the encoding technique needs the exact knowledge of the address bus trace. The power saving is reported as 42%. 3. Offset-Reorder-SM Encoding 3.1 Offset-Reorder-SM Encoding Mechanism A novel address bus encoding method called Offset-Reorder-SM (ORS) encoding is proposed, which is based on the dynamically reorder of the modified offset address bus lines with high toggling probability. It results in high power saving on the address bus. Similar to code, the basic saving happens as a result of freezing the bus when addresses are sequential. Based on the statistics reported in reference [12], more than 95% of the branches in any program have offsets that need less than 10 bits to be binary coded. Therefore, when the offset address is transmitted on bus, since the high bits of offset address always remain zero, the offset code has a small number of transitions on the bus lines. However, if a backward jump occurs in an instruction trace, the resulting offset will be negative. This negative number tends to have a small magnitude. Therefore, when it is encoded in two s complement form, it will contain many 1 in high bits compared with positive offset, which can result in a large number of transitions on the bus lines. In a typical application program, many small backward jumps exist. In ORS encoding, LSBInv(x) 87

3 function is applied to the offset address, which is as follows: M (t) =LSBInv(b (t) -b (t-1) ) where M (t) is the value of the modified offset address, b (t) is the address value at time t. LSBInv(x) function inverts all bits of offset except the most significant bits when the offset is negative. Otherwise, offset remains unchanged, as shown in table 1. Table 1 Example of LSBInv Function Original Offset FFFFFFFFh,(-1) FFFFFFFEh,(-2) FFFFFFF6h,(-10) h Modified Offset h h h FFFFFFFFh To decrease bus switching activit ies further, the modified offset address bus lines are dynamically reordered. Because most of the branch displacements of a typical program need maximum of 10 bits to be represented based on reference [12], the ten least significant bits of modified offset address are dynamically reordered, which are organized in clusters of N lines each. Each N-line cluster is tentatively reordered by swapping the input lines using a particular sorting. The process is repeated N! times until the optimal sorting is found, which minimizes the switching activit ies on address bus. An N-bit data word x(t) will be indicated as {x(t)(n-1), x(t)(n-2),, x(t)(0)}. A sorting s(t) is an ordered set of N indices {z N-1,,z 0 }. F is a combinational logic function to produce a swapped data word y(t) as follows: yt () = {()( yt N 1), yt ()( N 2),, yt ()(0)} = F( x( t),s( t)) = {x(t)(z N-1 ), x(t)(z N-2 ),, x(t)(z 0 )} For example, if s(t)={3,1,2,0} and x(t)={0,1,0,1}, then y(t)={0,0,1,1}. Each sorting s(t) has a unique inverse s -1 (t), so x( t) = F( y( t), s -1 ( t)) = F( F ( x( t), s( t)), s -1 ( t)) For instance, if s(t)={0,2,3,1}, then s -1 (t)= {1,2,0,3}. The ORS encoding method can be expressed by the following equation: () t () t ( B, SEL ) = + = () t ( y,0) otherwise ( t 1) () t ( t 1) ( B,1) if( b b SR) where B (t) is the encoded value on the bus at time t, b (t) is the address value at time t, SEL (t) is the additional bus line to transfer the information on the sequentiality of the addresses to the receiver side, SR is the stride between two successive addresses, y (t) is obtained by the original offset address which is modified with LSBInv (x) function, and the ten least significant bits are dynamically reordered with the optimal sorting. The architecture of this encoder is shown in Fig. 1. pcloc k COUNTER B b (t) (t- - b 1) (t- 1) RESE T LSBInv(x) H 0. 1 N!-1 Index book pcloc k sorting Reorde r of bus CMP REG distanc Hamming e enabl e CLK Fig. 1 The Architecture of Encoder REG? tp (ts - 1) y (t) tp (ts) From the definition of encoding function and inverse swapping, we derive the following decoding equation to obtain the original b (t) : b () t ( t 1) b + SR if SEL = ( 1) = ( t 1) 1 1 b + LSBInv ( FBt ( (), s ())) t if ( SEL = 0) opt where s opt is the optimal sorting, LSBInv -1 (x) function inverts all bits of x except the most significant bit when the MSB bit is 1 ; otherwise, x remains unchanged. 3.2 Optimal Sorting Pattern In ORS code, the optimal sorting s opt could 88

4 minimize the switching activity H[y(t) B (t-1) ], where H is the Hamming distance between y(t) and B (t-1). The sorting s can be generated according to the fixed sequence by a finite state machine. A counter takes count of the clock cycle, and each number should index a sorting to the index book. Because the allowed individual s are at most N!, the range of the counter is from 0 to N!-1. The optimal sorting will be found after N! attempts. One extra line tp is added to transmit the optimal sorting, tp can be expressed as follows: ( ts) ( ts 1) (ts) tp = tp, if ( H < Hmin ); ( ts) ( ts 1) tp = tp, otherwise. When H of current is no less than the previous minimum, tp remains unchanged; otherwise, the transition occurs on tp line, as shown in Fig. 1. H produces the Hamming distance between two words. CMP unit compares the actual Hamming distance with the temporary minimum. The receiver of optimal sorting is shown in Fig. 2. There is a counter synchronous with the counter of encoder. A register is used to store the number of counter with the signal tp. The output of the register is expressed as follows: ( ts) ( ts) ( ts) ( ts 1) ( ts 1) ( ts) ( ts 1) regv = cont &( tp tp ) + regv & ( tp tp ) where regv is the output of register, cont is the number of the counter. When transition occurs on tp line, the register stores the number of the counter; otherwise, the register is latched. After the N! clock cycles, the number of the register will index the optimal sorting. tp RESET REGISTER COUNTER pclock sorting index book N!-2 N!-1 Optimal sorting Fig. 2 The Receiver of Optimal Sorting Pattern 3.3 Experimental Results To evaluate the proposed encoding technique, we have generated detailed address bus traces for a number of SPEC2000 benchmarks using a simulator called simplescalar. Each trace consists of 10 million instructions. The used benchmark programs are gzip, gcc, mcf, equake and ammp. The different encoding techniques are applied to measure the change in switching activit ies. Table 2 show s the signal transition reduction ratios of each encoding method. The signal transition reduction ratio means the ratio between the number of signal transitions of the raw instruction address and the encoded address. We evaluate code, -XOR code, Offset-XOR code for comparison except ORS code. The last row of this table shows the average signal transition reduction ratio over all of the benchmarks for each encoding method. As shown in table 2, ORS encoding method is superior to other encoding methods in terms of signal transition reduction, and the signal transition is reduced to 16.2%. Experimental results indicate that ORS code is very effective and applicable for low power encoding of address bus. Table 2 Signal Transition Reduction Ratio for Each Encoding Method Benchmark Raw - Offset Adaptive Address XOR -XOR -Offset-M gzip gcc mcf equake ammp Average To estimate the actual overhead of the above encoder circuits, we have generated the physical transistor netlist of each encoder circuit. The target technology is 1.8-volt 0.18-µm CMOS process. I/O voltage is 3.3V. A gate-level circuit simulator is used to estimate the power dissipations of the encoders with traced instruction addresses of benchmark programs. The results of a 120 MHz system clock are reported in table 3. In Fig. 3, the percentage of total power saved versus external address bus capacitance is compared with different encoding techniques. 89

5 Table 3 Encoder Area Overhead and Power Dissipation Area of Encoder (µm 2 ) Average Power of Encoder (µw) Power dissipation percentage Ratio 40% 38% 36% 34% 32% 30% 28% 26% 24% 22% 20% 18% 16% 14% 12% - XOR Offset -XOR ORS ORS Offset-Xor -Xor 10% bus capatitance(pf) Fig. 3 Comparison of Power Percentage of Different 4. Conclusions Encoding Techniques We have presented a new address bus encoding method based on the adaptive reordering of the modified offset address bus lines. ORS encoding method reorders the modified offset address bus lines with high toggling probability, and the sorting index book is introduced to transmit the optimal sorting. The experimental results based on an instruction set simulator and SPEC2000 benchmarks show that ORS encoding method can reduce signal transitions on the address bus by 83.8%, and the actual overhead of the encoder circuit is estimated after encoder has been designed and synthesized with 0.18-µm CMOS technology. The results show that this encoding method is superior to the previous encoding methods in terms of signal transition reduction on the address bus, and it is very effective and applicable for low power encoding of address bus. References: [1] M. Pedram, Power Minimization in IC Design: Principles and Applications, ACM Trans. Design Automation Electron, Syst., 1996, 1(1): pp [2] V. Tiwari, D. Singh, S. Rajgopal, G. Mehta, R. Patel, F. Baez, Reducing Power in High-performance Microprocessors, in Proc. 35th Design Automation Conf., 1998: pp [3] M. Gowan, L. Brio, B. Jackson, Power Considerations in the Design of the Alpha Microprocessor, in Proc. 35th Design Automation Conf., 1998: pp [4] L. Benini, G. De Micheli, E. Macii, D. Sciuto, C. Silvano, Asymptotic Zero-Transition Activity Encoding for Address Buses in Low-Power Microprocessor-Based Systems, IEEE 7th Great Lakes Symposium on VLSL, 1997: pp [5] L. Benini, G. De Micheli, E. Macii, D. Sciuto, C. Silvano, Address Bus Encoding Techniques for System-Level Power Optimization, Design Automation and Test in Europe, 1998: pp [6] C. L. Su, C. Y. Tsui, A. M. Despain, Saving Power in the Control Path of Embedded Processors, IEEE Design Test Comput., 1994 (11): pp [7] W. C. Cheng, M. Pedram, Power-optimal Encoding for DRAM Address Bus, in Proc. Int. Symp. Low-Power Electron. Design, 2000: pp [8] R. Murgai, M. Fujita, A. Oliveria, Using Complementation and Resequencing to Minimize Transitions, in Proc. Design Automation Conf., 1998: pp [9] R. Murgai, M. Fujita, On Reducing Transition through Data Modifications, in Proc. of Design Automation Test Europe, 1999: pp [10] W. Fornaciari, M. Polentarutti, D. Sciuto, C. Silvano, Power Optimization of System-Level Address Buses Based on Software Profiling, CODES, 2000: pp [11] L. Benini, G. De Michelli, E. Macii, M. Poncino, S. Quer, System-Level Power Optimization of Special Purpose Applications: The Beach Solution, IEEE Symposium on Low Power Electronics and Design, 1997: pp [12] Hennessy, Patterson, Computer Architecture, A Quantitative Approach, Second Edition, Morgan Kaufinann Publishers, (Editors: Julia, Ivan, Susan) 90