EE382V: Embedded System Design and Modeling

Transcription

1 EE382V: Embedded System Design and System-Level Design Tools Andreas Gerstlauer Electrical and Computer Engineering University of Texas at Austin : Outline Overview System-level design landscape System-level design tools Commercial tools Academic tools SCE commercialization ELEGANT environment Specify-Explore-Refine (SER) tools EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer A. Gerstlauer 1

2 Electronic System-Level (ESL) Landscape Arbiter CPU Mem SPIRIT/IP-XACT (XML) Bridge MARTE (UML) B1 C1 B2 v1 Computation & Communication Matlab/Simulink, C2 LabView, Ptolemy HW IP System Synthesis Platform library Front-End Application specification SCE,?? System-Level Design Languages (SLDLs) VaST, OVP, Instruction-Set Simulator (ISS) Green Hills, gcc, VxWorks, Transaction-Level Models TLM n C/C++ code Software // Hardware Synthesis Back-End Tensilica B3 C-based RTL SystemC, CoWare, B4 Mentor Catapult, Forte, Software Object Code Hardware Synopsys Design VHDL/Verilog Compiler, EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 3 ESL Tools Electronic System-Level (ESL) terminology misused Often single hardware unit only (high-level HW synthesis) System-level has to span across hardware and software System-level frontend Hardware and software synthesis backend Commercial tools for modeling and simulation Algorithmic modeling (MoC) [UML, Matlab/Simulink, Labview] Virtual system prototyping (TLM) [Coware, VaST, Virtutech] Only horizontal integration across models / components Academic tools for synthesis and verification MPSoC synthesis [SCE, Metropolis, SCD, PeaCE, Deadalus] Vertical integration for path to implementation EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer A. Gerstlauer 2

3 Commercial Tools (1) CoFluent SystemC-based modeling and simulation Networks of timed processes Communication through queues, events, variables Early, high-level interactive design space exploration Graphical application, architecture and mapping capture Fast TLM simulation with estimated timing Space Codesign Graphical application, architecture and mapping capture (Eclipse) Process network with message-passing or shared-memory channels SystemC TLM simulation Annotated, host-compiled or cycle-accurate ISS models FPGA-based prototyping Cross-compilation and third-party hardware synthesis (Forte/Catapult) EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 5 Commercial Tools (2) CoWare Virtual system platforms SystemC TLM capture, modeling and simulation Extensive library of IP, processor and bus models Application-specific processor ISS models (LISAtek acquisition) Proprietary SystemC simulation framework Optimized SystemC kernel Graphical debugging, visualization and analysis capabilities Soc Designer Proprietary, C++ based modeling and simulation Fast, statically scheduled cycle-accurate simulation Special cycle-callable component models VaST and Virtutech Proprietary SW-centric virtual platform modeling and simulation Fast, cycle-approximate binary translated or compiled ISS + peripherals EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer A. Gerstlauer 3

4 Academic Tools Metropolis Platform-based design (PBD) SystemCoDesigner Dynamic dataflow MoC Automated design space exploration Daedalus KPN MoC for streaming, multi-media applications IP-based MPSoC assembly PeaCE Ptolemy extension as a Codesign Environment Recent extensions for software development (HoPES) SCE SpecC-based System-on-Chip Environment Successive, stepwise Specify-Explore-Refine methodology EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 7 Academic Tools: Metropolis Platform-based Pre-defined target architecture Reuse Meet-in-the-middle Platform mapping and configuration General, proprietary meta-modeling language Capture function, architecture and mapping framework Built-in parsing and simulation Back-end point tool integration EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer A. Gerstlauer 4

5 Academic Tools: SystemCoDesigner SysteMoC input model Dynamic dataflow MoC (actors + FSMDs) in SystemC Fully automatic, multi-objective design space exploration Multi-objective evolutionary algorithms (MOEAs) EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 9 Academic Tools: Daedalus KPN input model System assembly and simulation Explore, modify, select instances Sequential application Highlevel Models System-level design space exploration Automatic Parallelization Library of IP cores Common XML Interface Platform specification Mapping specification Parallel application specification (KPN) RTL-level Models XML-based open infrastructure System-level synthesis Multi-processor System on Chip (Synthesizable VHDL and C/C++ code for processors) EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer A. Gerstlauer 5

6 Coren Coren Coren Coren Core1 Coren EE382V: Embedded Sys Dsgn and Academic Tools: PeaCE Ptolemy-based Heterogeneous SDF+FSM application MoC Stepwise flow Application partitioning Communication architecture exploration Code and interface generation Software extensions: HOPES Parallel programming API Multi-processor code generation EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 11 System-On-Chip Environment (SCE) Specification Spec Design Decisions System Design Architecture Exploration Scheduling Exploration Network Exploration Communication Synthesis PE/OS Models CE/Bus Models Compile onto MPSoC platform CPU B1 B2 CPU Bus OS + Drv C1 C2 Mem v1 v2 C3 DSP B3 DSP Bus C4 OS + Drv TLM n TLMn TLMi System models Arch n Archn TLMn B4 HW Synthesize target HW/SW IP B5 RTL DB Hardware Synthesis Software Synthesis SW DB CPU ISS B1 RTOS HAL Mem DSP ISS B2,B3 RTOS HAL HWn.v HWn.v HWn.v RTLn RTLn RTLn ISSn ISSn ISSn Implementation Model CPUn.bin CPUn.bin CPUn.bin Arbiter Impl Impl n Impln n CPU Bus HW B4 Bridge DSP Bus IP B5 EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer A. Gerstlauer 6

7 Academic MPSoC Design Tools Approach DSE Comp. decision Comm. decision Comp. refine Comm. refine Daedalus Koski Metropolis PeaCE/HoPES SCE SystemCoDesigner EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 13 : Outline Overview System-level design landscape System-level design tools Commercial tools Academic tools SCE commercialization ELEGANT environment Specify-Explore-Refine (SER) tools EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer A. Gerstlauer 7

8 ELEGANT Environment Specification model Specification model simulation VisualSpec InterDesign Technologies Venus Fujitsu Formal verification Exploration and Refinement PE / CE / Bus database SER UCI TLM Co-simulation TLM Software synthesis CyberWorkBench NEC Cycle-accurate Co-simulation High-level synthesis Assertion/Property checking Software source code Hardware RTL ELEGANT : Electronic Design Guidance Tool for Space Use Source: InterDesign Technologies, Inc. / Japanese Aerospace Exploration Agency (JAXA) EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 15 ELEGANT SpaceWire Evaluation SpaceWire: aerospace communication protocol standard High-speed and high-reliability interconnection network Asynchronous, fault-tolerance, topology agnostic Automated SpaceWire design with ELEGANT tool set From top-level specification model down to HW/SW HW/SW partitioning and exploration of the architecture with SER Synthesis down to SpaceCube prototyping platform SpW Specification Model Share/reuse SpW design with high-level descriptions Evaluate HW/SW tradeoffs before implementation ELEGANT HW/SW partitioning and synthesis SpW implemented in HW SpW implemented in HW and SW Sp W Source: Japanese Aerospace Exploration Agency (JAXA) Sp W Micro computer SpaceCube EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer A. Gerstlauer 8

9 ELEGANT MPEG4 Decoder Evaluation MPEG4 decoder implementation Third-party evaluation by JAXA and Applistar, Inc. input MPEG4 decoder VLD DEQ IDCT + output QCIF size, YUV format QCIF size, simple profile MD MC mem VLD: variable length decoding DEQ: de-quantization IDCT: inverse discrete cosine transform MD: motion vector decoding MC: motion compensation Explore design alternatives by SER HR5000 MIPS 5kf All MPEG4 decoder on SW HR5000 MIPS 5kf HR5000 MIPS 5kf HR5000 MIPS 5kf HR MIPS-class 64-bit MPU for space apps. MIPS5kf core Eureka ES510 system controller MBus FPGA FPGA FPGA FPGA IDCT MC IDCT MC EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer 17 ELEGANT MPEG4 Design Explorations Final implementation delays simulated using single testbench Synthesis to RTL and cycle-accurate (CA) model Synthesis from SER-generated pin-accurate communication model (PAM) FPGA model is CA-SpecC model generated by NEC s CyberWorkbench Co-simulation with ELEGANT system model HR5000 CPU model is generated by SER Back-annotated timing with Fastveri for SW behaviors Comparison of design alternatives Decoding delay [m CPU CPU+IDCT CPU+MC CPU+2xHW HR5000 MIPS 5kf FPGA IDCT FPGA MC Source: JAXA and Applistar, Inc. Performance estimation Target performance (30 frames/s) can been estimated/verified 80MHz CPU/bus/HW clock freq. achieves 30 frames/s performance MBus EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer A. Gerstlauer 9

10 : Summary System-level design tools Commercial focus still only on modeling and simulation Academic approaches towards true system-level design Emerging commercial backend HW/SW synthesis Complete, automated system design flow From specification to implementation ELEGANT environment Full industrial system-level design solution Integrated tools for modeling, synthesis & verification Deployed in, e.g. NEC Toshiba Space Systems EE382V: Embedded Sys Dsgn and, 2010 A. Gerstlauer A. Gerstlauer 10