Design in the Late-Silicon Age

Transcription

1 Design in the Late-Silicon Age Jan M. Rabaey University of Berkeley Director MARCO Gigascale System Research Center DUSD(Labs)

2 History Proceeds along Ages 280M 12M Permian Triasic Jurassic Cretaceous Tertiary Quarternary 2.5M 3500BC 1500BC Stone Bronze Iron Old (Paleolithic) Middle (Mesolitic) New (Neolitic) Transitions between era s most often are marked by mass extinctions

3 So Does the Electronics Age Pre-silicon 1950 s Late 2010 s Silicon Post-silicon silicon Early-Silicon 70 s Late 90 s Silicon Late-Silicon The Custom Era The ASIC Age?? How to avoid the mass extinctions that typically go with transitions between ages?

4 ASICs on the Road to Extinction (?) ASIC/ASSP Design Starts ASIC ASSP * 2003* 2004* 2005* 2006* Courtesy R. Camposano, Synopsys

5 NRE: The Triple Whammy Relative Price Mask Cost Technology Node [nm] Engineering Man-Years Complexity and DSM 90 nm 0.13nm Gate Counts in Millions of Gates Source: Xilinx and Synopsys,, Inc

6 An Era of Fewer, Flexible and Reusable Components Berkeley Pleiades Xilinx Vertex Pro Janus Chip - ST Micro and Parades Platforms have taken a firm ground in application areas ranging from wireless, automotive, consumer, media processing, graphics and gamingg

7 Managing Flexibility and Concurrency Dramatically more SOC programmers than SOC designers Easier to create heterogeneous concurrency than to use it! RTOS CC Many Others System C VHDL The language soup Need tools and frameworks that support multiple Models-of of- Computation in a seamless and expandable way. The Metropolis Environment (Sangiovanni( Sangiovanni,, UCB)

8 Watch Out for Paradigm-Shifting Surprises Structured ASIC or the return of gate arrays minimized mask cost manufacturable 50% area overhead for similar performance example: VPGA (CMU) Maskless Lithography Eliminates mask cost Puts some constraints on design No to be expected any day, though

9 The Grand Challenges of the Late Silicon Era (1) Power and Energy Puts Bounds on Integration and Performance Limits the deployment of truly ambient electronics Courtesy IBM Berkeley PicoNode

10 The Grand Challenges of the Late Silicon Era (2) Uncertainty Process Variability puts Synchronous Design Paradigm under Severe Stress Courtesy Intel

11 The Grand Challenges of the Late Silicon Era (3) Reliability Errors Can and Will Happen Soft errors already a fact Process scaling reduces SNR

12 Some Bold Solutions (1) Aggressive Voltage Scaling Performance through concurrency Dynamic adaptation of supply and threshold voltages Careful orchestration of system activity MAC > 1X Scaling? Chandrakasan (MIT): 175 mv DSP (ISSCC 02) NEEDS SYSTEM-LEVEL APPROACH!

13 Some Bold Solutions (2) Abandon the Purely Synchronous Paradigm Late Binding Let the system make the timing decisions Allow occasional timing errors to happen and deal with them! 3 mm I-Cache Register File IF ID EX MEM D-Cache WB 3 mm Razor (U. Mich): Pseudo-synchronous synchronous Pleiades (Berkeley): Globally Asynchronous Locally Synchronous NEEDS SYSTEM-LEVEL APPROACH!

14 Some Bold Solutions (3) Self-Correcting Architectures Designs that detect and correct errors Careful use of redundancy and error correction Provide reliable computation layered on un-reliable fabrics (as in the communications world) Alpha mm 2 REMORA Checker 12 mm 2 Self-checking processor (U. Mich) Stanford NEEDS SYSTEM-LEVEL APPROACH!

15 Transitioning to the Post-Silicon Age Organic (polymer) Nanotube Molecular Implementation platforms that work under very low SNR, are non-deterministic, unpredictable and unreliable

16 Daunting Perspectives? You bet! The search for solutions needs the attention of the brightest minds all over the country and the world. Hence the MARCO Focus Research Center Program! Bringing together in a collaborative setting the leading minds in i design technology for electronics systems

17 Daunting Perspectives? You bet! The search for solutions needs the attention of the brightest minds m all over the country and the world. Hence the MARCO Focus Research Center Program! Gigascale System Research Center (GSRC) The design, verification, and test of complex, heterogeneous embedded systems-on-a-chip/package, covering the complete spectrum from system specification to implementation on emerging circuit fabrics.

18 Summary The semiconductor industry is facing a challenging time. Radically new disruptive solutions are needed. The GSRC collaborative model to paradigm-shifting research has proven to be very successful. Not Just Research as Usual Supporting the transition from the late to the post silicon age Avoiding Mass-Extinctions Through Preventive Action

19 Thank you! Thank you!