Proceedings of. The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002)

Transcription

1 Proceedings of The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002)

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3 Proceedings of The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002) July 2002 Isle of Bendor, France Editors Bernard Courtois Thomas Wik Yervant Zorian Sponsored by IEEE Computer Society IEEE Computer Society Technical Council on Test Technology IEEE Computer Society Technical Committee on VLSI In cooperation with IEEE Solid State Circuits Society Los Alamitos, California Washington Brussels Tokyo

4 Copyright 2002 by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved Copyright and Reprint Permissions: Abstracting is permitted with credit to the source. Libraries may photocopy beyond the limits of US copyright law, for private use of patrons, those articles in this volume that carry a code at the bottom of the first page, provided that the per-copy fee indicated in the code is paid through the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA Other copying, reprint, or republication requests should be addressed to: IEEE Copyrights Manager, IEEE Service Center, 445 Hoes Lane, P.O. Box 133, Piscataway, NJ The papers in this book comprise the proceedings of the meeting mentioned on the cover and title page. They reflect the authors opinions and, in the interests of timely dissemination, are published as presented and without change. Their inclusion in this publication does not necessarily constitute endorsement by the editors, the IEEE Computer Society, or the Institute of Electrical and Electronics Engineers, Inc. IEEE Computer Society Order Number PR01617 ISBN ISBN (bookbroker) ISBN X (microfiche) ISSN Additional copies may be ordered from: IEEE Computer Society IEEE Service Center IEEE Computer Society Customer Service Center 445 Hoes Lane Asia/Pacific Office Los Vaqueros Circle P.O. Box 1331 Watanabe Bldg., P.O. Box 3014 Piscataway, NJ Minami-Aoyama Los Alamitos, CA Tel: Minato-ku, Tokyo Tel: Fax: JAPAN Fax: Tel: cs.books@computer.org customer-service@ieee.org Fax: tokyo.ofc@computer.org Editorial production by Stephanie Kawada Cover art production by Alex Torres Printed in the United States of America by The Printing House

5 MTDT 2002 Table of Contents Message from the Chairs...x Conference Committee...xi TTTC Information Joint Session with The Eighth IEEE International On-Line Testing Workshop (IOLTW 2002) Session A: Plenary Session Keynote Address Embedded Memory Test and Repair A. Kablanian Session B: Memory BIST Analysis and Application Chair: B. Courtois Defect-Oriented Analysis of Memory BIST Tests... 7 A. Jee A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques D. Appello, A. Fudoli, V. Tancorre, F. Corno, M. Rebaudengo, and M. Sonza Reorda v

6 A Scan-Bist Environment for Testing Embedded Memories F. Karimi and F. Lombardi Session C: Memory ECC and Soft Errors Chair: C. Hawkins Soft Error Protection for Embedded Memories M. Nicolaidis Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories D. Rossi, C. Metra, and B. Riccò High Speed 15 ns 4 Mbits SRAM for Space Application B. Coloma, P. Delaunay, and O. Husson Session D: High Reliability in Railway and Automotive Systems Chairs: R. Kleihorst S. D Angelo The YATE Fail-Safe Interface: The User s Point of View D. Bied-Charreton, D. Guillon, and B. Jacques Fault Tolerant Insertion and Verification: A Case Study A. Manzone and D. De Costantini Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems L. Schiano, C. Metra, and D. Marino Session E: Embedded Memory Yield Enhancement Chair: F. Lombardi A Silicon-Based Yield Gain Evaluation Methodology for Embedded-SRAMs with Different Redundancy Scenarios E. Rondey, Y. Tellier, and S. Borri A March-Based Fault Location Algorithm for Static Random Access Memories V. A. Vardanian and Y. Zorian A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories R.-F. Huang, J.-F. Li, J.-C. Yeh, and C.-W. Wu Closing of the Joint IOLTW-MTDT Program vi

7 MTDT Plenary Session Keynote Address Challenges and Opportunities Created by the SoC Shockwave M. Templeton Session 1: Embedded Memory Systems and Test Optimization Chair: R. Leung Design and Test of a 9-Port SRAM for a 100 Gb/s STS-1 Switch R. Gibbins, R. D. Adams, T. Eckenrode, M. Ouellette, and Y. Wu Design of Embedded System for Video Coding with Logic-Enhanced DRAM and Configurable Process T. Kaya, I. Shirakawa, R. Miyamoto, and T. Onoye Adder Merged DRAM Architecture M. Hashimoto Session 2: Memory Test Strategies Chair: R. D. Adams March SS: A Test for All Static Simple RAM Faults S. Hamdioui, A. J. van de Goor, and M. Rodgers Random Testing of Multi-Port Static Random Access Memories F. Karimi, F. J. Meyer, and F. Lombardi Session 3: Fault Modeling Chair: C. Soldat A Fault Modeling Technique to Test Memory BIST Algorithms R. Venkatesh, S. Kumar, J. Philip, and S. Shukla Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM M. Redeker, B. F. Cockburn, D. G. Elliott, Y. Xiang, and S. A. Ung vii

8 An Investigation into Crosstalk Noise in DRAM Structures M. Redeker, B. F. Cockburn, and D. G. Elliott Session 4: Embedded Memory Compiler Tutorial Chair: C. Frey A. Shubat D. Gandhi Plenary Session Keynote Address SoC s Trends and Challenges going to 0.10 µm P. Magarshack Session 5: EPROM/EEPROM Design Chair: L. Bellefroid An Automated Design Methodology for EEPROM Cell (ADE) J. M. Portal, L. Forli, H. Aziza, and D. Née A Novel Memory Array Based on an Annular Single-Poly EPROM Cell for Use in Standard CMOS Technology C. Dray and P. Gendrier A New Single Ended Sense Amplifier for Low Voltage Embedded EEPROM Non Volatile Memories C. Papaix and J. M. Daga Session 6: Process Technology and Reliability Chair: TBD Validated 90 nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC) T. Devoivre, M. Lunenborg, C. Julien, J-P. Carrere, P. Ferreira, W. J. Toren, A. VandeGoor, P. Gayet, T. Berger, O. Hinsinger, P. Vannier, Y. Trouiller, Y. Rody, P-J. Goirand, R. Palla, I. Thomas, F. Guyader, D. Roy, B. Borot, N. Planes, S. Naudet, F. Pico, D. Duca, F. Lalanne, D. Heslinga, and M. Haond Converting an Embedded Low-Power SRAM from Bulk to PD-SOI M. R. Casu and P. Flatresse viii

9 Decreasing EEPROM Programming Bias with Negative Voltage, Reliability Impact R. Laffont, J. Razafindramora, P. Canet, R. Bouchakour, and J. M. Mirabel Session 7: Advanced Memory Technologies Panel Chair: B. F. Cockburn Panel on Advanced Embedded Memory Technologies B. F. Cockburn Author Index ix