MC10EP51, MC100EP V / 5V ECL D Flip-Flop with Reset and Differential Clock
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1 3.3V / 5V E Flip-Flop with Reset and ifferential lock escription The M0/00EP5 is a differential clock flip flop with reset. The device is functionally equivalent to the E5 and VE5 devices. The reset input is an asynchronous, level triggered signal. ata enters the master portion of the flip flop when the clock is OW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP5 allow the device to be used as a negative edge triggered flip-flop. The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the K input will be pulled down to V EE and the K input will be biased at V /2. The 00 Series contains temperature compensation. Features 350 ps Typical Propagation elay Maximum Frequency > 3 GHz Typical PE Mode Operating Range: V = 3.0 V to 5.5 V with V EE = 0 V NE Mode Operating Range: V = 0 V with V EE = 3.0 V to 5.5 V Open Input efault State Safety lamp on Inputs Pb Free Packages are vailable SOI SUFFIX SE 75 TSSOP T SUFFIX SE 94R FN MN SUFFIX SE 506 MRKING IGRMS* HEP5 YW HP5 YW 5S M 4 KEP5 YW KP5 YW 3N M 4 H K 5S 3N M = M0 = M00 = M0 = M00 = ate ode Y W = ssembly ocation = Wafer ot = Year = Work Week = Pb Free Package (Note: Microdot may be in either location) *For additional marking information, refer to pplication Note N002/. ORERING INFORMTION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. Semiconductor omponents Industries,, 200 ugust, 200 Rev. 7 Publication Order Number: M0EP5/
2 Table. PIN ESRIPTION RESET 2 R 7 V Q PIN K*, K* FUNTION E lock Inputs Reset* E synchronous Reset * E ata Input Q, Q E ata Outputs K K Flip-Flop Q V EE V V EE EP Positive Supply Negative Supply (FN only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GN) or leave unconnected, floating open. * Pins will default OW when left open. Figure. ead Pinout (Top View) and ogic iagram Table 2. TRUTH TBE H X R H K Z Z X Z = OW to HIGH Transition Q H Table 3. TTRIBUTES s Internal Input Pulldown Resistor Internal Input Pullup Resistor Value 75 k N/ ES Protection Human Body Model Machine Model harged evice Model > 2 kv > 200 V > 2 kv Moisture Sensitivity, Indefinite Time Out of rypack (Note ) Pb Pkg Pb Free Pkg SOI TSSOP FN evel evel evel evel evel 3 evel Flammability Rating Oxygen Index: 2 to 34 U 94 V 0.25 in Transistor ount 65 evices Meets or exceeds JEE Spec EI/JES7 I atchup Test. For additional information, see pplication Note N003/. 2
3 Table 4. MXIMUM RTINGS Parameter ondition ondition 2 Rating V PE Mode Power Supply V EE = 0 V 6 V V EE NE Mode Power Supply V = 0 V 6 V V I PE Mode Input Voltage NE Mode Input Voltage V EE = 0 V V = 0 V I out Output urrent ontinuous Surge V I V 6 V I V EE 6 T Operating Temperature Range 40 to +5 T stg Storage Temperature Range 65 to +50 J Thermal Resistance (Junction to mbient) 0 lfpm 500 lfpm SOI SOI J Thermal Resistance (Junction to ase) Standard Board SOI 4 to 44 J Thermal Resistance (Junction to mbient) 0 lfpm 500 lfpm TSSOP TSSOP J Thermal Resistance (Junction to ase) Standard Board TSSOP 4 to 44 J Thermal Resistance (Junction to mbient) 0 lfpm 500 lfpm FN FN V V m m T sol Wave Solder Pb Pb Free J Thermal Resistance (Junction to ase) (Note 2) FN 35 to 40 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating onditions is not implied. Extended exposure to stresses above the Recommended Operating onditions may affect device reliability. 2. JEE standard multilayer board 2S2P (2 signal, 2 power) Table 5. 0EP HRTERISTIS, PE V = 3.3 V, V EE = 0 V (Note 3) I EE Power Supply urrent m V OH Output HIGH Voltage (Note 4) mv V O Output OW Voltage (Note 4) mv V IH Input HIGH Voltage (Single Ended) mv V I Input OW Voltage (Single Ended) mv Input HIGH Voltage ommon Mode Range (ifferential onfiguration) (Note 5) V I IH Input HIGH urrent I I Input OW urrent NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit 3. Input and output parameters vary : with V. V EE can vary +0.3 V to 2.2 V. 4. ll loading with 50 to V 2.0 V. 5. min varies : with V EE, max varies : with V. The range is referenced to the most positive side of the differential 3
4 Table 6. 0EP HRTERISTIS, PE V = 5.0 V, V EE = 0 V (Note 6) I EE Power Supply urrent m V OH Output HIGH Voltage (Note 7) mv V O Output OW Voltage (Note 7) mv V IH Input HIGH Voltage (Single Ended) mv V I Input OW Voltage (Single Ended) mv Input HIGH Voltage ommon Mode Range (ifferential onfiguration) (Note ) V I IH Input HIGH urrent I I Input OW urrent NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit 6. Input and output parameters vary : with V. V EE can vary +2.0 V to 0.5 V. 7. ll loading with 50 to V 2.0 V.. min varies : with V EE, max varies : with V. The range is referenced to the most positive side of the differential Table 7. 0EP HRTERISTIS, NE V = 0 V; V EE = 5.5 V to 3.0 V (Note 9) I EE Power Supply urrent m I EE Power Supply urrent m VOH Output HIGH Voltage (Note 0) mv V O Output OW Voltage (Note 0) mv V IH Input HIGH Voltage (Single Ended) mv V I Input OW Voltage (Single Ended) mv Input HIGH Voltage ommon Mode Range (ifferential onfiguration) (Note ) V EE V EE V EE V I IH Input HIGH urrent I I Input OW urrent NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit 9. Input and output parameters vary : with V. 0.ll loading with 50 to V 2.0 V.. min varies : with V EE, max varies : with V. The range is referenced to the most positive side of the differential 4
5 Table. 00EP HRTERISTIS, PE V = 3.3 V, V EE = 0 V (Note 2) I EE Power Supply urrent m V OH Output HIGH Voltage (Note 3) mv V O Output OW Voltage (Note 3) mv V IH Input HIGH Voltage (Single Ended) mv V I Input OW Voltage (Single Ended) mv Input HIGH Voltage ommon Mode Range (ifferential onfiguration) (Note 4) V I IH Input HIGH urrent I I Input OW urrent NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit 2.Input and output parameters vary : with V. V EE can vary +0.3 V to 2.2 V. 3.ll loading with 50 to V 2.0 V. 4. min varies : with V EE, max varies : with V. The range is referenced to the most positive side of the differential Table 9. 00EP HRTERISTIS, PE V = 5.0 V, V EE = 0 V (Note 5) I EE Power Supply urrent m V OH Output HIGH Voltage (Note 6) mv V O Output OW Voltage (Note 6) mv V IH Input HIGH Voltage (Single Ended) mv V I Input OW Voltage (Single Ended) mv Input HIGH Voltage ommon Mode Range (ifferential onfiguration) (Note 7) V I IH Input HIGH urrent I I Input OW urrent NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit 5.Input and output parameters vary : with V. V EE can vary +2.0 V to 0.5 V. 6.ll loading with 50 to V 2.0 V. 7. min varies : with V EE, max varies : with V. The range is referenced to the most positive side of the differential 5
6 Table 0. 00EP HRTERISTIS, NE V = 0 V; V EE = 5.5 V to 3.0 V (Note ) I EE Power Supply urrent m V OH Output HIGH Voltage (Note 9) mv V O Output OW Voltage (Note 9) mv V IH Input HIGH Voltage (Single Ended) mv V I Input OW Voltage (Single Ended) mv Input HIGH Voltage ommon Mode Range (ifferential onfiguration) (Note 20) V EE V EE V EE V I IH Input HIGH urrent I I Input OW urrent NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit.input and output parameters vary : with V. 9.ll loading with 50 to V 2.0 V. 20. min varies : with V EE, max varies : with V. The range is referenced to the most positive side of the differential Table. HRTERISTIS V = 0 V; V EE = 3.0 V to 5.5 V or V = 3.0 V to 5.5 V; V EE = 0 V (Note 2) f max Maximum Frequency (Figure 2) > 3 > 3 > 3 GHz t PH, ps t PH Propagation elay to Output ifferential K, K to Q, Q RESET to Q, Q t RR Reset Recovery ps t S t H t PW Setup Time Hold Time Minimum Pulse Width RESET t JITTER ycle to ycle Jitter (Figure 2).2 <.2 <.2 < ps t r Output Rise/Fall Times Q, Q t f (20% 0%) NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit 2.Measured using a 750 mv source, 50% duty cycle clock source. ll loading with 50 to V 2.0 V ps ps ps 6
7 V OUTpp (mv) ÉÉÉÉÉ (JITTER) FREQUENY (MHz) Figure 2. F max /Jitter Measured Simulated JITTER OUT ps (RMS) ÉÉ river evice Q Q Z o = 50 Z o = 50 Receiver evice V TT V TT = V 2.0 V Figure 3. Typical Termination for Output river and evice Evaluation (See pplication Note N020/ Termination of E ogic evices.) 7
8 ORERING INFORMTION evice Package Shipping M0EP5 SOI 9 s / Rail M0EP5G SOI 9 s / Rail M0EP5R2 SOI 2500 / Tape & Reel M0EP5R2G SOI 2500 / Tape & Reel M0EP5T TSSOP 00 s / Rail M0EP5TG TSSOP 00 s / Rail M0EP5TR2 TSSOP 2500 / Tape & Reel M0EP5TR2G M0EP5MNR4G TSSOP FN 2500 / Tape & Reel 000 / Tape & Reel M00EP5 SOI 9 s / Rail M00EP5G SOI 9 s / Rail M00EP5R2 SOI 2500 / Tape & Reel M00EP5R2G SOI 2500 / Tape & Reel M00EP5T TSSOP 00 s / Rail M00EP5TG TSSOP 00 s / Rail M00EP5TR2 TSSOP 2500 / Tape & Reel M00EP5TR2G TSSOP 2500 / Tape & Reel M00EP5MNR4G FN 000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BR0/. Resource Reference of pplication Notes N405/ E lock istribution Techniques N406/ esigning with PE (E at +5.0 V) N503/ EinPS I/O SPiE Modeling Kit N504/ Metastability and the EinPS Family N56/ Interfacing Between VS and E N672/ The E Translator Guide N00/ Odd Number ounters esign N002/ Marking and ate odes N020/ Termination of E ogic evices N066/ Interfacing with EinPS N090/ s of E evices
9 PKGE IMENSIONS X B Y 5 4 S 0.25 (0.00) M Y SOI NB SE ISSUE H M K NOTES:. IMENSIONING N TOERNING PER NSI Y4.5M, ONTROING IMENSION: MIIMETER. 3. IMENSION N B O NOT INUE MO PROTRUSION. 4. MXIMUM MO PROTRUSION 0.5 (0.006) PER SIE. 5. IMENSION OES NOT INUE MBR PROTRUSION. OWBE MBR PROTRUSION SH BE 0.27 (0.005) TOT IN EXESS OF THE IMENSION T MXIMUM MTERI ONITION THRU RE OBSOETE. NEW STNR IS Z H G 0.25 (0.00) M Z Y S X S SETING PNE 0.0 (0.004) N X 45 M J MIIMETERS INHES IM MIN MX MIN MX B G.27 BS BS H J K M 0 0 N S SOERING FOOTPRINT* SE 6: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOERRM/. 9
10 PKGE IMENSIONS TSSOP T SUFFIX PSTI TSSOP PKGE SE 94R 02 ISSUE 0.5 (0.006) T 0.5 (0.006) T U U S 2X /2 PIN IENT S 5 x V K REF (0.004) M T U S V S B U F 0.25 (0.00) M NOTES:. IMENSIONING N TOERNING PER NSI Y4.5M, ONTROING IMENSION: MIIMETER. 3. IMENSION OES NOT INUE MO FSH. PROTRUSIONS OR GTE BURRS. MO FSH OR GTE BURRS SH NOT EXEE 0.5 (0.006) PER SIE. 4. IMENSION B OES NOT INUE INTERE FSH OR PROTRUSION. INTERE FSH OR PROTRUSION SH NOT EXEE 0.25 (0.00) PER SIE. 5. TERMIN NUMBERS RE SHOWN FOR REFERENE ONY. 6. IMENSION N B RE TO BE ETERMINE T TUM PNE -W (0.004) T SETING PNE G ETI E ETI E W MIIMETERS INHES IM MIN MX MIN MX B F G 0.65 BS BS K BS 0.93 BS M
11 PKGE IMENSIONS FN SE ISSUE PIN ONE REFERENE B NOTES:. IMENSIONING N TOERNING PER SME Y4.5M, ONTROING IMENSION: MIIMETERS. 3. IMENSION b PPIES TO PTE TERMIN N IS MESURE BETWEEN 0.25 N 0.30 MM FROM TERMIN. 4. OPNRITY PPIES TO THE EXPOSE P S WE S THE TERMINS. 2 X X 0.0 ÇÇÇ ÇÇÇ ÇÇÇ TOP VIEW E MIIMETERS IM MIN MX REF b BS E 2.00 BS E e 0.50 BS K X SETING PNE 0.0 SIE VIEW (3) 2 e/2 4 X e E2 K 5 X b B NOTE 3 BOTTOM VIEW EinPS is a trademark of Semiconductor omponents Industries, (SI). ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, (SI). SI reserves the right to make changes without further notice to any products herein. SI makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SI assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SI data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SI does not convey any license under its patent rights nor the rights of others. SI products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SI product could create a situation where personal injury or death may occur. Should Buyer purchase or use SI products for any such unintended or unauthorized application, Buyer shall indemnify and hold SI and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SI was negligent regarding the design or manufacture of the part. SI is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBITION ORERING INFORMTION ITERTURE FUFIMENT: iterature istribution enter for ON Semiconductor P.O. Box 563, enver, olorado 027 US Phone: or Toll Free US/anada Fax: or Toll Free US/anada orderlit@onsemi.com N. merican Technical Support: Toll Free US/anada Europe, Middle East and frica Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order iterature: For additional information, please contact your local Sales Representative M0EP5/
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