NB3L553/D. 2.5 V / 3.3 V / 5.0 V 1:4 Clock Fanout Buffer

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1 2.5 V / 3.3 V / 5.0 V :4 lock Fanout Buffer Description The NB3L553 is a low skew to 4 clock fanout buffer, designed for clock distribution in mind. The NB3L553 specifically guarantees low output to output skew. Optimal design, layout and processing minimize skew within a device and from device to device. Features Input/Output lock Frequency up to 200 MHz Low Skew Outputs (35 ps), Typical RMS Phase Jitter (2 khz 20 MHz): 29 fs (Typical) Output goes to Three State Mode via OE Operating Range: V DD = V to 5.25 V 5 V Tolerant Input lock I LK Ideal for Networking locks Packaged in pin SOI Industrial Temperature Range These are Pb Free Devices I LK OE Q Q2 Q3 Q4 Figure. Block Diagram 3L553 L Y W MRKING DIGRMS* SOI D SUFFIX SE 75 = Specific Device ode = ssembly Location = Wafer Lot = Year = Work Week = Pb Free Package DFN MN SUFFIX SE 506 PINOUT DIGRM V DD OE 2 7 Q0 Q3 3 6 Q Q2 4 5 GND I LK 3L553 LYW 6P M 6P = Specific Device ode M = Date ode = Pb Free Package (Note: Microdot may be in either location) *For additional marking information, refer to pplication Note ND002/D. ORDERING INFORMTION Device Package Shipping NB3L553DG NB3L553DR2G SOI (Pb Free) SOI (Pb Free) 9 Units/Rail 2500/Tape & Reel NB3L553MNR4G* DFN (Pb Free) 000/Tape & Reel *ontact Sales Representative For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD0/D. Semiconductor omponents Industries, LL, 200 June, 200 Rev. 7 Publication Order Number: NB3L553/D

2 Table. OE, OUTPUT ENBLE FUNTION OE Function 0 Disable Enable Table 2. PIN DESRIPTION Pin # Name Type Description V DD Power Positive supply voltage (2.375 V to 5.25 V) 2 Q0 (LV)MOS/(LV)TTL Output lock Output 0 3 Q (LV)MOS/(LV)TTL Output lock Output 4 GND Power Negative supply voltage; onnect to ground, 0 V 5 I LK (LV)MOS Input lock Input. 5.0 V tolerant 6 Q2 (LV)MOS/(LV)TTL Output lock Output 2 7 Q3 (LV)MOS/(LV)TTL Output lock Output 3 OE (LV)TTL Input V DD for normal operation. Pin has no internal pullup or pull down resistor for open condition default. Use from to 0 kohms external resistor to force an open condition default state. EP Thermal Exposed Pad (DFN only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. 2

3 Table 3. MXIMUM RTINGS Symbol Parameter ondition ondition 2 Rating Unit V DD Positive Power Supply GND = 0 V 6.0 V V I Input Voltage OE I LK GND = 0 V and V DD = V to 5.25 V GND 0.5 V I V DD GND 0.5 V I 5.75 V T Operating Temperature Range, Industrial 40 to +5 T stg Storage Temperature Range 65 to +50 J Thermal Resistance (Junction to mbient) 0 lfpm 500 lfpm SOI /W /W J Thermal Resistance (Junction to ase) (Note ) SOI 4 to 44 /W J Thermal Resistance (Junction to mbient) 0 lfpm 500 lfpm DFN DFN 29 4 /W /W J Thermal Resistance (Junction to ase) (Note ) DFN 35 to 40 /W Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating onditions is not implied. Extended exposure to stresses above the Recommended Operating onditions may affect device reliability.. JEDE standard multilayer board 2S2P (2 signal, 2 power) Table 4. TTRIBUTES ESD Protection haracteristic Human Body Model Machine Model harged Device Model Value > 2 kv > 50 V > TBD kv Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2) Level Flammability Rating Oxygen Index: 2 to 34 UL 94 code V 0.25 in Transistor ount Meets or Exceeds JEDE Standard EI/JESD7 I Latchup Test 53 Devices 2. For additional Moisture Sensitivity information, refer to pplication Note ND003/D. 3

4 Table 5. D HRTERISTIS (V DD = V to V, GND = 0 V, T = 40 to +5 ) (Note 3) Symbol haracteristic Min Typ Max Unit I DD Power Supply 35 MHz, No Load m V OH Output HIGH Voltage I OH = 6 m.7 V V OL Output LOW Voltage I OL = 6 m 0.4 V V IH, I LK Input HIGH Voltage, I LK (V DD 2) V V IL, I LK Input LOW Voltage, I LK (V DD 2) 0.5 V V IH, OE Input HIGH Voltage, OE. V DD V V IL, OE Input LOW Voltage, OE 0.7 V ZO Nominal Output Impedance 20 IN Input apacitance, I LK, OE 5.0 pf IOS Short ircuit urrent ± 2 m D HRTERISTIS (V DD = 3.5 V to 3.45 V, GND = 0 V, T = 40 to +5 ) (Note 3) Symbol haracteristic Min Typ Max Unit I DD Power Supply 35 MHz, No Load m V OH Output HIGH Voltage I OH = 25 m 2.4 V V OL Output LOW Voltage I OL = 25 m 0.4 V V OH Output HIGH Voltage I OH = 2 m (MOS level) V DD 0.4 V V IH, I LK Input HIGH Voltage, I LK (V DD 2) V V IL, I LK Input LOW Voltage, I LK (V DD 2) 0.7 V V IH, OE Input HIGH Voltage, OE 2.0 V DD V V IL, OE Input LOW Voltage, OE 0 0. V ZO Nominal Output Impedance 20 IN Input apacitance, OE 5.0 pf IOS Short ircuit urrent ± 50 m D HRTERISTIS (V DD = 4.75 V to 5.25 V, GND = 0 V, T = 40 to +5 ) (Note 3) Symbol haracteristic Min Typ Max Unit I DD Power Supply 35 MHz, No Load 45 5 m V OH Output HIGH Voltage I OH = 35 m 2.4 V V OL Output LOW Voltage I OL = 35 m 0.4 V V OH Output HIGH Voltage I OH = 2 m (MOS level) V DD 0.4 V V IH, I LK Input HIGH Voltage, I LK (V DD 2) V V IL, I LK Input LOW Voltage, I LK (V DD 2) V V IH, OE Input HIGH Voltage, OE 2.0 V DD V V IL, OE Input LOW Voltage, OE 0. V ZO Nominal Output Impedance 20 IN Input apacitance, OE 5.0 pf IOS Short ircuit urrent ± 0 m 4

5 Table 6. HRTERISTIS; V DD = 2.5 V 5% (V DD = V to V, GND = 0 V, T = 40 to +5 ) (Note 3) Symbol haracteristic Min Typ Max Unit f in Input Frequency 200 MHz t r /t f Output rise and fall times; 0. V to 2.0 V.0.5 ns t pd Propagation Delay, LK to Q n (Note 4) ns t skew Output to output skew; (Note 5) ps t skew Device to device skew, (Note 5) 500 ps HRTERISTIS; V DD = 3.3 V 5% (V DD = 3.5 V to 3.45 V, GND = 0 V, T = 40 to +5 ) (Note 3) Symbol haracteristic onditions Min Typ Max Unit f in Input Frequency 200 MHz t jitter ( ) RMS Phase Jitter (Integrated 2 khz 20 MHz) (See Figures 2 and 3) f carrier = 00 MHz fs t r /t f Output rise and fall times; 0. V to 2.0 V ns t pd Propagation Delay, LK to Q n (Note 4) ns t skew Output to output skew; (Note 5) ps t skew Device to device skew, (Note 5) 500 ps HRTERISTIS; V DD = 5.0 V 5% (V DD = 4.75 V to 5.25 V, GND = 0 V, T = 40 to +5 ) (Note 3) Symbol haracteristic Min Min Typ Max Unit f in Input Frequency 200 MHz t jitter ( ) RMS Phase Jitter (Integrated 2 khz 20 MHz) (See Figures 2 and 3) f carrier = 00 MHz 29 fs t r /t f Output rise and fall times; 0. V to 2.0 V ns t pd Propagation Delay, LK to Q n (Note 4) ns t skew Output to output skew; (Note 5) ps t skew Device to device skew, (Note 5) 500 ps 3. Outputs loaded with external R L = 33 series resistor and L = 5 pf to GND for proper operation. Duty cycle out = duty in. 0.0 F decoupling capacitor should be connected between V DD and GND. 4. Measured with rail to rail input clock 5. Measured on rising edges at V DD 2 between any two outputs with equal loading. 5

6 Figure 2. Phase Noise Plot at 00 MHz at an Operating Voltage of 3.3 V, Room Temperature The above plot captured using gilent E5052 shows dditive Phase Noise of the NB3L553 device measured with an input source generated by gilent E663B. The RMS phase jitter contributed by the device (integrated between 2 khz to 20 MHz; as shown in the shaded area) is fs (RMS Phase Jitter of the input source is fs and Output (DUT+Source) is 93.6 fs). Figure 3. Phase Noise Plot at 00 MHz at an Operating Voltage of 5 V, Room Temperature The above plot captured using gilent E5052 shows dditive Phase Noise of the NB3L553 device measured with an input source generated by gilent E663B. The RMS phase jitter contributed by the device (integrated between 2 khz to 20 MHz; as shown in the shaded area) is 29 fs (RMS Phase Jitter of the input source is fs and Output (DUT+Source) is 03.5 fs). 6

7 PKGE DIMENSIONS SOI NB SE ISSUE J X B Y 5 4 S 0.25 (0.00) M Y M K NOTES:. DIMENSIONING ND TOLERNING PER NSI Y4.5M, ONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION ND B DO NOT INLUDE MOLD PROTRUSION. 4. MXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INLUDE DMBR PROTRUSION. LLOWBLE DMBR PROTRUSION SHLL BE 0.27 (0.005) TOTL IN EXESS OF THE D DIMENSION T MXIMUM MTERIL ONDITION THRU RE OBSOLETE. NEW STNDRD IS Z H G D 0.25 (0.00) M Z Y S X S SETING PLNE 0.0 (0.004) N X 45 M J MILLIMETERS INHES DIM MIN MX MIN MX B D G.27 BS BS H J K M 0 0 N S SOLDERING FOOTPRINT* SLE 6: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 7

8 PKGE DIMENSIONS DFN SE ISSUE D PIN ONE REFERENE D B NOTES:. DIMENSIONING ND TOLERNING PER SME Y4.5M, ONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b PPLIES TO PLTED TERMINL ND IS MESURED BETWEEN 0.25 ND 0.30 MM FROM TERMINL. 4. OPLNRITY PPLIES TO THE EXPOSED PD S WELL S THE TERMINLS. 2 X X 0.0 ÇÇÇ ÇÇÇ ÇÇÇ TOP VIEW E MILLIMETERS DIM MIN MX REF b D 2.00 BS D E 2.00 BS E e 0.50 BS K 0.20 L X SETING PLNE 0.0 SIDE VIEW (3) D2 e/2 4 X L e E2 K 5 X b B NOTE 3 BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, LL (SILL). SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any license under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should Buyer purchase or use SILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLITION ORDERING INFORMTION LITERTURE FULFILLMENT: Literature Distribution enter for ON Semiconductor P.O. Box 563, Denver, olorado 027 US Phone: or Toll Free US/anada Fax: or Toll Free US/anada orderlit@onsemi.com N. merican Technical Support: Toll Free US/anada Europe, Middle East and frica Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NB3L553/D

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