MC10EP51, MC100EP V / 5VНECL D Flip Flop with Reset and Differential Clock

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3.3V / 5VНEC Flip Flop with Reset and ifferential Clock escription The MC0/00EP5 is a differential clock flip flop with reset. The device is functionally equivalent to the E5 and VE5 devices.

1 3.3V / 5VНEC Flip Flop with Reset and ifferential Clock escription The MC0/00EP5 is a differential clock flip flop with reset. The device is functionally equivalent to the E5 and VE5 devices. The reset input is an asynchronous, level triggered signal. ata enters the master portion of the flip flop when the clock is OW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP5 allow the device to be used as a negative edge triggered flip-flop. The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CK input will be pulled down to V EE and the CK input will be biased at V CC /2. The 00 Series contains temperature compensation. Features 350 ps Typical Propagation elay Maximum Frequency > 3 GHz Typical PEC Mode Operating Range: V CC = 3.0 V to 5.5 V with V EE = 0 V NEC Mode Operating Range: V CC = 0 V with V EE = 3.0 V to 5.5 V Open Input efault State Safety Clamp on Inputs Pb Free Packages are Available SOIC SUFFIX CASE 75 T SUFFIX CASE 94R FN MN SUFFIX CASE 506AA MARKING IAGRAMS* HEP5 AYW HP5 AYW 5S 4 KEP5 AYW KP5 AYW 3N 4 H K 5S 3N = MC0 = MC00 = MC0 = MC00 = ate Code A Y W = Assembly ocation = Wafer ot = Year = Work Week = Pb Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AN002/. ORERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. Semiconductor Components Industries, C, 2006 January, 2006 Rev. 4 Publication Order Number: MC0EP5/

2 Table. PIN ESCRIPTION RESET 2 R 7 V CC Q PIN CK*, CK* FUNCTION EC Clock Inputs Reset* EC Asynchronous Reset * EC ata Input Q, Q EC ata Outputs Flip-Flop V CC V EE Positive Supply Negative Supply CK 3 6 Q * Pins will default OW when left open. Table 2. TRUTH TABE CK 4 5 V EE H X R H CK Z Z X Q H Figure. ead Pinout (Top View) and ogic iagram Z = OW to HIGH Transition Table 3. ATTRIBUTES s Internal Input Pulldown Resistor Internal Input Pullup Resistor Value 75 k N/A ES Protection Human Body Model Machine Model Charged evice Model > 2 kv > 200 V > 2 kv Moisture Sensitivity, Indefinite Time Out of rypack (Note ) Pb Pkg Pb Free Pkg SOIC FN evel evel evel evel evel 3 evel Flammability Rating Oxygen Index: 2 to 34 U 94 V 0.25 in Transistor Count 65 evices Meets or exceeds JEEC Spec EIA/JES7 IC atchup Test. For additional information, see Application Note AN003/. 2

3 Table 4. MAXIMUM RATINGS Parameter Condition Condition 2 Rating Unit V CC PEC Mode Power Supply V EE = 0 V 6 V V EE NEC Mode Power Supply V CC = 0 V 6 V V I PEC Mode Input Voltage NEC Mode Input Voltage V EE = 0 V V CC = 0 V I out Output Current Continuous Surge V I V CC 6 V I V EE 6 T A Operating Temperature Range 40 to +5 C T stg Storage Temperature Range 65 to +50 C JA Thermal Resistance (Junction to Ambient) 0 lfpm 500 lfpm SOIC SOIC JC Thermal Resistance (Junction to Case) Standard Board SOIC 4 to 44 JA Thermal Resistance (Junction to Ambient) 0 lfpm 500 lfpm JC Thermal Resistance (Junction to Case) Standard Board 4 to 44 JA Thermal Resistance (Junction to Ambient) 0 lfpm 500 lfpm T sol Wave Solder Pb Pb Free FN FN Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected V V ma ma C Table 5. 0EP C CHARACTERISTICS, PEC V CC = 3.3 V, V EE = 0 V (Note 2) 40 C 25 C 5 C Min Typ Max Min Typ Max Min Typ Max I EE Power Supply Current ma V OH Output HIGH Voltage (Note 3) mv V O Output OW Voltage (Note 3) mv V IH Input HIGH Voltage (Single Ended) mv V I Input OW Voltage (Single Ended) mv V IHCMR Input HIGH Voltage Common Mode Range (ifferential Configuration) (Note 4) V I IH Input HIGH Current A I I Input OW Current A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary : with V CC. V EE can vary +0.3 V to 2.2 V. 3. All loading with 50 to V CC 2.0 V. 4. V IHCMR min varies : with V EE, V IHCMR max varies : with V CC. The V IHCMR range is referenced to the most positive side of the differential input signal. Unit 3

4 Table 6. 0EP C CHARACTERISTICS, PEC V CC = 5.0 V, V EE = 0 V (Note 5) 4

5 Table. 00EP C CHARACTERISTICS, PEC V CC = 3.3 V, V EE = 0 V (Note ) 40 C 25 C 5 C Min Typ Max Min Typ Max Min Typ Max I EE Power Supply Current ma V OH Output HIGH Voltage (Note 2) mv V O Output OW Voltage (Note 2) mv V IH Input HIGH Voltage (Single Ended) mv V I Input OW Voltage (Single Ended) mv V IHCMR Input HIGH Voltage Common Mode Range (ifferential Configuration) (Note 3) V I IH Input HIGH Current A I I Input OW Current A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously.. Input and output parameters vary : with V CC. V EE can vary +0.3 V to 2.2 V. 2.All loading with 50 to V CC 2.0 V. 3.V IHCMR min varies : with V EE, V IHCMR max varies : with V CC. The V IHCMR range is referenced to the most positive side of the differential input signal. Unit Table 9. 00EP C CHARACTERISTICS, PEC V CC = 5.0 V, V EE = 0 V (Note 4) 40 C 25 C 5 C Min Typ Max Min Typ Max Min Typ Max I EE Power Supply Current ma V OH Output HIGH Voltage (Note 5) mv V O Output OW Voltage (Note 5) mv V IH Input HIGH Voltage (Single Ended) mv V I Input OW Voltage (Single Ended) mv V IHCMR Input HIGH Voltage Common Mode Range (ifferential Configuration) (Note 6) V I IH Input HIGH Current A I I Input OW Current A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4.Input and output parameters vary : with V CC. V EE can vary +2.0 V to 0.5 V. 5.All loading with 50 to V CC 2.0 V. 6.V IHCMR min varies : with V EE, V IHCMR max varies : with V CC. The V IHCMR range is referenced to the most positive side of the differential input signal. Unit 5

6 Table 0. 00EP C CHARACTERISTICS, NEC V CC = 0 V; V EE = 5.5 V to 3.0 V (Note 7) 40 C 25 C 5 C Min Typ Max Min Typ Max Min Typ Max I EE Power Supply Current ma V OH Output HIGH Voltage (Note ) mv V O Output OW Voltage (Note ) mv V IH Input HIGH Voltage (Single Ended) mv V I Input OW Voltage (Single Ended) mv V IHCMR Input HIGH Voltage Common Mode Range (ifferential Configuration) (Note 9) V EE V EE V EE V I IH Input HIGH Current A I I Input OW Current A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7.Input and output parameters vary : with V CC..All loading with 50 to V CC 2.0 V. 9.V IHCMR min varies : with V EE, V IHCMR max varies : with V CC. The V IHCMR range is referenced to the most positive side of the differential input signal. Unit Table. AC CHARACTERISTICS V CC = 0 V; V EE = 3.0 V to 5.5 V or V CC = 3.0 V to 5.5 V; V EE = 0 V (Note 20) 40 C 25 C 5 C Min Typ Max Min Typ Max Min Typ Max f max Maximum Frequency (Figure 2) > 3 > 3 > 3 GHz t PH, ps t PH Propagation elay to Output ifferential CK, CK to Q, Q RESET to Q, Q t RR Reset Recovery ps t S t H t PW Setup Time Hold Time Minimum Pulse Width RESET t JITTER Cycle to Cycle Jitter (Figure 2).2 <.2 <.2 < ps t r Output Rise/Fall Times Q, Q t f (20% 0%) NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 20.Measured using a 750 mv source, 50% duty cycle clock source. All loading with 50 to V CC 2.0 V Unit ps ps ps 6

7 V OUTpp (mv) ÉÉÉÉÉ (JITTER) FREQUENCY (MHz) Figure 2. F max /Jitter Measured Simulated JITTER OUT ps (RMS) ÉÉ river evice Q Q Z o = 50 Z o = 50 Receiver evice V TT V TT = V CC 2.0 V Figure 3. Typical Termination for Output river and evice Evaluation (See Application Note AN020/ Termination of EC ogic evices.) 7

8 ORERING INFORMATION evice Package Shipping MC0EP5 SOIC 9 Units / Rail MC0EP5G SOIC 9 Units / Rail MC0EP5R2 SOIC 2500 / Tape & Reel MC0EP5R2G SOIC 2500 / Tape & Reel MC0EP5T 00 Units / Rail MC0EP5TG 00 Units / Rail MC0EP5TR / Tape & Reel MC0EP5TR2G 2500 / Tape & Reel MC0EP5MNR4 FN 000 / Tape & Reel MC0EP5MNR4G FN 000 / Tape & Reel MC00EP5 SOIC 9 Units / Rail MC00EP5G SOIC 9 Units / Rail MC00EP5R2 SOIC 2500 / Tape & Reel MC00EP5R2G SOIC 2500 / Tape & Reel MC00EP5T 00 Units / Rail MC00EP5TG 00 Units / Rail MC00EP5TR / Tape & Reel MC00EP5TR2G 2500 / Tape & Reel MC00EP5MNR4 FN 000 / Tape & Reel MC00EP5MNR4G FN 000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BR0/. Resource Reference of Application Notes AN405/ EC Clock istribution Techniques AN406/ esigning with PEC (EC at +5.0 V) AN503/ ECinPS I/O SPiCE Modeling Kit AN504/ Metastability and the ECinPS Family AN56/ Interfacing Between VS and EC AN642/ The EC Translator Guide AN00/ Odd Number Counters esign AN002/ Marking and ate Codes AN020/ Termination of EC ogic evices AN066/ Interfacing with ECinPS AN090/ AC s of EC evices

9 PACKAGE IMENSIONS SOIC NB CASE ISSUE AG 9

10 PACKAGE IMENSIONS T SUFFIX PASTIC TSSOP PACKAGE CASE 94R 02 ISSUE A 0.5 (0.006) T 0.5 (0.006) T U U S 2X /2 PIN IENT S 5 x A V K REF (0.004) M T U S V S B U F 0.25 (0.00) M NOTES:. IMENSIONING AN TOERANCING PER ANSI Y4.5M, CONTROING IMENSION: MIIMETER. 3. IMENSION A OES NOT INCUE MO FASH. PROTRUSIONS OR GATE BURRS. MO FASH OR GATE BURRS SHA NOT EXCEE 0.5 (0.006) PER SIE. 4. IMENSION B OES NOT INCUE INTEREA FASH OR PROTRUSION. INTEREA FASH OR PROTRUSION SHA NOT EXCEE 0.25 (0.00) PER SIE. 5. TERMINA NUMBERS ARE SHOWN FOR REFERENCE ONY. 6. IMENSION A AN B ARE TO BE ETERMINE AT ATUM PANE W. 0.0 (0.004) T SEATING PANE C G ETAI E ETAI E W MIIMETERS INCHES IM MIN MAX MIN MAX A B C F G 0.65 BSC BSC K BSC 0.93 BSC M

11 PACKAGE IMENSIONS FN CASE 506AA 0 ISSUE C PIN ONE REFERENCE A B NOTES:. IMENSIONING AN TOERANCING PER ASME Y4.5M, CONTROING IMENSION: MIIMETERS. 3. IMENSION b APPIES TO PATE TERMINA AN IS MEASURE BETWEEN 0.25 AN 0.30 MM FROM TERMINA. 4. COPANARITY APPIES TO THE EXPOSE PA AS WE AS THE TERMINAS. 2 X 0.0 C 2 X 0.0 ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ C TOP VIEW E MIIMETERS IM MIN MAX A A A REF b BSC E 2.00 BSC E e 0.50 BSC K C A X SEATING PANE 0.0 C A SIE VIEW (A3) C 2 e/2 4 X e E2 K 5 X b 0.0 C 0.05 C A B NOTE 3 BOTTOM VIEW ECinPS is a trademark of Semiconductor Components Industries, C (SCIC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, C (SCIC). SCIC reserves the right to make changes without further notice to any products herein. SCIC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCIC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCIC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCIC does not convey any license under its patent rights nor the rights of others. SCIC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCIC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCIC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCIC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCIC was negligent regarding the design or manufacture of the part. SCIC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBICATION ORERING INFORMATION ITERATURE FUFIMENT: iterature istribution Center for ON Semiconductor P.O. Box 632, Phoenix, Arizona USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2 9 Kamimeguro, Meguro ku, Tokyo, Japan Phone: ON Semiconductor Website: Order iterature: For additional information, please contact your local Sales Representative. MC0EP5/

MARKING DIAGRAMS* ORDERING INFORMATION 8 1 SO 8 D SUFFIX CASE 751 KEP51 ALYW HEP51 ALYW 8 1 TSSOP 8 DT SUFFIX CASE 948R KP51 ALYW

MARKING DIAGRAMS* ORDERING INFORMATION 8 1 SO 8 D SUFFIX CASE 751 KEP51 ALYW HEP51 ALYW 8 1 TSSOP 8 DT SUFFIX CASE 948R KP51 ALYW The MC0/EP5 is a differential clock flip flop with reset. The device is functionally equivalent to the E5 and VE5 devices. The reset input is an asynchronous, level triggered signal. ata enters the master