MC10E137, MC100E VНECL 8-Bit Ripple Counter

Transcription

1 5 НEC 8-Bit ipple Counter escription The MC10E/100E137 is a very high speed binary ripple counter. The two least significant bits were designed with very fast edge rates while the more significant bits maintain standard ECinPS output edge rates. This allows the counter to operate at very high frequencies while maintaining a moderate power dissipation level. The device is ideally suited for multiple frequency clock generation as well as a counter in a high performance ATE time measurement board. Both asynchronous and synchronous enables are available to maximize the device s flexibility for various applications. The asynchronous enable input, A_Start, when asserted enables the counter while overriding any synchronous enable signals. The E137 features XOed enable inputs, EN1 and EN2, which are synchronous to the CK input. When only one synchronous enable is asserted the counter becomes disabled on the next CK transition; all outputs remain in the previous state poised for the other synchronous enable or A_Start to be asserted to re-enable the counter. Asserting both synchronous enables causes the counter to become enabled on the next transition of the CK. If EN1 (or EN2) and CK edges are coincident, sufficient delay has been inserted in the CK path (to compensate for the XO gate delay and the internal -flip flop setup time) to insure that the synchronous enable signal is clocked correctly, hence, the counter is disabled. All input pins left open will be pulled OW via an input pulldown resistor. Therefore, do not leave the differential CK inputs open. oing so causes the current source transistor of the input clock gate to become saturated, thus upsetting the internal bias regulators and jeopardizing the stability of the device. The asynchronous Master eset resets the counter to an all zero state upon assertion. The BB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to BB as a switching reference voltage. BB may also rebias AC coupled inputs. When used, decouple BB and CC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 ma. When not used, BB should be left open. The 100 Series contains temperature compensation. PCC 28 FN SUFFIX CASE 776 MAKING IAGAM* MCxxxE137FNG AWYYWW xxx = 10 or 100 A = Assembly ocation W = Wafer ot YY = Year WW = Work Week G = Pb Free Package *For additional marking information, refer to Application Note AN8002/. OEING INFOMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. 1 Features ifferential Clock Input and ata Output Pins BB Output for Single-Ended Use Synchronous and Asynchronous Enable Pins Asynchronous Master eset PEC Mode Operating ange: CC = 4.2 to 5.7 with EE = 0 NEC Mode Operating ange: CC = 0 with EE = 4.2 to 5.7 Internal Input 50 k Pull down esistors Transistor Count = 330 devices ES Protection: uman Body Model: > 2 k, Machine Model: > 200 Meets or Exceeds JEEC Spec EIA/JES78 IC atchup Test Moisture Sensitivity evel: Pb = 1; Pb Free = 3 For Additional Information, see Application Note AN8003/ Flammability ating: U in, Oxygen Index: 28 to 34 Pb Free Packages are Available* *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques eference Manual, SOEM/. Semiconductor Components Industries, C, 2006 November, 2006 ev. 8 1 Publication Order Number: MC10E137/

2 CCO 5 5 Table 1. PIN ESCIPTION A_Start PIN FUNCTION EN1 EN2 EE Pinout: 28-ead PCC (Top iew) CC 3 CK, CK 0-7, 0-7 A_Start EN1, EN2 M EC ifferential Clock Inputs EC ifferential Outputs EC Asynchronous Enable Input EC Synchronous Enable Inputs Asynchronous Master eset CK BB eference oltage Output CK CC, CCO EE Positive Supply Negative Supply BB M CCO CCO * All CC and CCO pins are tied together on the die. Warning: All CC, CCO, and EE pins must be externally connected to Power Supply to guarantee proper operation. Figure ead Pinout A_Start EN1 EN CK CK CK CK BB CK CK CK CK CK CK M Figure 2. ogic iagram 2

3 3 Table 2. SEUENTIA TUT TABE Function EN1 EN2 A_Start M CK eset X X X X Count Stop Asynch Start Count Stop Synch Start Stop Count eset X X X X = ow to igh Transition Table 3. MAXIMUM ATINGS Parameter Condition 1 Condition 2 ating Unit CC PEC Mode Power Supply EE = 0 8 EE NEC Mode Power Supply CC = 0 8 I PEC Mode Input oltage NEC Mode Input oltage EE = 0 CC = 0 I CC I EE 6 6 I out Output Current Continuous Surge ma ma T A Operating Temperature ange 0 to +85 C T stg Storage Temperature ange 65 to +150 C JA Thermal esistance (Junction to Ambient) 0 lfpm 500 lfpm PCC 28 PCC C/W C/W JC Thermal esistance (Junction to Case) Standard Board PCC to 26 C/W EE PEC Operating ange NEC Operating ange 4.2 to to 4.2 T sol Wave Solder Pb Pb Free C Stresses exceeding Maximum atings may damage the device. Maximum atings are stress ratings only. Functional operation above the ecommended Operating Conditions is not implied. Extended exposure to stresses above the ecommended Operating Conditions may affect device reliability.

4 Table 4. 10E SEIES PEC C CAACTEISTICS CCx = 5.0 ; EE = 0.0 (Note 1) Min Typ Max Min Typ Max Min Typ Max Unit I EE Power Supply Current ma O Output IG oltage (Note 2) m 70 O Output OW oltage (Note 2) m I Input IG oltage (Single Ended) m I Input OW oltage (Single Ended) m BB Output oltage eference ICM Input IG oltage Common Mode ange (ifferential Configuration) (Note 3) I I Input IG Current A I I Input OW Current A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit 1. Input and output parameters vary 1:1 with CC. EE can vary 0.46 / Outputs are terminated through a 50 resistor to CC ICM min varies 1:1 with EE, max varies 1:1 with CC. Table 5. 10E SEIES NEC C CAACTEISTICS CCx = 0.0 ; EE = 5.0 (Note 4) Min Typ Max Min Typ Max Min Typ Max I EE Power Supply Current ma O Output IG oltage (Note 5) m O Output OW oltage (Note 5) m I Input IG oltage (Single Ended) m I Input OW oltage (Single Ended) m BB Output oltage eference ICM Input IG oltage Common Mode ange (ifferential Configuration) (Note 6) I I Input IG Current A I I Input OW Current A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit 4. Input and output parameters vary 1:1 with CC. EE can vary 0.46 / Outputs are terminated through a 50 resistor to CC ICM min varies 1:1 with EE, max varies 1:1 with CC. Unit 4

5 Table E SEIES PEC C CAACTEISTICS CCx = 5.0 ; EE = 0.0 (Note 7) Min Typ Max Min Typ Max Min Typ Max I EE Power Supply Current ma O Output IG oltage (Note 8) m O Output OW oltage (Note 8) m I Input IG oltage (Single Ended) m I Input OW oltage (Single Ended) m BB Output oltage eference ICM Input IG oltage Common Mode ange (ifferential Configuration) (Note 9) I I Input IG Current A I I Input OW Current A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit 7. Input and output parameters vary 1:1 with CC. EE can vary 0.46 / Outputs are terminated through a 50 resistor to CC ICM min varies 1:1 with EE, max varies 1:1 with CC. Unit Table E SEIES NEC C CAACTEISTICS CCx = 0.0 ; EE = 5.0 (Note 10) Min Typ Max Min Typ Max Min Typ Max I EE Power Supply Current ma O Output IG oltage (Note 11) m O Output OW oltage (Note 11) m I Input IG oltage (Single Ended) m Unit I Input OW oltage (Single Ended) m BB Output oltage eference ICM Input IG oltage Common Mode ange (ifferential Configuration) (Note 12) I I Input IG Current A I I Input OW Current A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit 10.Input and output parameters vary 1:1 with CC. EE can vary 0.46 / Outputs are terminated through a 50 resistor to CC ICM min varies 1:1 with EE, max varies 1:1 with CC. 5

6 Table 8. AC CAACTEISTICS CCx = 5.0 ; EE = 0.0 or CCx = 0.0 ; EE = 5.0 (Note 13) Min Typ Max Min Typ Max Min Typ Max f COUNT Maximum Count Frequency Mz t P t P Propagation elay to Output CK to 0 CK to 1 CK to 2 CK to 3 CK to 4 CK to 5 CK to 6 CK to 7 A_Start to 0 M to t s Setup Time (EN1, EN2) ps t h old Time (EN1, EN2) ps t eset ecovery Time M, A_Start Unit ps ps t PW Minimum Pulse Width CK, M, A_Start ps PP Input oltage Swing CK/CK (ifferential Configuration) (Note 14) t JITTE andom Clock Jitter (MS) < 1 < 1 < 1 ps t r t f ise/fall Times (20% 80%) 0,1 2 to ps NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit Series: EE can vary 0.46 / Series: EE can vary 0.46 / Minimum input swing for which AC parameters are guaranteed. Full C EC output swings will be generated with only 50 m input swings. 6

7 river evice o = 50 o = 50 eceiver evice TT TT = CC 2.0 Figure 3. Typical Termination for Output river and evice Evaluation (See Application Note AN8020/ Termination of EC ogic evices.) OEING INFOMATION evice Package Shipping MC10E137FN PCC Units / ail MC10E137FNG PCC 28 (Pb Free) 37 Units / ail MC10E137FN2 PCC / Tape & eel MC10E137FN2G PCC 28 (Pb Free) 500 / Tape & eel MC100E137FN PCC Units / ail MC100E137FNG PCC 28 (Pb Free) 37 Units / ail MC100E137FN2 PCC / Tape & eel MC100E137FN2G PCC 28 (Pb Free) 500 / Tape & eel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and eel Packaging Specifications Brochure, B8011/. esource eference of Application Notes AN1405/ EC Clock istribution Techniques AN1406/ esigning with PEC (EC at +5.0 ) AN1503/ ECinPS I/O SPiCE Modeling Kit AN1504/ Metastability and the ECinPS Family AN1568/ Interfacing Between S and EC AN1672/ The EC Translator Guide AN8001/ Odd Number Counters esign AN8002/ Marking and ate Codes AN8020/ Termination of EC ogic evices AN8066/ Interfacing with ECinPS AN8090/ AC s of EC evices 7

8 PACKAGE IMENSIONS PCC 28 FN SUFFIX PASTIC PCC PACKAGE CASE ISSUE E N Y BK B (0.180) M T M S N S U (0.180) M T M S N S M 28 1 W X IEW G (0.250) S T M S N S A (0.180) M T M S N S (0.180) M T M S N S (0.180) M T M S N S C E K1 G G1 J IEW S (0.100) T SEATING PANE K F (0.180) M T M S N S (0.250) S T M S N S IEW S NOTES: 1. ATUMS, M, AN N ETEMINE WEE TOP OF EA SOUE EXITS PASTIC BOY AT MO PATING INE. 2. IMENSION G1, TUE POSITION TO BE MEASUE AT ATUM T, SEATING PANE. 3. IMENSIONS AN U O NOT INCUE MO FAS. AOWABE MO FAS IS (0.250) PE SIE. 4. IMENSIONING AN TOEANCING PE ANSI Y14.5M, CONTOING IMENSION: INC. 6. TE PACKAGE TOP MAY BE SMAE TAN TE PACKAGE BOTTOM BY UP TO (0.300). IMENSIONS AN U AE ETEMINE AT TE OUTEMOST EXTEMES OF TE PASTIC BOY EXCUSIE OF MO FAS, TIE BA BUS, GATE BUS AN INTEEA FAS, BUT INCUING ANY MISMATC BETWEEN TE TOP AN BOTTOM OF TE PASTIC BOY. 7. IMENSION OES NOT INCUE AMBA POTUSION O INTUSION. TE AMBA POTUSION(S) SA NOT CAUSE TE IMENSION TO BE GEATE TAN (0.940). TE AMBA INTUSION(S) SA NOT CAUSE TE IMENSION TO BE SMAE TAN (0.635). INCES MIIMETES IM MIN MAX MIN MAX A B C E F G BSC 1.27 BSC J K U W X Y G K

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