NVTFS5116PL. Power MOSFET. 60 V, 14 A, 52 m, Single P Channel
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1 Power MOSFET 6 V, 4 A, 52 m, Single P Channel Features Small Footprint (3.3 x 3.3 mm) for Compact esign Low R S(on) to Minimize Conduction Losses Low Capacitance to Minimize river Losses NVTFS56PLWF Wettable Flanks Product AEC Q Qualified and PPAP Capable These evices are Pb Free and are RoHS Compliant MAXIMUM RATINGS ( unless otherwise noted) Parameter Symbol Value Unit rain to Source Voltage V SS 6 V Gate to Source Voltage V GS ±2 V Continuous rain Current R J mb (Notes, 2, 3, 4) Steady Power issipation State R J mb (Notes, 2, 3) Continuous rain Current R JA (Notes & 3, 4) Steady Power issipation State R JA (Notes, 3) T mb = 25 C I 4 A T mb = C T mb = 25 C P 2 W T mb = C T A = 25 C I 6 A T A = C 4 T A = 25 C P 3.2 W T A = C.6 Pulsed rain Current T A = 25 C, t p = s I M 26 A Operating Junction and Storage Temperature T J, T stg 55 to +75 Source Current (Body iode) I S 7 A Single Pulse rain to Source Avalanche Energy (, V = 5 V, V GS = V, I L(pk) = 3 A, L =. mh, R G = 25 ) Lead Temperature for Soldering Purposes (/8 from case for s) C E AS 45 mj T L 26 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RESISTANCE MAXIMUM RATINGS (Note ) Parameter Symbol Value Unit Junction to Mounting Board (top) Steady State (Note 2 and 3) R J mb 7.2 C/W V (BR)SS R S(on) MAX I MAX 6 V G (4) WFN8 ( 8FL) CASE 5AB XXXX A Y WW 52 V V P Channel MOSFET (5 8) S (,2,3) 4 A MARKING IAGRAM S S S G XXXX AYWW = Specific evice Code = Assembly Location = Year = Work Week = Pb Free Package (Note: Microdot may be in either location) ORERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. Junction to Ambient Steady State (Note 3) R JA 47. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Psi ( ) is used as required per JES5 2 for packages in which substantially less than % of the heat flows to single case surface. 3. Surface mounted on FR4 board using a 65 mm 2, 2 oz. Cu pad. 4. Continuous C current rating. Maximum current for pulses as long as second is higher but is dependent on pulse duration and duty cycle. Semiconductor Components Industries, LLC, 24 June, 24 Rev. 3 Publication Order Number: NVTFS56PL/
2 ELECTRICAL CHARACTERISTICS ( unless otherwise noted) Parameter Symbol Test Condition Min Typ Max Unit OFF CHARACTERISTICS rain to Source Breakdown Voltage V (BR)SS V GS = V, I = 25 A 6 V Zero Gate Voltage rain Current I SS VGS = V, V S = 6 V. A T J = 25 C Gate to Source Leakage Current I GSS V S = V, V GS = 2 V na ON CHARACTERISTICS (Note 5) Gate Threshold Voltage V GS(TH) V GS = V S, I = 25 A 3 V rain to Source On Resistance R S(on) V GS = V, m V GS = 4.5 V, 5 72 Forward Transconductance g FS V S = 5 V, I = 5 A S CHARGES AN CAPACITANCES Input Capacitance C iss V GS = V, f =. MHz, 258 pf Output Capacitance C oss V S = 25 V 27 Reverse Transfer Capacitance C rss 84 Total Gate Charge Q G(TOT) 4 nc Threshold Gate Charge Q G(TH) V GS = 4.5 V, V S = 48 V, nc Gate to Source Charge Q GS 4 Gate to rain Charge Q G 8 Total Gate Charge Q G(TOT) V GS = V, V S = 48 V, 25 nc SWITCHING CHARACTERISTICS (Note 6) Turn On elay Time t d(on) 4 ns Rise Time t r V GS = 4.5 V, V S = 48 V, 68 Turn Off elay Time t d(off) 24 Fall Time t f 36 RAIN SOURCE IOE CHARACTERISTICS Forward iode Voltage V S V GS = V, I S = 7 A Reverse Recovery Time t RR.79.2 V T J = 25 C.64 Charge Time t a V GS = V, di S /dt = A/ s, 6 ischarge Time t b I S = 7 A 5 2 ns Reverse Recovery Charge Q RR 24 nc 5. Pulse Test: Pulse Width 3 s, uty Cycle 2%. 6. Switching characteristics are independent of operating junction temperatures. 2
3 TYPICAL CHARACTERISTICS 5 V GS = 7 V 4 V S V I, RAIN CURRENT (A) R S(on), RAIN TO SOURCE RESISTANCE ( ) V 5. V 4.6 V 4.3 V 4 V 3.7 V 3.4 V 3. V 2.8 V V S, RAIN TO SOURCE VOLTAGE (V) Figure. On Region Characteristics V GS, GATE TO SOURCE VOLTAGE (V) Figure 3. On Resistance vs. Gate to Source Voltage I, RAIN CURRENT (A) R S(on), RAIN TO SOURCE RESISTANCE ( ) T J = 25 C T J = 55 C V GS, GATE TO SOURCE VOLTAGE (V) Figure 2. Transfer Characteristics V GS = 4.5 V V GS = V I, RAIN CURRENT (A) Figure 4. On Resistance vs. rain Current and Gate Voltage R S(on), RAIN TO SOURCE RESISTANCE (NORMALIZE) V GS = V I SS, LEAKAGE (na) V GS = V T J = 5 C T J = 25 C T J, JUNCTION TEMPERATURE ( C) Figure 5. On Resistance Variation with Temperature V S, RAIN TO SOURCE VOLTAGE (V) Figure 6. rain to Source Leakage Current vs. Voltage 3
4 TYPICAL CHARACTERISTICS C, CAPACITANCE (pf) C iss V GS = V V S, RAIN TO SOURCE VOLTAGE (V) Figure 7. Capacitance Variation V GS, GATE TO SOURCE VOLTAGE (V) 4 2 V S = 48 V 2 C oss C rss Q gs Q gd Q T Q g, TOTAL GATE CHARGE (nc) Figure 8. Gate to Source Voltage vs. Total Charge t, TIME (ns) V = 48 V V GS = 4.5 V t d(off) t d(on) t f t r I S, SOURCE CURRENT (A) V GS = V. R G, GATE RESISTANCE ( ) Figure 9. Resistive Switching Time Variation vs. Gate Resistance V S, SOURCE TO RAIN VOLTAGE (V) Figure. iode Forward Voltage vs. Current I, RAIN CURRENT (A) V GS = V Single Pulse T C = 25 C s s ms ms R S(on) Limit Thermal Limit dc Package Limit.. V S, RAIN TO SOURCE VOLTAGE (V) Figure. Maximum Rated Forward Biased Safe Operating Area E AS, SINGLE PULSE RAIN TO SOURCE AVALANCHE ENERGY (mj) I = 3 A T J, STARTING JUNCTION TEMPERATURE ( C) Figure 2. Maximum Avalanche Energy vs. Starting Junction Temperature 4
5 TYPICAL CHARACTERISTICS R JA(t) ( C/W). uty Cycle = Single Pulse PULSE TIME (sec) Figure 3. Thermal Response EVICE ORERING INFORMATION evice Marking Package Shipping NVTFS56PLTAG 56 WFN8 5 / Tape & Reel NVTFS56PLWFTAG 6LW WFN8 NVTFS56PLTWG 56 WFN8 NVTFS56PLWFTWG 6LW WFN8 5 / Tape & Reel 5 / Tape & Reel 5 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BR8/. 5
6 PACKAGE IMENSIONS WFN8 3.3x3.3,.65P CASE 5AB ISSUE. C. C 8X b. C A B.5 C 4X L 2X.2 C A B 2X E E c TOP VIEW A SIE VIEW ETAIL A e/2 4 K.2 C 6X e ETAIL A 4X A C SEATING PLANE NOTES:. IMENSIONING AN TOLERANCING PER ASME Y4.5M, CONTROLLING IMENSION: MILLIMETERS. 3. IMENSION AN E O NOT INCLUE MOL FLASH PROTRUSIONS OR GATE BURRS. PACKAGE OUTLINE MILLIMETERS IM MIN NOM MAX A A..5 b c BSC E E BSC E e.65 BSC G.3.4 K.65.8 L.3.43 L.6.3 M SOLERING FOOTPRINT* 8X.42 MIN BSC BSC E BSC PITCH INCHES NOM 4X.66 MAX E2 E3 M G BOTTOM VIEW L IMENSION: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box 563, enver, Colorado 827 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NVTFS56PL/
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