NB6L V / 3.3V Differential 2 X 2 Crosspoint Switch with LVPECL Outputs. Multi-Level Inputs w/ Internal Termination
|
|
- Kenneth Roberts
- 5 years ago
- Views:
Transcription
1 .5V / 3.3V ifferential X Crosspoint Switch with LVPECL Outputs Multi-Level Inputs w/ Internal Termination escription The NB6L7 is a clock or data high-bandwidth fully differential x Crosspoint Switch with internal source termination and LVPECL output structure, optimized for low skew and minimal jitter. The differential inputs incorporate internal termination resistors and will accept LVPECL, CML, LVS, LVCMOS, or LVTTL logic levels. The SELECT inputs are single-ended and can be driven with LVCMOS/LVTTL. The differential LVPECL outputs provide 800 mv output swings when externally terminated with a resistor to.0 V. The device is offered in a small 3 mm x 3 mm 16-pin QFN package. The NB6L7 is a member of the ECLinPS MAX family of high performance clock and data management products. Features Input Clock Frequency > 3.0GHz Input ata Rate > 3 Gb/s 45 ps Typical Propagation elay 100 ps Typical Rise and Fall Times 0.5 ps maximum RMS Clock Jitter LVPECL, CML or LVS Input Compatible ifferential LVPECL Outputs, 800 mv Amplitude, Typical Operating Range: =.375 V to 3.63 V with GN = 0 V Internal Input Termination Provided Functionally Compatible with Existing.5 V/3.3 V LVEL, LVEP, EP, and SG evices -40 C to +85 C Ambient Operating Temperature These are Pb-Free evices 1 QFN-16 MN SUFFIX CASE 485G MARKING IAGRAM* A = Assembly Location L = Wafer Lot Y = Year W = Work Week = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AN800/. ORERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet NB6L 7 ALYW Semiconductor Components Industries, LLC, 008 April, Rev. 4 1 Publication Order Number: NB6L7/
2 VT VT1 SEL0 SEL k + 75 k GN Q0 Q0 + Q1 Q1 Figure 1. Logic/Block iagram
3 GN Q0 Q Exposed Pad (EP) Table 1. INPUT/OUTPUT SELECT TRUTH TABLE SEL0* SEL1* Q0 Q1 SEL0 1 1 L L 0 0 H L VT0 3 4 NB6L Q1 Q1 GN L H 0 1 H H 1 1 *efaults HIGH when left open VT1 1 1 SEL1 Figure. Pin Configuration (Top View) Table. PIN ESCRIPTION Pin Name I/O escription 1 SEL0 LVTTL, LVCMOS Input 0 LVPECL, CML, LVS, LVTTL, LVCMOS, Input 3 0 LVPECL, CML, LVS, LVTTL, LVCMOS, Input Select Logic Input control that selects 0 or 1 to output Q0. See Table 1, Select Input Function Table. Pin defaults HIGH when left open Noninverted ifferential Input. Note 1. Inverted ifferential Input. Note 1. 4 VT0 - Internal Termination Pin. Note 1. 5 VT1 - Internal termination pin. Note LVPECL, CML, LVS, LVTTL, LVCMOS, Input 7 1 LVPECL, CML, LVS, LVTTL, LVCMOS, Input 8 SEL1 LVTTL,LVCMOS Input Noninverted ifferential Input. Note 1. Inverted ifferential Input. Note 1. Select Logic Input control that selects 0 or 1 to output Q1. See Table 1, Select Input Function Table. Pin defaults HIGH when left open 9 GN - Negative Supply Voltage 10 Q1 LVPECL Output Inverted ifferential Output. Typically Terminated with Resistor to -.0 V. 11 Q1 LVPECL Output Noninverted ifferential Output. Typically Terminated with Resistor to -.0 V. 1 - Positive Supply Voltage 13 - Positive Supply Voltage 14 Q0 LVPECL Output Inverted ifferential Reset Input. Typically Terminated with Resistor to -.0 V. 15 Q0 LVPECL Output Noninverted ifferential Reset Input. Typically Terminated with Resistor to -.0 V. 16 GN - Negative Supply Voltage - EP - The Exposed Pad (EP) on the QFN-16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat-sinking conduit. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to GN on the PC board. 1. In the differential configuration when the input termination pin (VTn, VTn) are connected to a common termination voltage or left open, and if no signal is applied on n/n input, then the device will be susceptible to self-oscillation.. All and GN pins must be externally connected to a power supply for proper operation. 3
4 Table 3. ATTRIBUTES ES Protection Characteristics Human Body Model Machine Model Value > kv > 00 V Moisture Sensitivity 16-QFN Level 1 Flammability Rating Oxygen Index: 8 to 34 UL in Transistor Count Meets or exceeds JEEC Spec EIA/JES78 IC Latchup Test For additional information, see Application Note AN8003/. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition Rating Unit Positive Power Supply GN = 0 V 4.0 V V IO Positive Input/Output Voltage GN = 0 V -0.5 V IO V V INPP ifferential Input Voltage - - GN V I IN Input Current Through R T ( Resistor) Static Surge ma ma I OUT Output Current (LVPECL Output) Continuous Surge T A Operating Temperature Range QFN to +85 C T stg Storage Temperature Range -65 to +150 C JA Thermal Resistance (Junction-to-Ambient) (Note 3) 0 lfpm 500 lfpm QFN-16 QFN-16 JC Thermal Resistance (Junction-to-Case) (Note 3) QFN-16 4 C/W T sol Wave Solder Pb-Free 65 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEEC standard multilayer board - SP ( signal, power) with 8 filled thermal vias under exposed pad ma ma C/W C/W 4
5 Table 5. C CHARACTERISTICS, Multi-Level Inputs =.375 V to 3.63 V, GN = 0 V, TA = -40 C to +85 C Symbol Characteristic Min Typ Max Unit POWER SUPPLY CURRENT I CC Power Supply Current (Inputs and Outputs Open) ma LVPECL OUTPUTS (Notes 4 and 5) V OH Output HIGH Voltage mv = 3.3 V =.5 V V OL Output LOW Voltage = 3.3 V =.5 V IFFERENTIAL INPUT RIVEN SINGLE-ENE (see Figures 4 and 5) (Note 6) V th Input Threshold Reference Voltage Range (Note 7) mv V IH Single-ended Input HIGH Voltage V th mv V IL Single-ended Input LOW Voltage GN V th mv V ISE Single-ended Input Voltage Amplitude (V IH - V IL ) GN mv IFFERENTIAL INPUTS RIVEN IFFERENTIALLY (see Figures 7 and 9) V IH ifferential Input HIGH Voltage 1050 mv V IL ifferential Input LOW Voltage GN mv V I ifferential Input Voltage (n, n) (V IH - V IL ) GN mv V CMR Input Common Mode Range (ifferential Configuration) (Note 9) mv I IH Input HIGH Current n/n, (VTn/VTn Open) A I IL Input LOW Current n/n, (VTn/VTn Open) A SINGLE-ENE LVCMOS/LVTTL CONTROL INPUTS V IH Single-ended Input HIGH Voltage 000 mv V IL Single-ended Input LOW Voltage GN 800 mv I IH Input HIGH Current A I IL Input LOW Current A TERMINATION RESISTORS R TIN Internal Input Termination Resistor NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. LVPECL outputs loaded with to -.0 V for proper operation. 5. Input and output parameters vary 1:1 with. 6. V th, V IH, V IL,, and V ISE parameters must be complied with simultaneously. 7. V th is applied to the complementary input when operating in single-ended mode. 8. V IH, V IL, V I and V CMR parameters must be complied with simultaneously. 9. V CMR minimum varies 1:1 with GN, V CMR max varies 1:1 with. The V CMR range is referenced to the most positive side of the differential input signal. mv 5
6 Table 6. AC CHARACTERISTICS =.375 V to 3.63 V, V EE = 0 V, or = 0 V, V EE = V to V, T A = -40 C to +85 C; (Note 10) Symbol Characteristic Min Typ Max Unit V OUTPP Output Voltage Amplitude (@ V INPPmin ) f in 1.5 GHz (Note 14) (See Figure 16) f in.5 GHz f in 3.0 GHz t PLH, Propagation elay (@0.5GHz) n to Qn t PHL SELn to Qn t SKEW uty Cycle Skew (Note 11) Within evice Skew evice to evice Skew (Note 1) t C Output Clock uty Cycle f in 3.0 GHz (Reference uty Cycle = 50%) t JITTER RMS Random Clock Jitter (Note 13) f in =.5 GHz f in = 3.0 GHz ata ependent Jitter f ATA =.5 Gb/s f ATA = 3.0 Gb/s V INPP Input Voltage Swing/Sensitivity (ifferential Configuration) (Note 14) mv ps % GN mv ps ps t r,t f Output Rise/Fall 0.5 GHz (0% - 80%) Q, Q ps NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10.Measured by forcing V INPP (minimum) from a 50% duty cycle clock source. All loading with an external R L = to.0 V. Input edge rates 40 ps (0% - 80%). 11. uty cycle skew is measured between differential outputs using the deviations of the sum of T pw - and T pw 0.5 GHz. 1. evice to device skew is measured between outputs under identical 0.5 GHz. 13. Additive RMS jitter with 50% duty cycle clock signal. 14. Input and output voltage swing is a single-ended measurement operating in differential mode. 6
7 VT R C R C I VT Figure 3. Input Structure V IH V th V IL V thmax V th V IHmax V ILmax V IH V th V IL V thmin V IHmin V th Figure 4. ifferential Input riven Single-Ended GN Figure 5. V th iagram V ILmin V I = V IH() - V IL() V IH V IL Figure 6. ifferential Inputs riven ifferentially Figure 7. ifferential Inputs riven ifferentially V IH(MAX) V IL V INPP = V IH () - V IL () V CMR V IH V I = V IH - V IL Q V IL Q V OUTPP = V OH (Q) - V OL (Q) V IH(MIN) t P GN V IL(MIN) t P Figure 8. V CMR iagram Figure 9. AC Reference Measurement 7
8 Z O = NB6L7 Z O = NB6L7 LVPECL river VT = - V Z O = LVS river V T = Open Z O = GN GN GN GN Figure 10. LVPECL Interface Figure 11. LVS Interface Z O = NB6L7 CML river V T = Z O = GN GN Figure 1. Standard Load CML Interface Z O = NB6L7 Z O = NB6L7 ifferential river VT = V REFAC * Z O = Single-Ended river VT = V REFAC * (Open) GN Figure 13. Capacitor-Coupled ifferential Interface (VT Connected to V REFAC ) GN GN Figure 14. Capacitor-Coupled Single-Ended Interface (VT Connected to V REFAC ) GN *V REFAC bypassed to ground with a 0.01 F capacitor 8
9 river evice Q Q Z o = Z o = Receiver evice V TT V TT = -.0 V Figure 15. Typical Termination for Output river and evice Evaluation (See Application Note AN800/ - Termination of ECL Logic evices.) OUTPUT VOLTAGE AMPLITUE (mv) OUTPUT FREQUENCY (GHz) Figure 16. Output Voltage Amplitude (V OUTPP ) versus Output Frequency at Ambient Temperature (Typical) Total Jitter = 5 ps evice Jitter = 1 ps Input Jitter = 13 ps Figure 17. Typical Output Wave Form - ata Signal PRBS 3-1 Room Temperature, 400 mv Input Amplitude, =.5 V,.488 Gb/s (X-scale = 80 ps/iv; y-scale = 100 mv/iv) 9
10 Total Jitter = 8 ps evice Jitter = 15 ps Input Jitter = 13 ps Figure 18. Typical Output Wave Form - ata Signal PRBS 3-1 Room Temperature, 75 mv Input Amplitude, 3 Gb/s (X-scale = 80 ps/iv; y-scale = 100 mv/iv) ORERING INFORMATION NB6L7MNG NB6L7MNRG evice Package Shipping QFN-16 (Pb-free) QFN-16 (Pb-free) 13 Units / Rail 3000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BR8011/. 10
11 PACKAGE IMENSIONS 16 X PIN 1 LOCATION 16X L NOTE C 0.10 C 0.08 C 16X K 0.15 C 4 ÇÇ 1 TOP VIEW SIE VIEW e 5 8 (A3) 9 A B E A1 e 1 E A C EXPOSE PA 16 PIN QFN MN SUFFIX CASE 485G-01 ISSUE C SEATING PLANE NOTES: 1. IMENSIONING AN TOLERANCING PER ASME Y14.5M, CONTROLLING IMENSION: MILLIMETERS. 3. IMENSION b APPLIES TO PLATE TERMINAL AN IS MEASURE BETWEEN 0.5 AN 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSE PA AS WELL AS THE TERMINALS. 5. L max CONITION CAN NOT VIOLATE 0. MM MINIMUM SPACING BETWEEN LEA TIP AN FLAG MILLIMETERS IM MIN MAX A A A3 0.0 REF b BSC E 3.00 BSC E e 0.50 BSC K 0.18 TYP L SOLERING FOOTPRINT* EXPOSE PA 0.10 C 0.05 C 16X b A B NOTE BOTTOM VIEW SCALE 10: mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. ECLinPS MAX is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box 5163, enver, Colorado 8017 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center -9-1 Kamimeguro, Meguro-ku, Tokyo, Japan Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. NB6L7/
NB7V52M. 1.8V / 2.5V Differential D Flip-Flop w/ Reset and CML Outputs. Multi Level Inputs w/ Internal Termination
1.8V / 2.5V ifferential Flip-Flop w/ Reset and CML Outputs Multi Level Inputs w/ Internal Termination escription The is a 10 GHz differential flip flop with a differential asynchronous Reset. The differential
More informationMC100LVELT20 Product Preview 3.3VНLVTTL/LVCMOS to Differential LVPECL Translator Description The MC100LVELT20 is a 3.3 V TTL/CMOS to differential PECL
Product Preview 3.3VНLVTTL/LVCMOS to ifferential LVPECL Translator escription The is a 3.3 V TTL/CMOS to differential PECL translator. Because PECL (Positive ECL) levels are used, only + 3.3 V and ground
More informationNB7L32M. 2.5V/3.3V, 14GHz 2 Clock Divider w/cml Output and Internal Termination
2.5V/3.3V, 14GHz 2 Clock ivider w/cml Output and Internal Termination escription The NB7L32M is an integrated 2 divider with differential clock inputs and asynchronous reset. ifferential clock inputs incorporate
More informationNB4N855S 3.3 V, 1.5 Gb/s Dual AnyLevel to LVDS Receiver/Driver/Buffer/ Translator
3.3 V,.5 Gb/s ual AnyLevel to LVS Receiver/river/Buffer/ Translator escription NB4N55S is a clock or data Receiver/river/Buffer/Translator capable of translating AnyLevel input signal (LVPECL, CML, HSTL,
More informationNB6N11S. 3.3 V 1:2 AnyLevel Input to LVDS Fanout Buffer / Translator
NB6NS 3.3 V :2 AnyLevel Input to LVS Fanout Buffer / Translator escription The NB6NS is a differential :2 Clock or ata Receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVS.
More informationMC10ELT22, MC100ELT22. 5VНDual TTL to Differential PECL Translator
5VНual TTL to ifferential PECL Translator The MC0ELT/00ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and ground are required. The small outline
More informationNBXDBA V, MHz / MHz LVPECL Clock Oscillator
. V, 106.25 MHz / 212.5 MHz LVPECL Clock Oscillator The NBXBA012 dual frequency crystal oscillator (XO) is designed to meet today s requirements for. V LVPECL clock generation applications. The device
More informationNBXDBA V, 75 MHz / 150 MHz LVPECL Clock Oscillator
. V, 75 MHz / 150 MHz LVPECL Clock Oscillator The NBXBA009 dual frequency crystal oscillator (XO) is designed to meet today s requirements for. V LVPECL clock generation applications. The device uses a
More informationNB3N106K. 3.3V Differential 1:6 Fanout Clock Driver with HCSL Outputs
3.3V Differential 1:6 Fanout Clock Driver with HCSL Outputs Description The is a differential 1:6 Clock fanout buffer with High speed Current Steering Logic (HCSL) outputs optimized for ultra low propagation
More informationMC100EP16VS. 3.3V / 5V ECL Differential Receiver/Driver with Variable Output Swing
3.3V / 5V ECL ifferential Receiver/river with Variable Output Swing escription The MC00EP6VS is a differential receiver with variable output amplitude. The device is functionally equivalent to the 00EP6
More informationNB7L14M. MARKING DIAGRAM* Features
2.5V/3.3V Differential :4 Clock/Data Fanout Buffer/ Translator with CML Outputs and Internal Termination Description The NB7L4M is a differential to 4 clock/data distribution chip with internal source
More informationNBXDBA019, NBXHBA019, NBXSBA V, 125 MHz / 250 MHz LVPECL Clock Oscillator
NBXBA019, NBXHBA019, NBXSBA019. V, 15 MHz / 50 MHz LVPECL Clock Oscillator The single and dual frequency crystal oscillator (XO) is designed to meet today s requirements for. V LVPECL clock generation
More informationNBXDBA V, 62.5 MHz / 125 MHz LVPECL Clock Oscillator
. V, 62.5 MHz / 125 MHz LVPECL Clock Oscillator The NBXBA014 dual frequency crystal oscillator (XO) is designed to meet today s requirements for. V LVPECL clock generation applications. The device uses
More informationNB6L V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator
.5 V/3.3 V Multilevel Input to ifferential LVPECL/LVNECL : Clock or ata Fanout Buffer/Translator The NB6L is an enhanced differential : clock or data fanout buffer/translator. The device has the same pinout
More informationNBXSBA /3.3 V, MHz LVPECL Clock Oscillator
2.5/. V, 5. MHz LVPECL Clock Oscillator The NBXSBA051, single frequency, crystal oscillator (XO) is designed to meet today s requirements for 2.5/. V LVPECL clock generation applications. The device uses
More informationNBXHGA /3.3 V, MHz LVPECL Clock Oscillator
2.5/. V, 125.00 MHz LVPECL Clock Oscillator The NBXHGA019, single frequency, crystal oscillator (XO) is designed to meet today s requirements for 2.5/. V LVPECL clock generation applications. The device
More informationNBSG16M. 2.5 V/3.3 V Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer
2.5 V/3.3 V Multilevel Input to CML Clock/ata Receiver/river/Translator Buffer escription The NBSG6M is a differential current mode logic (CML) receiver/driver/translator buffer. The device is functionally
More informationNBSG53ABAR2. 2.5V/3.3VНSiGe Selectable Differential Clock and Data D Flip Flop/Clock Divider with Reset and OLS*
NBSG3A.V/3.3VНSiGe Selectable Differential Clock and Data D Flip Flop/Clock Divider with Reset and OLS* The NBSG3A is a multi-function differential D flip-flop (DFF) or fixed divide by two (DIV/) clock
More informationNB3N108K. 3.3V Differential 1:8 Fanout Clock Data Driver with HCSL Outputs
3.3V Differential 1:8 Fanout Clock Data with HCSL Outputs Description The is a differential 1:8 Clock fanout buffer with High speed Current Steering Logic (HCSL) outputs optimized for ultra low propagation
More informationNBXSBA024, NBXSBB024, NBXMBB V / 3.3 V, MHz LVPECL Clock Oscillator
NBXSBA0, NBXSBB0, NBXMBB0.5 V /. V, 6.08 MHz LVPECL Clock Oscillator The single frequency, crystal oscillator (XO) is designed to meet today s requirements for.5 V /. V LVPECL clock generation applications.
More informationNBVSPA V, MHz LVDS Voltage-Controlled Clock Oscillator (VCXO) PureEdge Product Series
2.5 V, 212.00 MHz LVS Voltage-Controlled Clock Oscillator (VCXO) PureEdge Product Series The NBVSPA01 voltage controlled crystal oscillator (VCXO) is designed to meet today s requirements for 2.5 V LVS
More informationMC10EP142, MC100EP V / 5 VНECL 9 Bit Shift Register
MCEP42, MCEP42 3.3 V / 5 VНECL 9 Bit Shift Register The MCEP/EP42 is a 9 bit shift register, designed with byte-parity applications in mind. The MC/EP42 is capable of performing serial/parallel data into
More informationNBXDPA V / 3.3 V, MHz / MHz LVDS Clock Oscillator
2.5 V / 3.3 V, 156.25 MHz / 312.5 MHz LVS Clock Oscillator The NBXPA017 dual frequency crystal oscillator (XO) is designed to meet today s requirements for 2.5 V and 3.3 V LVS clock generation applications.
More informationMC10EL16, MC100EL V ECL Differential Receiver
MC0EL6, MC00EL6 5.0 V ECL ifferential Receiver The MC0EL/00EL6 is a differential receiver. The device is functionally equivalent to the E6 device with higher performance capabilities. With output transition
More informationNBXDPA V / 3.3 V, 125 MHz / 250 MHz LVDS Clock Oscillator
2.5 V / 3.3 V, 125 MHz / 250 MHz LVS Clock Oscillator The NBXPA019 dual frequency crystal oscillator (XO) is designed to meet today s requirements for 2.5 V and 3.3 V LVS clock generation applications.
More informationMC10EP57, MC100EP V / 5V ECL 4:1 Differential Multiplexer
3.3V / 5V ECL 4:1 Differential Multiplexer Description The MC10/100EP57 is a fully differential 4:1 multiplexer. By leaving the SEL1 line open (pulled LOW via the input pulldown resistors) the device can
More informationNB4N840M. 3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Internal Termination
3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with Output and Internal Termination Description The NB4N84M is a high bandwidth fully differential dual 2 x 2 crosspoint switch with inputs/outputs
More informationNB4L V/3.3V Differential 2x10 Crosspoint Clock Driver with SDI Programmable Output Selects
2.5V/3.3V Differential 2x10 Crosspoint Clock Driver with SDI Programmable Output Selects The is a Clock input crosspoint fanout distribution device selecting between one of two input clocks on each of
More informationNB3N502/D. 14 MHz to 190 MHz PLL Clock Multiplier
4 MHz to 90 MHz PLL Clock Multiplier Description The NB3N502 is a clock multiplier device that generates a low jitter, TTL/CMOS level output clock which is a precise multiple of the external input reference
More informationNB7L1008M. 2.5V / 3.3V 1:8 CML Fanout. Multi Level Inputs w/ Internal Termination
2.5V / 3.3V 1:8 CML Fanout Multi Level Inputs w/ Internal Termination Description The is a high performance differential 1:8 Clock/Data fanout buffer. The produces eight identical output copies of Clock
More informationNB7V72M. 1.8V / 2.5V Differential 2 x 2 Crosspoint Switch with CML Outputs Clock/Data Buffer/Translator. Multi Level Inputs w/ Internal Termination
.8V / 2.5V Differential 2 x 2 Crosspoint Switch with CML Outputs Clock/Data Buffer/Translator Multi Level Inputs w/ Internal Termination Description The is a high bandwidth, low voltage, fully differential
More informationMC10EP08, MC100EP V / 5V ECL 2-Input Differential XOR/XNOR
MC0EP0, MC00EP0 3.3V / 5V ECL 2-Input ifferential XOR/XNOR escription The MC0/00EP0 is a differential XOR/XNOR gate. The EP0 is ideal for applications requiring the fastest AC performance available. The
More informationNB7L111M. 2.5V/3.3V, 6.125Gb/s 2:1:10 Differential Clock/Data Driver with CML Output
2.5V/3.3V, 6.1Gb/s 2:1:10 Differential Clock/Data Driver with CML Output Description The NB7L111M is a low skew 2:1:10 differential clock/data driver, designed with clock/data distribution in mind. It
More informationNB4N121K. 3.3V Differential 1:21 Differential Fanout Clock Driver with HCSL level Output
3.3V ifferential 1:21 ifferential Fanout lock river with HSL level Output escription The is a lock differential input fanout distribution 1 to 21 HSL level differential outputs, optimized for ultra low
More informationLOGIC DIAGRAM AND PINOUT ASSIGNMENT V CC TTL PECL 3. MARKING DIAGRAMS* ORDERING INFORMATION PIN DESCRIPTION HLT20 ALYW KLT20 ALYW
The MC0ELT/00ELT20 is a TTL to differential PECL translator. Because PECL (Positive ECL) levels are used, only +5 V and ground are required. The small outline -lead package and the single gate of the ELT20
More informationNB6N14S 3.3 V 1:4 AnyLevel Differential Input to LVDS Fanout Buffer/Translator
3.3 V :4 AnyLevel Differential Input to LVDS Fanout Buffer/Translator The is a differential :4 Clock or Data Receiver and will accept AnyLevel differential input signals: LVPECL, CML or LVDS. These signals
More informationNB6L14S. 2.5 V 1:4 AnyLevel Differential Input to LVDS Fanout Buffer/Translator
2.5 V :4 AnyLevel Differential Input to LVDS Fanout Buffer/Translator The is a differential :4 Clock or Data Receiver and will accept AnyLevel differential input signals: LVPECL, CML, LVDS, or HSCL. These
More informationNB6L295M 2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential CML Outputs
2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential CML Outputs Multi Level Inputs w/ Internal Termination The NB6L295M is a Dual Channel Programmable Delay Chip designed primarily
More informationNB4L V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer
2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer Description The NB4L6254 is a differential 2x2 clock switch and drives precisely aligned clock signals through its LVPECL fanout
More informationNB3N853531E. 3.3 V Xtal or LVTTL/LVCMOS Input 2:1 MUX to 1:4 LVPECL Fanout Buffer
3.3 V Xtal or LVTTL/LVCMOS Input 2:1 MUX to 1:4 LVPECL Fanout Buffer Description The NB3N853531E is a low skew 3.3 V supply 1:4 clock distribution fanout buffer. An input MUX selects either a Fundamental
More informationNB3N508S. 3.3V, 216 MHz PureEdge VCXO Clock Generator with M LVDS Output
3.3V, 216 MHz PureEdge VCXO Clock Generator with M LVDS Output Description The NB3N508S is a high precision, low phase noise Voltage Controlled Crystal Oscillator (VCXO) and phase lock loop (PLL) that
More informationNTJS3151P. Trench Power MOSFET. 12 V, 3.3 A, Single P Channel, ESD Protected SC 88
NTJS5P Trench Power MOSFET V,. A, Single P Channel, ES Protected SC 88 Features Leading Trench Technology for Low R S(ON) Extending Battery Life SC 88 Small Outline (x mm, SC7 Equivalent) Gate iodes for
More informationMC100EPT22/D. MARKING DIAGRAMS* ORDERING INFORMATION SO 8 D SUFFIX CASE 751 KPT22 ALYW TSSOP 8 DT SUFFIX CASE 948R KA22 ALYW
The MC00EPT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL (Positive ECL) levels are used only +3.3 V and ground are required. The small outline lead package and the single
More informationMC10EP51, MC100EP V / 5VНECL D Flip Flop with Reset and Differential Clock
3.3V / 5VНEC Flip Flop with Reset and ifferential Clock escription The MC0/00EP5 is a differential clock flip flop with reset. The device is functionally equivalent to the E5 and VE5 devices. The reset
More informationP3P85R01A. 3.3V, 75 MHz to 200 MHz LVCMOS TIMING SAFE Peak EMI Reduction Device
3.3V, 75 MHz to 200 MHz LVCMOS TIMING SAFE Peak EMI Reduction Device Functional Description P3P85R0A is a versatile, 3.3 V, LVCMOS, wide frequency range, TIMING SAFE Peak EMI reduction device. TIMING SAFE
More informationNCN Differential Channel 1:2 Mux/Demux Switch for PCI Express Gen3
4-Differential Channel 1:2 Mux/Demux Switch for PCI Express Gen3 The NCN3411 is a 4 Channel differential SPDT switch designed to route PCI Express Gen3 signals. When used in a PCI Express application,
More informationP2I2305NZ. 3.3V 1:5 Clock Buffer
3.3V :5 Clock Buffer Functional Description P2I2305NZ is a low cost high speed buffer designed to accept one clock input and distribute up to five clocks in mobile PC systems and desktop PC systems. The
More informationMC100EL29. 5VНECL Dual Differential Data and Clock D Flip Flop With Set and Reset
MCE29 5НEC ual ifferential ata and Clock Flip Flop With Set and Reset escription The MCE29 is a dual master slave flip flop. The device features fully differential ata and Clock inputs as well as outputs.
More informationNB7VQ1006M. 1.8 V / 2.5 V 10 Gbps Equalizer Receiver with 1:6 Differential CML Outputs. Multi-Level Inputs W / Internal Termination
.8 V / 2.5 V 0 Gbps Equalizer Receiver with :6 Differential CML Outputs Multi-Level Inputs W / Internal Termination Description The is a high performance differential :6 CML fanout buffer with a selectable
More informationMC10H352. Quad CMOS to PECL* Translator
Quad CMOS to PECL* Translator Description The MC10H352 is a quad translator for interfacing data between a CMOS logic section and the PECL section of digital systems when only a +5.0 Vdc power supply is
More informationNTMFS5C604NL. Power MOSFET. 60 V, 1.2 m, 276 A, Single N Channel
NTMFSC64NL Power MOSFET 6 V,. m, 76 A, Single N Channel Features Small Footprint (x6 mm) for Compact esign Low R S(on) to Minimize Conduction Losses Low Q G and Capacitance to Minimize river Losses These
More information7WB Bit Bus Switch. The 7WB3126 is an advanced high speed low power 2 bit bus switch in ultra small footprints.
2-Bit Bus Switch The WB326 is an advanced high speed low power 2 bit bus switch in ultra small footprints. Features High Speed: t PD = 0.25 ns (Max) @ V CC = 4.5 V 3 Switch Connection Between 2 Ports Power
More informationNB6L572M. 2.5V / 3.3V Differential 4:1 Mux to 1:2 CML Clock/Data Fanout / Translator. Multi Level Inputs w/ Internal Termination
2.5V / 3.3V Differential 4: Mux to :2 CML Clock/Data Fanout / Translator Multi Level Inputs w/ Internal Termination Description The is a high performance differential 4: Clock / Data input multiplexer
More informationNTR4170NT3G. Power MOSFET. 30 V, 3.1 A, Single N Channel, SOT 23
NTR47N Power MOSFET V,. A, Single N Channel, SOT Features Low R S(on) Low Gate Charge Low Threshold Voltage Halide Free This is a Pb Free evice Applications Power Converters for Portables Battery Management
More informationMARKING DIAGRAMS* ORDERING INFORMATION KPT23 ALYW SO 8 D SUFFIX CASE 751 TSSOP 8 DT SUFFIX CASE 948R KA23 ALYW
The MC00EPT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL (Positive ECL) levels are used, only +3.3 V and ground are required. The small outline -lead package and the dual gate design
More informationNTMFS4936NCT3G. NTMFS4936NC Power MOSFET 30 V, 79 A, Single N Channel, SO 8 FL
NTMFS4936N, NTMFS4936NC Power MOSFET 3 V, 79 A, Single N Channel, Features Low R S(on), Low Capacitance and Optimized Gate Charge to Minimize Conduction, river and Switching Losses Next Generation Enhanced
More informationLOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION
The SN74LS64 is a high speed 8-Bit Serial-In Parallel-Out Shift Register. Serial data is entered through a 2-Input AN gate synchronous with the LOW to HIGH transition of the clock. The device features
More informationNB2879A. Low Power, Reduced EMI Clock Synthesizer
Low Power, Reduced EMI Clock Synthesizer The NB2879A is a versatile spread spectrum frequency modulator designed specifically for a wide range of clock frequencies. The NB2879A reduces ElectroMagnetic
More informationMC100EP V 2:1:9 Differential HSTL/PECL/LVDS to HSTL Clock Driver with LVTTL Clock Select and Enable
3.3 2:: Differential HSTL/PECL/LDS to HSTL Clock Driver with LTTL Clock Select and Enable Description The MC00EP80 is a low skew 2:: differential clock driver, designed with clock distribution in mind,
More informationNBSG72A. 2.5 V/3.3 V SiGe Differential 2 x 2 Crosspoint Switch with Output Level Select
2.5 V/3.3 V SiGe Differential 2 x 2 Crosspoint Switch with Output Level Select The NBSG72A is a high-bandwidth fully differential 2 2 crosspoint switch with Output Level Select (OLS) capabilities. This
More informationNTHS2101P. Power MOSFET. 8.0 V, 7.5 A P Channel ChipFET
NTHSP Power MOSFET. V,. A P Channel ChipFET Features Offers an Ultra Low R S(on) Solution in the ChipFET Package Miniature ChipFET Package % Smaller Footprint than TSOP making it an Ideal evice for Applications
More informationNVTFS5124PL. Power MOSFET 60 V, 6 A, 260 m, Single P Channel
Power MOSFET V, A, m, Single P Channel Features Small Footprint (3.3 x 3.3 mm) for Compact esign Low R S(on) to Minimize Conduction Losses Low Q G and Capacitance to Minimize river Losses NVTFS5PLWF Wettable
More informationNVTFS5826NL. Power MOSFET 60 V, 24 m, 20 A, Single N Channel
Power MOSFET 6 V, 24 m, 2 A, Single N Channel Features Small Footprint (3.3 x 3.3 mm) for Compact esign Low R S(on) to Minimize Conduction Losses Low Capacitance to Minimize river Losses NVTFS5826NLWF
More informationP1P Portable Gaming Audio/Video Multimedia. MARKING DIAGRAM. Features
.8V, 4-PLL Low Power Clock Generator with Spread Spectrum Functional Description The PP4067 is a high precision frequency synthesizer designed to operate with a 27 MHz fundamental mode crystal. Device
More informationNB3V8312C. Ultra-Low Jitter, Low Skew 1:12 LVCMOS/LVTTL Fanout Buffer
Ultra-Low Jitter, Low Skew : LCMOS/LTTL Fanout Buffer The is a high performance, low skew LCMOS fanout buffer which can distribute ultra low jitter clocks from an LCMOS/LTTL input up to 50 MHz. The LCMOS
More informationNTMFS5H409NL. Power MOSFET. 40 V, 1.1 m, 270 A, Single N Channel
Power MOSFET 4 V,. m, 7 A, Single N Channel Features Small Footprint (5x6 mm) for Compact esign Low R S(on) to Minimize Conduction Losses Low Q G and Capacitance to Minimize river Losses These evices are
More informationNB7VQ58M. 1.8V / 2.5V / 3.3V Differential 2:1 Clock/Data Multiplexer / Translator with CML Outputs. w/ Selectable Input Equalizer
NB7V58M.8V / 2.5V / 3.3V Differential 2: Clock/Data Multiplexer / Translator with CML Outputs w/ Selectable Input Equalizer Multi Level Inputs w/ Internal Termination Description The NB7V58M is a high
More informationNTMFS4H01N Power MOSFET
NTMFS4HN Power MOSFET V, 334 A, Single N Channel, SO 8FL Features Optimized esign to Minimize Conduction and Switching Losses Optimized Package to Minimize Parasitic Inductances Optimized material for
More informationMC100EPT V LVTTL/LVCMOS to LVPECL Translator
MCEPT622 3.3V VTT/VCMOS to VPEC Translator Description The MCEPT622 is a 0 Bit VTT/VCMOS to VPEC translator. Because VPEC (Positive EC) levels are used only +3.3 V and ground are required. The device has
More informationMBRD835LT4G. SWITCHMODE Power Rectifier. DPAK Surface Mount Package SCHOTTKY BARRIER RECTIFIER 8.0 AMPERES, 35 VOLTS
MBRD8L Preferred Device SWITCHMODE Power Rectifier Surface Mount Package This SWITCHMODE power rectifier which uses the Schottky Barrier principle with a proprietary barrier metal, is designed for use
More informationNVTFS5116PL. Power MOSFET. 60 V, 14 A, 52 m, Single P Channel
Power MOSFET 6 V, 4 A, 52 m, Single P Channel Features Small Footprint (3.3 x 3.3 mm) for Compact esign Low R S(on) to Minimize Conduction Losses Low Capacitance to Minimize river Losses NVTFS56PLWF Wettable
More informationNCP304A. Voltage Detector Series
Voltage Detector Series The NCP0A is a second generation ultralow current voltage detector. This device is specifically designed for use as a reset controller in portable microprocessor based systems where
More informationPCS2I2309NZ. 3.3 V 1:9 Clock Buffer
. V 1:9 Clock Buffer Functional Description PCS2I209NZ is a low cost high speed buffer designed to accept one clock input and distribute up to nine clocks in mobile PC systems and desktop PC systems. The
More informationNSTB1005DXV5T1, NSTB1005DXV5T5. Dual Common Base Collector Bias Resistor Transistors
NSTB005DXV5T, NSTB005DXV5T5 Preferred Devices Dual Common Base Collector Bias Resistor Transistors NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The BRT (Bias Resistor
More informationNB7VQ572M. 1.8V / 2.5V /3.3V Differential 4:1 Mux w/input Equalizer to 1:2 CML Clock/Data Fanout / Translator
1.8V / 2.5V /3.3V Differential 4:1 Mux w/input Equalizer to 1:2 CML Clock/Data Fanout / Translator Multi Level Inputs w/ Internal Termination Description The is a high performance differential 4:1 Clock
More informationEMF5XV6T5G. Power Management, Dual Transistors. NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
Preferred Devices Power Management, Dual Transistors NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network Features Simplifies Circuit Design Reduces Board Space Reduces Component
More informationNLAS7222B, NLAS7222C. High-Speed USB 2.0 (480 Mbps) DPDT Switches
High-Speed USB 2.0 (480 Mbps) DPDT Switches ON Semiconductor s NLAS7222B and NLAS7222C are part of a series of analog switch circuits that are produced using the company s advanced sub micron CMOS technology,
More informationMC100EL30. 5VНECL Triple D Flip Flop with Set and Reset
MCE30 5VНEC Triple Flip Flop with et and Reset The MCE30 is a triple master slave flip flop with differential outputs. ata enters the master latch when the clock input is OW and transfers to the slave
More informationNTLJD4116NT1G. Power MOSFET. 30 V, 4.6 A, Cool Dual N Channel, 2x2 mm WDFN Package
NTLJDN Power MOSFET V,. A, Cool Dual N Channel, x mm WDFN Package Features WDFN Package Provides Exposed Drain Pad for Excellent Thermal Conduction x mm Footprint Same as SC 88 Lowest R DS(on) Solution
More informationMMSZ4678ET1 Series. Zener Voltage Regulators. 500 mw SOD 123 Surface Mount
MMSZ4678ET Series Zener Voltage Regulators 5 mw SOD 3 Surface Mount Three complete series of Zener diodes are offered in the convenient, surface mount plastic SOD 3 package. These devices provide a convenient
More informationMBD301G, MMBD301LT1G. Silicon Hot-Carrier Diodes. SCHOTTKY Barrier Diodes 30 VOLTS SILICON HOT CARRIER DETECTOR AND SWITCHING DIODES
Silicon Hot-Carrier iodes SCHOTTKY Barrier iodes These devices are designed primarily for high efficiency UHF and VHF detector applications. They are readily adaptable to many other fast switching RF and
More informationMJD44H11 (NPN) MJD45H11 (PNP)
MJDH (NPN) MJD5H (PNP) Preferred Device Complementary Power Transistors For Surface Mount Applications Designed for general purpose power and switching such as output or driver stages in applications such
More informationMC100EPT V LVTTL/LVCMOS to LVPECL Translator Description The MC100EPT622 is a 10- Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL (Positiv
3.3V VTT/VCMOS to VPEC Translator Description The is a 0- Bit VTT/VCMOS to VPEC translator. Because VPEC (Positive EC) levels are used only +3.3 V and ground are required. The device has an OR- ed enable
More informationMMSZ5221BT1 Series. Zener Voltage Regulators. 500 mw SOD 123 Surface Mount
MMSZ5BT Series Preferred Device Zener Voltage Regulators 5 mw SOD 3 Surface Mount Three complete series of Zener diodes are offered in the convenient, surface mount plastic SOD 3 package. These devices
More informationMC GHz Low Power Prescaler With Stand-By Mode
2.5 GHz Low Power Prescaler With Stand-By Mode Description The M1295 is a single modulus prescaler for low power frequency division of a 2.5 GHz high frequency input signal. MOSAI V technology is utilized
More informationMJD44H11 (NPN) MJD45H11 (PNP) Complementary Power Transistors. DPAK For Surface Mount Applications
MJDH (NPN) MJD5H (PNP) Complementary Power Transistors For Surface Mount Applications Designed for general purpose power and switching such as output or driver stages in applications such as switching
More informationNVLJD4007NZTBG. Small Signal MOSFET. 30 V, 245 ma, Dual, N Channel, Gate ESD Protection, 2x2 WDFN Package
NVLJD7NZ Small Signal MOSFET V, 2 ma, Dual, N Channel, Gate ESD Protection, 2x2 WDFN Package Features Optimized Layout for Excellent High Speed Signal Integrity Low Gate Charge for Fast Switching Small
More informationMUN5211DW1T1 Series. NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
MUNDWT Series Preferred Devices Dual Bias Resistor Transistors NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The BRT (Bias Resistor Transistor) contains a single transistor
More informationNUP4302MR6T1G. Schottky Diode Array for Four Data Line ESD Protection
Schottky Diode Array for Four Data Line ESD Protection The NUP432MR6 is designed to protect high speed data line interface from ESD, EFT and lighting. Features Very Low Forward Voltage Drop Fast Switching
More informationMC10EP142, MC100EP V / 5 VНECL 9 Bit Shift Register
MC0EP42, MCEP42 3.3 V / 5 VНECL Bit Shift Register The MC0EP/EP42 is a bit shift register, designed with byte-parity applications in mind. The MC0/EP42 is capable of performing serial/parallel data into
More informationMC3488A. Dual EIA 423/EIA 232D Line Driver
Dual EIA423/EIA232D Line Driver The MC34A dual is singleended line driver has been designed to satisfy the requirements of EIA standards EIA423 and EIA232D, as well as CCITT X.26, X.2 and Federal Standard
More informationNLHV18T Channel Level Shifter
18-Channel Level Shifter The NLHV18T3244 is an 18 channel level translator designed for high voltage level shifting applications such as displays. The 18 channels are divided into twelve and two three
More informationPZTA92T1. High Voltage Transistor. PNP Silicon SOT 223 PACKAGE PNP SILICON HIGH VOLTAGE TRANSISTOR SURFACE MOUNT
High Voltage Transistor PNP Silicon Features These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant MAXIMUM RATINGS (T C = 25 C unless otherwise noted) Rating Symbol Value Unit Collector-Emitter
More informationPCS2P2309/D. 3.3V 1:9 Clock Buffer. Functional Description. Features. Block Diagram
3.3V 1:9 Clock Buffer Features One-Input to Nine-Output Buffer/Driver Buffers all frequencies from DC to 133.33MHz Low power consumption for mobile applications Less than 32mA at 66.6MHz with unloaded
More informationMARKING DIAGRAMS* ORDERING INFORMATION 8 1 SO 8 D SUFFIX CASE 751 KEP51 ALYW HEP51 ALYW 8 1 TSSOP 8 DT SUFFIX CASE 948R KP51 ALYW
The MC0/EP5 is a differential clock flip flop with reset. The device is functionally equivalent to the E5 and VE5 devices. The reset input is an asynchronous, level triggered signal. ata enters the master
More informationNLAS3699B. Dual DPDT Ultra Low R ON Switch
Dual DPDT Ultra Low R ON Switch The NLAS3699B is a dual independent ultra low R ON DPDT analog switch. This device is designed for low operating voltage, high current switching of speaker output for cell
More informationNTS2101P. Power MOSFET. 8.0 V, 1.4 A, Single P Channel, SC 70
NTS11P Power MOSFET 8. V, 1.4 A, Single P Channel, SC 7 Features Leading Trench Technology for Low R DS(on) Extending Battery Life 1.8 V Rated for Low Voltage Gate Drive SC 7 Surface Mount for Small Footprint
More informationNLAS323. Dual SPST Analog Switch, Low Voltage, Single Supply A4 D
Dual SPST Analog Switch, Low Voltage, Single Supply The NLAS323 is a dual SPST (Single Pole, Single Throw) switch, similar to /2 a standard 466. The device permits the independent selection of 2 analog/digital
More informationMMSZ2V4T1 Series. Zener Voltage Regulators. 500 mw SOD 123 Surface Mount
MMSZVT Series Zener Voltage Regulators 5 mw SOD 3 Surface Mount Three complete series of Zener diodes are offered in the convenient, surface mount plastic SOD 3 package. These devices provide a convenient
More informationMUN5311DW1T1G Series.
MUNDWTG Series Preferred Devices Dual Bias Resistor Transistors NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The Bias Resistor Transistor (BRT) contains a single
More information