NBSG53ABAR2. 2.5V/3.3VНSiGe Selectable Differential Clock and Data D Flip Flop/Clock Divider with Reset and OLS*

Transcription

1 NBSG3A.V/3.3VНSiGe Selectable Differential Clock and Data D Flip Flop/Clock Divider with Reset and OLS* The NBSG3A is a multi-function differential D flip-flop (DFF) or fixed divide by two (DIV/) clock generator. This is a part of the GigaComm family of high performance Silicon Germanium products. A strappable control pin is provided to select between the two functions. The device is housed in a low profile 4x4 mm 16-pin Flip-Chip BGA (FCBGA) or a 3x3 mm 16 pin FN package. The NBSG3A is a device with data, clock, OLS, reset, and select inputs. Differential inputs incorporate internal termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVCMOS/LVTTL, CML, or LVDS. The OLS input is used to program the peak- to- peak output amplitude between and 8 in five discrete steps. The RESET and SELECT inputs are single- ended and can be driven with either LVECL or LVCMOS/LVTTL input levels. Data is transferred to the outputs on the positive edge of the clock. The differential clock inputs of the NBSG3A allow the device to also be used as a negative edge triggered device. Maximum Input Clock Frequency (DFF) > 8 GHz Typical (See Figures 4, 6, 8, 1, and 11) Maximum Input Clock Frequency (DIV/) > 1 GHz Typical (See Figures, 7, 9, 1, and 11) 1 ps Typical Propagation Delay (OLS = FLOAT) 4 ps Typical Rise and Fall Times (OLS = FLOAT) DIV/ Mode (Active with Select Low) DFF Mode (Active with Select High) Selectable Swing PECL Output with Operating Range: V CC =.37 V to 3.46 V with V EE = V Selectable Swing NECL Output with NECL Inputs with Operating Range: V CC = V with V EE = -.37 V to V Selectable Output Level ( V,, 4, 6, or 8 Peak-to-Peak Output) Internal Input Termination Resistors on all Differential Inputs *Output Level Select FCBGA-16 BA SUFFIX CASE 489 MARKING DIAGRAM** SG 3A LYW **For further details, refer to Application Note AND8/D Device Package Shipping NBSG3ABA NBSG3ABAR NBSG3MN FN-16 MN SUFFIX CASE 48G NBSG3MNR ORDERING INFORMATION 4x4 mm FCBGA-16 4x4 mm FCBGA-16 3x3 mm FN-16 3x3 mm FN-16 SG3A ALYW A = Assembly Location L = Wafer Lot Y = Year W = Work Week 1 Units/Tray /Tape & Reel 13 Units/Rail 3/Tape & Reel Board NBSG3ABAEVB Description NBSG3ABA Evaluation Board Semiconductor Components Industries, LLC, 3 April, 3 - Rev. 4 1 Publication Order Number: NBSG3A/D

2 NBSG3A A VTD D D VTD V CC R SEL OLS Exposed Pad (EP) VTCLK 1 1 V EE B C CLK CLK VTCLK VTCLK V CC V EE CLK CLK 3 NBSG3A 11 1 D V CC R SEL OLS Figure 1. BGA-16 Pinout (Top View) Table 1. Pin Description Pin VTCLK 4 9 V CC VTD D D VTD Figure. FN-16 Pinout (Top View) BGA FN Name I/O Description C 1 VTCLK - Internal Termination Pin. See Table 4. C1 CLK ECL, CML, LVCMOS, LVDS, LVTTL Input B1 3 CLK ECL, CML, LVCMOS, LVDS, LVTTL Input Inverted Differential Input. Noninverted Differential Input. B 4 VTCLK - Internal Termination Pin. See Table 4. A1 VTD - Internal termination pin. See Table 4. A 6 D ECL, CML, LVCMOS, LVDS, LVTTL Input A3 7 D ECL, CML, LVCMOS, LVDS, LVTTL Input Inverted Differential Input. Noninverted Differential Input. A4 8 VTD - Internal Termination Pin. See Table 4. D1,B3 9,16 Positive Supply Voltage B4 1 RSECL Output Inverted Differential Output. Typically Terminated with Resistor to V TT = V. C4 11 RSECL Output Noninverted Differential Output. Typically Terminated with Resistor to V TT = V. C3 1 V EE - Negative Supply Voltage D4 13 OLS* Input Input Pin for the Output Level Select (OLS). See Table. D3 14 SEL LVECL, LVCMOS, LVTTL Input D 1 R LVECL, LVCMOS, LVTTL Input Select Logic Input. Internal 7 k to V EE. Reset D Flip-Flop. Internal 7 k to V EE. N/A - EP Exposed Pad. (Note 1) 1. All V CC and V EE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a heat-sinking conduit.. In the differential configuration when the input termination pins (VTD, VTD, VTCLK, VTCLK) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self-oscillation. 3. When an output level of 4 is desired and V EE > 3. V, K resistor should be connected from OLS pin to V EE.

3 NBSG3A V CC OLS VTD D D VTD D Flip-Flop (DFF) R 1 VTCLK CLK D Flip-Flop (DIV/) CLK VTCLK R R SEL 7 k 7 k V EE Figure 3. Simplified Logic Diagram Table. OUTPUT LEVEL SELECT (OLS) OLS / VPP OLS Sensitivity V CC 8 OLS V OLS 1.8 V 6 OLS 1 1. V OLS 7 V EE (Note 4) 4 OLS + 1 Float 6 N/A 4. When an output level of 4 is desired and V EE > 3. V,. k resistor should be connected from OLS to V EE. Table 3. TRUTH TABLE R SEL D CLK Function H x x x L Reset L H L Z L DFF L H H Z H DFF L L x Z DIV/ Z = LOW to HIGH Transition Table 4. INTERFACING OPTIONS INTERFACING OPTIONS CML LVDS CONNECTIONS Connect VTCLK, VTD and VTCLK, VTD to V CC Connect VTCLK, VTD and VTCLK, VTD Together AC-COUPLED Bias VTCLK, VTD and VTCLK, VTD Inputs within Common Mode Range (V IHCMR ) RSECL, PECL, NECL LVTTL, LVCMOS Standard ECL Termination Techniques An External Voltage (V THR ) should be Applied to the Unused Complementary Differential Input. Nominal V THR is 1. V for LVTTL and V CC / for LVCMOS Inputs. This Voltage must be within the V THR Specification. 3

4 NBSG3A Table. ATTRIBUTES Characteristics Positive Operating Voltage Range for V CC (V EE = V) Negative Operating Voltage Range for V EE (V CC = V) Internal Input Pulldown Resistor (R, SEL) ESD Protection Human Body Model Machine Model Charged Device Model Value.37 V to 3.46 V -.37 V to V 7 k > 1. kv > V > 4 kv Moisture Sensitivity (Note ) 16-FCBGA 16-FN Level 3 Level 1 Flammability Rating UL 94 in Oxygen Index 8 to 34 Transistor Count 48 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test. For additional information, refer to Application Note AND83/D. Table 6. MAXIMUM RATINGS (Note 6) Symbol Parameter Condition 1 Condition Rating Units V CC Positive Power Supply V EE = V 3.6 V V EE Negative Power Supply V CC = V -3.6 V V I Positive Input Negative Input V EE = V V CC = V V I V CC V I V EE V V V INPP Differential Input Voltage D - D V EE.8 V V EE <.8 V I IN Input Current Through R T ( Resistor) Static Surge I OUT Output Current Continuous Surge T A Operating Temperature Range 16 FCBGA 16 FN.8 V EE to +7-4 to +8 V V ma ma ma ma C T stg Storage Temperature Range -6 to +1 C JA Thermal Resistance (Junction-to-Ambient) (Note 7) LFPM LFPM LFPM LFPM 16 FCBGA 16 FCBGA 16 FN 16 FN C/W C/W C/W C/W JC Thermal Resistance (Junction-to-Case) SP (Note 7) SP (Note 8) 16 FCBGA 16 FN. 4. C/W C/W T sol Wave Solder < 1 Seconds C 6. Maximum Ratings are those values beyond which device damage may occur. 7. JEDEC standard 1-6, multilayer board - SP ( signal, power). 8. JEDEC standard multilayer board - SP ( signal, power) with 8 filled thermal vias under exposed pad. 4

5 NBSG3A Table 7. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT V CC =. V; V EE = V (Note 9) -4 C C 7 C(BGA)/8 C(FN)** Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit I EE Negative Power Supply Current ma V OH Output HIGH Voltage (Note 1) V OL Output LOW Voltage (Note 1) (OLS =.4 V) (OLS =.8 V, OLS = FLOAT) (OLS = 1. V) (OLS = V EE ) V OUTPP V IH Output Voltage Amplitude (OLS =.4 V) (OLS =.8 V, OLS = FLOAT) (OLS = 1. V) (OLS = V EE ) Input HIGH Voltage (Single-Ended) (Notes 1 and 14) CLK, CLK, D, D * V CC * V CC * V CC V IL Input LOW Voltage (Single-Ended) (Notes 13 and 14) CLK, CLK, D, D V EE 14* 1 V EE 14* 1 V EE 14* 1 V IH Input High Voltage (Single-Ended) R, SEL 19 V CC 13 V CC 141 V CC V IL Input Low Voltage (Single-Ended) R, SEL V EE 89 V EE 9 V EE 11 V THR Input Threshold Voltage (Single-Ended) (Note 14) V IHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 11) V R TIN Internal Input Termination Resistor I IH Input HIGH Current (@V IH ) R, SEL CLK, CLK, D, D I IL Input LOW Current (@V IL ) R, SEL CLK, CLK, D, D 3 NOTE: GigaComm circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than lfpm is maintained. 9. Input and output parameters vary 1:1 with V CC. V EE can vary +.1 V to -.96 V. 1.All outputs loaded with to. V. 11. V IHCMR min varies 1:1 with V EE, V IHCMR max varies 1:1 with V CC. The V IHCMR range is referenced to the most positive side of the differential input signal. 1.V IH cannot exceed V CC. V THR < V IL always V EE. V IL - V THR < V THR is the voltage applied to one input when running in single-ended mode. *Typicals used for testing purposes. **The device packaged in FCBGA-16 have maximum ambient temperature specification of 7 C and devices packaged in FN-16 have maximum ambient temperature specification of 8 C A A

6 NBSG3A Table 8. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT V CC = 3.3 V; V EE = V (Note 1) -4 C C 7 C(BGA)/8 C(FN)*** Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit I EE Negative Power Supply Current ma V OH Output HIGH Voltage (Note 16) V OL Output LOW Voltage (Note 16) (OLS =.4 V) (OLS =.8 V, OLS = FLOAT) (OLS = 1. V) **(OLS = V EE ) V OUTPP V IH Output Amplitude Voltage (OLS =.4 V) (OLS =.8 V, OLS = FLOAT) (OLS = 1. V) **(OLS = V EE ) Input HIGH Voltage (Single-Ended) (Notes 18 and ) CLK, CLK, D, D * V CC * V CC * V CC V IL Input LOW Voltage (Single-Ended) (Notes 19 and ) CLK, CLK, D, D 6 14* * * 1 V IH Input High Voltage (Single-Ended) R, SEL 9 V CC 1 V CC 1 V CC V IL Input Low Voltage (Single-Ended) R, SEL V EE 169 V EE 17 V EE 181 V THR Input Threshold Voltage (Single-Ended) (Note ) V IHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 17) V R TIN Internal Input Termination Resistor I IH Input HIGH Current (@V IH ) R, SEL CLK, CLK, D, D I IL Input LOW Current (@V IL ) R, SEL CLK, CLK, D, D 3 NOTE: GigaComm Circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than lfpm is maintained. 1.Input and output parameters vary 1:1 with V CC. V EE can vary +.9 V to -.16 V. 16.All outputs loaded with to. V. 17.V IHCMR min varies 1:1 with V EE, V IHCMR max varies 1:1 with V CC. The V IHCMR range is referenced to the most positive side of the differential input signal. 18.V IH cannot exceed V CC. V THR < V IL always V EE. V IL - V THR < 6..V THR is the voltage applied to one input when running in single-ended mode. *Typicals used for testing purposes. **When an output level of 4 is desired and V EE > 3. V, a k resistor should be connected from OLS to V EE. ***The device packaged in FCBGA-16 have maximum ambient temperature specification of 7 C and devices packaged in FN-16 have maximum ambient temperature specification of 8 C A A 6

7 NBSG3A Table 9. DC CHARACTERISTICS, NECL INPUT WITH NECL OUTPUT V CC = V; V EE = V to -.37 V (Note 1) -4 C C 7 C(BGA)/8 C(FN)*** Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit I EE Negative Power Supply Current ma V OH Output HIGH Voltage (Note ) V OL Output LOW Voltage (Note ) V V EE -3. V (OLS =.4 V) (OLS =.8 V, OLS =FLOAT) (OLS = 1. V) **(OLS = V EE ) -3. V < V EE -.37 V (OLS =.4 V) (OLS =.8 V, OLS =FLOAT) (OLS = 1. V) (OLS = V EE ) V OUTPP V IH Output Voltage Amplitude V V EE -3. V (OLS =.4 V) (OLS =.8 V, OLS = FLOAT) (OLS = 1. V) **(OLS = V EE ) -3. V < V EE -.37 V (OLS =.4 V) (OLS =.8 V, OLS =FLOAT) (OLS = 1. V) (OLS = V EE ) Input HIGH Voltage (Single- Ended) (Notes 4 and 6) CLK, CLK, D, D * V CC * V CC * V CC V IL Input LOW Voltage (Single- Ended) (Notes and 6) CLK, CLK, D, D 6 14* * * 1 V IH V IL Input High Voltage (Single-Ended) R, SEL V CC Input Low Voltage (Single-Ended) R, SEL V EE -161 V EE -14 V EE -148 V THR Input Threshold Voltage (Single-Ended) (Note 6) V IHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 3) V NOTE: GigaComm circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than lfpm is maintained. 1.Input and output parameters vary 1:1 with V CC..All outputs loaded with to. V. 3.V IHCMR min varies 1:1 with V EE, V IHCMR max varies 1:1 with V CC. The V IHCMR range is referenced to the most positive side of the differential input signal. 4.V IH cannot exceed V CC. V THR < 6..V IL always V EE. V IL - V THR < 6. 6.V THR is the voltage applied to one input when running in single-ended mode. *Typicals used for testing purposes. **When an output level of 4 is desired and V EE > 3. V, a k resistor should be connected from OLS to V EE. ***The device packaged in FCBGA-16 have maximum ambient temperature specification of 7 C and devices packaged in FN-16 have maximum ambient temperature specification of 8 C. 7

8 NBSG3A Table 9. DC CHARACTERISTICS, NECL INPUT WITH NECL OUTPUT V CC = V; V EE = V to -.37 V (Note 1) (continued) Symbol Characteristic Min -4 C Typ Max Min C Typ Max 7 C(BGA)/8 C(FN)*** R TIN Internal Input Termination Resistor I IH Input HIGH Current (@V IH ) R, SEL CLK, CLK, D, D I IL Input LOW Current (@V IL ) R, SEL CLK, CLK, D, D I OLS OLS Input Current (See Figure 1) (OLS =.4 V) (OLS =.8 V, OLS = FLOAT) (OLS = 1. V) V V EE -3. V *(OLS = V EE ) -3. V < V EE -.37 V (OLS = V EE ) NOTE: GigaComm circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than lfpm is maintained. 1.Input and output parameters vary 1:1 with V CC..All outputs loaded with to. V. 3.V IHCMR min varies 1:1 with V EE, V IHCMR max varies 1:1 with V CC. The V IHCMR range is referenced to the most positive side of the differential input signal. 4.V IH cannot exceed V CC. V THR < 6..V IL always V EE. V IL - V THR < 6. 6.V THR is the voltage applied to one input when running in single-ended mode. *Typicals used for testing purposes. **When an output level of 4 is desired and V EE > 3. V, a k resistor should be connected from OLS to V EE. ***The device packaged in FCBGA-16 have maximum ambient temperature specification of 7 C and devices packaged in FN-16 have maximum ambient temperature specification of 8 C Min Typ Max Unit A A A 8

9 NBSG3A Table 1. AC CHARACTERISTICS for FCBGA-16 V CC = V; V EE = V to -.37 V or V CC =.37 V to 3.46 V; V EE = V -4 C C 7 C Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit f max Maximum Frequency GHz (See Figures 4, 6, 8, 1, and 11) DFF (See Figures, 7, 9, 1, and 11) (Note 7) DIV/ t PLH, t PHL Propagation Delay to Output Differential CLK, (OLS =.4 V) (OLS =.8 V, OLS = FLOAT) **(OLS = V EE ) SEL, (OLS =.4 V) (OLS =.8 V, OLS = FLOAT) **(OLS = V EE ) R, DIV/ DFF (OLS =.4 V) DIV/ (OLS =.4 V) DFF (OLS =.8 V, OLS = FLOAT) DIV/ (OLS =.8 V, OLS = FLOAT) DFF **(OLS = V EE ) DIV/ **(OLS = V EE ) DFF t SKEW Duty Cycle Skew (Notes 8 and 3) DFF ps t JITTER V INPP RMS Random Clock Jitter f in 8 GHz (See Figures 4 and 6) (Note 7) Peak-to-Peak Data Dependent Jitter f in = 8 Gb/s Input Voltage Swing/Sensitivity (Differential Configuration) (Note 9) t r Output Rise/Fall Times (% - 8%) t 1 GHz, (OLS =.4 V) (OLS =.8 V, OLS = FLOAT) **(OLS = V EE ) TBD t s Setup Time D CLK ps t h Hold Time D CLK ps t rr Reset Recovery DFF, DIV/ ps 7.Measured using a source, % duty cycle clock source. Repetitive 11 input data pattern. All outputs loaded with to. V. Input edge rates is 4 ps (% - 8%). 8.See Figure 14. t SKEW = t PLH - t PHL for a nominal % differential clock input waveform. 9.V INPP (MAX) cannot exceed V EE (Applicable only when V EE < 6 ). 3.See Figure 1. Duty Cycle % vs. Frequency. **When an output level of 4 is desired and V EE > 3. V, a k resistor should be connected from OLS to V EE ps ps ps 9

10 NBSG3A Table 11. AC CHARACTERISTICS for FN-16 V CC = V; V EE = V to -.37 V or V CC =.37 V to 3.46 V; V EE = V -4 C C 8 C Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit f max Maximum Frequency GHz (See Figures 4, 6, 8, 1, and 11) DFF (See Figures, 7, 9, 1, and 11) (Note 31) DIV/ t PLH, t PHL Propagation Delay to Output Differential (Note 3) CLK, SEL, R, D IN / DFF t SKEW Duty Cycle Skew (Notes 3 and 34) DFF ps t JITTER V INPP RMS Random Clock Jitter f in 8 GHz (See Figures 4 and 6) (Note 31) Peak-to-Peak Data Dependent Jitter f in = 8 Gb/s Input Voltage Swing/Sensitivity (Differential Configuration) (Note 33) t r Output Rise/Fall Times (% - 8%) t 1 GHz, (OLS =.4 V) (OLS =.8 V, OLS = FLOAT) **(OLS = V EE ). TBD TBD TBD t s Setup Time D CLK ps t h Hold Time D CLK 1 7 ps t rr Reset Recovery DFF, DIV/ ps 31.Measured using a source, % duty cycle clock source. Repetitive 11 input data pattern. All outputs loaded with to. V. Input edge rates is 4 ps (% - 8%). 3.See Figure 14. t SKEW = t PLH - t PHL for a nominal % differential clock input waveform. 33.V INPP (MAX) cannot exceed V EE (Applicable only when V EE < 6 ). 34.See Figure 1. Duty Cycle % vs. Frequency. 3. For all OLS Configuration. **When an output level of 4 is desired and V EE > 3. V, a k resistor should be connected from OLS to V EE. ***The device packaged in FCBGA-16 have maximum ambient temperature specification of 7 C and devices packaged in FN-16 have maximum ambient temperature specification of 8 C ps ps ps 1

11 NBSG3A 9 8 OLS = V CC 9 8 OUTPUT VOLTAGE AMPLITUDE OLS =.8 V, OLS = FLOAT 7 6 *OLS = V EE 4 OLS =.4 V 3 1 RMS JITTER INPUT FREUENCY (GHz) JITTER OUT ps (RMS) Figure 4. Output Voltage Amplitude (V OUTPP ) / RMS Jitter vs. Input Frequency (f in ) for DFF Mode ( V EE = 3.3 C; Repetitive 11 Input Data Pattern) OUTPUT VOLTAGE AMPLITUDE OLS = V CC OLS =.8 V, OLS = FLOAT *OLS = V EE OLS =.4 V INPUT FREUENCY (GHz) Figure. Output Voltage Amplitude (V OUTPP ) / RMS Jitter vs. Input Frequency (f in ) for DIV/ Mode ( V EE = 3.3 C) *When an output level of 4 is desired and V EE > 3. V, a k resistor should be connected from OLS to V EE. 11

12 NBSG3A 9 8 OLS = V CC 9 8 OUTPUT VOLTAGE AMPLITUDE OLS = V 7 CC -.8 V, OLS = FLOAT 6 *OLS = V EE 4 OLS =.4 V 3 1 RMS JITTER INPUT FREUENCY (GHz) JITTER OUT ps (RMS) Figure 6. Output Voltage Amplitude (V OUTPP ) / RMS Jitter vs. Input Frequency (f in ) for DFF Mode ( V EE =. C; Repetitive 11 Input Data Pattern) 9 8 OLS = V CC OUTPUT VOLTAGE AMPLITUDE *OLS =.8 V, OLS = FLOAT OLS = V EE OLS =.4 V INPUT FREUENCY (GHz) Figure 7. Output Voltage Amplitude (V OUTPP ) / RMS Jitter vs. Input Frequency (f in ) for DIV/ Mode ( V EE =. C) *When an output level of 4 is desired and V EE > 3. V, a k resistor should be connected from OLS to V EE. 1

13 NBSG3A V OH /V OL () V OH () V OH () V OL () V OL () INPUT FREUENCY (GHz) Figure 8. V OH /V OL (/) vs. Input Frequency (f in ) for DFF Mode ( V EE = 3.3 C and OLS =.8 V, OLS = FLOAT) V OH /V OL () V OH () V OH () V OL () V OL () INPUT FREUENCY (GHz) Figure 9. V OH /V OL (/) vs. Input Frequency (f in ) for DIV/ Mode ( V EE = 3.3 C and OLS =.8 V, OLS = FLOAT) 13

14 NBSG3A DUTY CYCLE (%) DIV/ Mode DFF Mode INPUT FREUENCY (GHz) Figure 1. Duty Cycle % vs. Input Frequency (f in ) ( V EE = 3.3 C) DUTY CYCLE (%) DIV/ Mode DFF Mode INPUT FREUENCY (GHz) Figure 11. Duty Cycle % vs. Input Frequency (f in ) ( V EE =. 7 C) 14

15 NBSG3A 3 1 I OLS ( A) V CC V EE V OLS () Figure 1. Typical OLS Input Current vs. OLS Input Voltage ( V EE = 3.3 C) V outpp () V CC OLS () V EE Figure 13. OLS Operating Area 1

16 NBSG3A CLK CLK V INPP = V IH (CLK) - V IL (CLK) V OUTPP = V OH () - V OL () t PHL t PLH Figure 14. AC Reference Measurement Driver Device D D Receiver Device V TT V TT =. V Figure 1. Typical Termination for Output Driver and Device Evaluation (Refer to Application Note AND8 - Termination of ECL Logic Devices) 16

17 NBSG3A PACKAGE DIMENSIONS FCBGA-16 BA SUFFIX PLASTIC 4 X 4 (mm) BGA FLIP CHIP PACKAGE CASE ISSUE O LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA -X- -Y- E 3 X e. S D VIEW M-M A B C D 3 16 X b K M M FEDUCIAL FOR PIN A1 IDENTIFICATION IN THIS AREA.1 M Z X Y.8 M Z NOTES: 1. DIMENSIONS ARE IN MILLIMETERS.. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.M, DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. MILLIMETERS DIM MIN MAX A 1.4 MAX A1..3 A 1. REF b.3. D 4. BSC E 4. BSC e 1. BSC S. BSC.1 Z A A A X.1 Z -Z- DETAIL K ROTATED 9 CLOCKWISE 17

18 NBSG3A PACKAGE DIMENSIONS 16 PIN FN MN SUFFIX CASE 48G-1 ISSUE O A M -X- -Y- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.M, CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION D APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN. AND.3 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.. (.1) T. (.1) T R.8 (.3) T K N J B C -T- SEATING PLANE MILLIMETERS INCHES DIM MIN MAX MIN MAX A 3. BSC.118 BSC B 3. BSC.118 BSC C D E F G. BSC. BSC H J. REF.8 REF K.... L M 1. BSC.9 BSC N 1. BSC.9 BSC P R E L 8 G H 4 9 F D NOTE 3.1 (.4) M T X Y P GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 163, Denver, Colorado 817 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada ONlit@hibbertco.com N. American Technical Support: Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center -9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 13-1 Phone: ON Semiconductor Website: For additional information, please contact your local Sales Representative. 18 NBSG3A/D