NBSG16M. 2.5 V/3.3 V Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer

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1 2.5 V/3.3 V Multilevel Input to CML Clock/ata Receiver/river/Translator Buffer escription The NBSG6M is a differential current mode logic (CML) receiver/driver/translator buffer. The device is functionally equivalent to the EP6, LVEP6, or SG6 devices with CML output structure and lower EMI capabilities. Inputs incorporate internal termination resistors and accept LVNECL (Negative ECL), LVPECL (Positive ECL), LVTTL, LVCMOS, CML, or LVS. The CML output structure contains internal source termination resistor to. The device generates output amplitude with receiver resistor to. The V BB pin is internally generated voltage supply available to this device only. For all single-ended input conditions, the unused complementary differential input is connected to V BB as a switching reference voltage. V BB may also rebias AC coupled inputs. When used, decouple V BB via a 0.0 F capacitor and limit current sourcing or sinking to 0.5 ma. When not used, V BB output should be left open. Features Maximum Input Clock Frequency > GHz Typical Maximum Input ata Rate > Gb/s Typical 20 ps Typical Propagation elay 35 ps Typical Rise and Fall Times Positive CML Output with Operating Range: = 2.3 V to V with = 0 V Negative CML Output with RSNECL or NECL Inputs with Operating Range: = 0 V with = 2.3 V to V CML Output Level; Peak-to-Peak Output with Receiver Resistor to Internal Input and Output Termination Resistors Compatible with Existing 2.5 V/3.3 V LVEP, EP, LVEL and SG evices V BB Reference Voltage Output These are Pb-Free evices A L Y W FN 6 MN SUFFIX CASE 485G MARKG IAGRAM* 6 SG 6M ALYW = Assembly Location = Wafer Lot = Year = Work Week = Pb Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AN8002/. ORERG FORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. Semiconductor Components Industries, LLC, 204 June, 204 Rev. 9 Publication Order Number: NBSG6M/

2 V BB Exposed Pad (EP) VT NBSG6M VT NC Figure. FN 6 Pinout (Top View) Table. P ESCRIPTION Pin Name I/O escription ÁÁÁÁÁÁ V T ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 2 LVS, CML, ECL, LVTTL, LVCMOS Input Internal Termination Pin. See Table 2. (Note 2) Inverted ifferential Input (Note 2) 3 LVS, CML, ECL, LVTTL, LVCMOS Input Noninverted ifferential Input. (Note 2) 4 V T Internal Termination Pin. See Table 2. (Note 2) 5 Positive Supply Voltage. All pins must be externally connected to Power Supply to 6 NC No Connect 7 Negative Supply Voltage. All pins must be externally connected to Power Supply to 8 Negative Supply Voltage. All pins must be externally connected to Power Supply to 9 Positive Supply Voltage. All pins must be externally connected to Power Supply to CML Output Noninverted CML ifferential Output with Internal Source Termination Resistor. (Note ) CML Output Inverted CML ifferential Output with Internal Source Termination Resistor. (Note ) 2 Positive Supply Voltage. All pins must be externally connected to Power Supply to 3 Negative Supply Voltage. All pins must be externally connected to Power Supply to 4 Negative Supply Voltage. All pins must be externally connected to Power Supply to 5 V BB Internally Generated ECL Reference Output Voltage 6 Positive Supply Voltage. All pins must be externally connected to Power Supply to EP The Exposed Pad (EP) on the FN 6 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat-sinking conduit. The pad is not electrically connected to the die but may be electrically and thermally connected to on the PC board.. CML outputs require receiver termination resistor to for proper operation. 2. In the differential configuration when the input termination pin (V T, V T ) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self-oscillation. 2

3 VT VT V BB Figure 2. Logic iagram 6 ma Figure 3. CML Output Structure Table 2. Interfacing Options TERFACG OPTIONS CML LVS CONNECTIONS Connect VT and VT to Connect VT and VT together AC COUPLE Bias VT and VT Inputs within (V IHCMR ) Common Mode Range RSECL, PECL, NECL LVTTL, LVCMOS Standard ECL Termination Techniques An external voltage should be applied to the unused complementary differential input. Nominal voltage.5 V for LVTTL and /2 for LVCMOS inputs. Table 3. ATTRIBUTES Characteristics Value ES Protection Human Body Model Machine Model Charged evice Model > kv > 0 V > 4 kv Moisture Sensitivity, Indefinite Time Out of rypack (Note 3) Level Flammability Rating Oxygen Index: 28 to 34 UL 94 V 0.25 in Transistor Count 45 Meets or exceeds JEEC Spec EIA/JES78 IC Latchup Test 3. For additional Moisture Sensitivity information, refer to Application Note AN8003/. 3

4 Table 4. MAXIMUM RATGS Symbol Parameter Condition Condition 2 Rating Unit Positive Power Supply = 0 V 3.6 V Negative Power Supply = 0 V 3.6 V V I Positive Input Negative Input = 0 V = 0 V V I 3.6 V I 3.6 V V PP ifferential Input Voltage 2.8 V < 2.8 V I Input Current Through R T ( Resistor) Static Surge I out Output Current Continuous Surge V ma ma I BB V BB Sink/Source.0 ma T A Operating Temperature Range to +85 C T stg Storage Temperature Range 65 to + C JA Thermal Resistance (Junction-to-Ambient) (Note 4) 0 lfpm 500 lfpm C/W JC Thermal Resistance (Junction-to-Case) S2P (Note 4) 4.0 C/W T sol Wave Solder Pb-Free <2 to C 265 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 4. JEEC standard multilayer board S2P ( signal, 2 power) 4

5 Table 5. C CHARACTERISTICS, POSITIVE CML OUTPUT ( = 2.5 V; = 0 V) (Note 5) C 25 C 85 C Symbol Characteristic POWER SUPPLY CURRENT Min Typ Max Min Typ Max Min Typ Max Unit I CC Positive Power Supply Current ma CML OUTPUTS (Note 6) V OH Output HIGH Voltage V OL Output LOW Voltage IFFERENTIAL CLOCK PUTS RIVEN SGLE-ENE (Figures 8 & ) (Note 7) V IH Input HIGH Voltage V IL Input LOW Voltage 0 V IH 0 V IH 0 V IH Input Threshold Voltage Range (Note 8) V ISE Single-Ended Input Voltage (V IH V IL ) V BB ECL Reference Output Voltage IFFERENTIAL PUTS RIVEN IFFERENTIALLY (Figures 9 & ) (Note 9) V IH ifferential Input HIGH Voltage V IL ifferential Input LOW Voltage 0 V IH 0 V IH 0 V IH V I V IHCMR ifferential Input Voltage (V IH V IL ) Input HIGH Voltage Common Mode Range (Note ) (Figure 2) I IH Input HIGH Current (@V IH ) A I IL Input LOW Current (@V IL ) A TERMATION RESISTORS R T Internal Input Termination Resistor R TOUT Internal Output Termination Resistor Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary : with. 6. All loading with to 2.0 V. 7., V IH, V IL, and V ISE parameters must be complied with simultaneously. 8. is applied to the complementary input when operating in single-ended mode. = (V IH V IL ) / V IH, V IL, V I and V IHCMR parameters must be complied with simultaneously..v IHCMR min varies : with, V IHCMR max varies : with. The V IHCMR range is referenced to the most positive side of the differential input signal. 5

6 Table 6. C CHARACTERISTICS, POSITIVE CML OUTPUT ( = 3.3 V; = 0 V) (Note ) C 25 C 85 C Symbol Characteristic POWER SUPPLY CURRENT Min Typ Max Min Typ Max Min Typ Max Unit I CC Positive Power Supply Current ma CML OUTPUTS (Note 2) V OH Output HIGH Voltage V OL Output LOW Voltage IFFERENTIAL CLOCK PUTS RIVEN SGLE-ENE (Figures 8 & ) (Note 3) V IH Input HIGH Voltage V IL Input LOW Voltage 0 V IH 0 V IH 0 V IH Input Threshold Voltage Range (Note 4) V ISE Single-Ended Input Voltage (V IH V IL ) V BB ECL Reference Voltage Output IFFERENTIAL PUTS RIVEN IFFERENTIALLY (Figures 9 & ) (Note 5) V IH ifferential Input HIGH Voltage V IL ifferential Input LOW Voltage 0 V IH 0 V IH 0 V IH V I V IHCMR ifferential Input Voltage (V IH V IL ) Input HIGH Voltage Common Mode Range (Note 6) (Figure 2) I IH Input HIGH Current (@V IH ) A I IL Input LOW Current (@V IL ) A TERMATION RESISTORS R T Internal Input Termination Resistor R TOUT Internal Output Termination Resistor Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously.. Input and output parameters vary : with. 2.All loading with to 2.0 V. 3., V IH, V IL, and V ISE parameters must be complied with simultaneously. 4. is applied to the complementary input when operating in single-ended mode. = (V IH V IL ) / 2. 5.V IH, V IL, V I and V IHCMR parameters must be complied with simultaneously. 6.V IHCMR min varies : with, V IHCMR max varies : with. The V IHCMR range is referenced to the most positive side of the differential input signal. 6

7 Table 7. C CHARACTERISTICS, NEGATIVE CML OUTPUT ( =0V; = V to 2.3 V) (Note 7) C 25 C 85 C Symbol Characteristic POWER SUPPLY CURRENT Min Typ Max Min Typ Max Min Typ Max Unit I CC Positive Power Supply Current ma CML OUTPUTS (Note 8) V OH Output HIGH Voltage V OL Output LOW Voltage IFFERENTIAL CLOCK PUTS RIVEN SGLE-ENE (Figures 8 & ) (Note 9) V IH Input HIGH Voltage V IL Input LOW Voltage V IH V IH V IH Input Threshold Voltage Range (Note 20) V ISE Single-Ended Input Voltage (V IH V IL ) V BB ECL Reference Voltage Output IFFERENTIAL PUTS RIVEN IFFERENTIALLY (Figures 9 & ) (Note 2) V IH ifferential Input HIGH Voltage V IL ifferential Input LOW Voltage V IH V IH V IH V I ifferential Input Voltage (V IH V IL ) V IHCMR Input HIGH Voltage Common Mode Range (Note 22) (Figure 2) I IH Input HIGH Current (@V IH ) A I IL Input LOW Current (@V IL ) A TERMATION RESISTORS R T Internal Input Termination Resistor R TOUT Internal Output Termination Resistor Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7.Input and output parameters vary : with. 8.All loading with to 2.0 V. 9., V IH, V IL, and V ISE parameters must be complied with simultaneously. 20. is applied to the complementary input when operating in single-ended mode. = (V IH V IL ) / 2. 2.V IH, V IL, V I and V IHCMR parameters must be complied with simultaneously. 22.V IHCMR min varies : with, V IHCMR max varies : with. The V IHCMR range is referenced to the most positive side of the differential input signal. 7

8 Table 8. AC CHARACTERISTICS ( = 0 V; = V to 2.3 V or = 2.3 V to V; = 0 V) Symbol Characteristic V OUTPP Output Voltage Amplitude f in < 7 GHz (See Figure 4) (Note 23) f in < GHz C 25 C 85 C Min Typ Max Min Typ Max Min Typ Max Unit t PLH, t PHL Propagation elay to Output ifferential ps t SKEW uty Cycle Skew (Note 24) ps t JITTER RMS Random Clock Jitter (Note 26) f in < GHz Peak-to-Peak ata ependent Jitter (Note 27) f in < Gb/s V PP Input Voltage Swing/Sensitivity (ifferential Configuration) (Note 25) ps t r Output Rise/Fall GHz, tf (20% 80%) ps NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 23.Measured using a source, 50% duty cycle clock source. All loading with to. Input edge rates ps (20% 80%). 24.See Figure 3 t skew = t PLH t PHL for a nominal 50% differential clock input waveform. 25.V PP(max) cannot exceed. (Applicable only when < 2500 ). Input voltage swing is a single-ended measurement operating in differential mode. 26.Additive RMS jitter with 50% duty cycle clock signal at GHz. 27.Additive Peak-to-Peak data dependent jitter with NRZ PRBS2 3 data rate at Gb/s. OUTPUT VOLTAGE AMPLITUE () = 3.3 V = 2.5 V FREUENCY (GHz) Figure 4. Output Voltage Amplitude (V OUTPP ) versus Input Clock Frequency (f in ) at Ambient Temperature (Typical) 8

9 Application Information All inputs can accept PECL, CML, and LVS signal levels. The input voltage can range from to.2 V. Examples interfaces are illustrated below in a environment (Z = ). SG6M Z V T SG6M Z V T Figure 5. CML to CML Interface Recommended R T Values R T PECL river R T R T Z Z V Bias V Bias V T V T SG6M 5.0 V V 2.5 V 80 Figure 7. PECL to CML Receiver Interface LVS river Z Z V T SG6M V T Figure 6. LVS to CML Receiver Interface 9

10 V IH V IL Figure 8. ifferential Input riven Single-Ended Figure 9. ifferential Inputs riven ifferentially max V IHmax V ILmax V IH V IL V I = V IH() V IL() V IH V IL min V IHmin V ILmin Figure. iagram Figure. ifferential Inputs riven ifferentially V IHCMRmax V IHmax V ILmax V IHCMR V IHtyp V I = V IH V IL V ILtyp V IHCMRmin V IHmin V ILmin Figure 2. V IHCMR iagram

11 V PP () = V IH () IL () V PP () = V IH () IL () V OUTPP () = V OH () V OL () V OUTPP () = V OH () V OL () t PHL t PLH Figure 3. AC Reference Measurement river evice Z o = Z o = Receiver evice Figure 4. Typical Termination for Output river and evice Evaluation (Refer to Application Note AN8020 Termination of ECL Logic evices) ORERG FORMATION NBSG6MMNG NBSG6MMNR2G evice Package Shipping FN-6 (Pb-Free / Halide-Free) FN-6 (Pb-Free / Halide-Free) 23 Units / Tube 3000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BR80/.

12 PACKAGE IMENSIONS FN6 3x3, 0.5P CASE 485G ISSUE F 2X P LOCATION 2X NOTE 4 0. C 0.05 C 0.05 C 0. C ETAIL A 6X L ÇÇÇ ÇÇÇ ÇÇÇ TOP VIEW ETAIL B SIE VIEW 2 8 (A3) A B E A A C 0. C A B L EXPOSE Cu SEATG PLANE L ETAIL A ALTERNATE TERMAL CONSTRUCTIONS ÉÉÉ MOL CMP A ETAIL B ALTERNATE CONSTRUCTIONS L ÉÉ PACKAGE OUTLE A3 NOTES:. IMENSIONG AN TOLERANCG PER ASME Y4.5M, CONTROLLG IMENSION: MILLIMETERS. 3. IMENSION b APPLIES TO PLATE TERMAL AN IS MEASURE BETWEEN 0.25 AN 0.30 MM FROM TERMAL. 4. COPLANARITY APPLIES TO THE EXPOSE PA AS WELL AS THE TERMALS. MILLIMETERS IM M NOM MAX A A A REF b BSC E 3.00 BSC E e 0.50 BSC K 0.8 TYP L L RECOMMENE SOLERG FOOTPRT* 6X X K 4 6 e e/2 BOTTOM VIEW 9 E2 6X b 0. C 0.05 C A B NOTE 3 6X X 2X PITCH IMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. The products described herein (NBSG6M), may be covered by U.S. patents including 6,362,644. There may be other patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORERG FORMATION LITERATURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box 563, enver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NBSG6M/

13 Mouser Electronics Authorized istributor Click to View Pricing, Inventory, elivery & Lifecycle Information: ON Semiconductor: NBSG6MMNG NBSG6MMNR2G