HUF733P3F Electrical Specifications T C = o C, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS OFF STATE SPECIFICATIONS

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1 H UF733P3F Data Sheet April 3A, V,.3 Ohm, NChannel, Logic Level UltraFET Power MOSFET Packaging Symbol JEDEC TOAB SOURCE DRAIN GATE DRAIN (FLANGE) D Features Ultra Low OnResistance r DS(ON) =.3Ω, V GS = V r DS(ON) =.3Ω, V GS = V Simulation Models Temperature Compensated PSPICE and SABER Electrical Models Spice and SABER Thermal Impedance Models Peak Current vs Pulse Width Curve UIS Rating Curve Switching Time vs R GS Curves Qualified to AEC Q RoHS Compliant G Ordering Information S PART NUMBER PACKAGE BRAND HUF733P3F TOAB 733P Absolute Maximum Ratings T C = o C, Unless Otherwise Specified Ratings Units Drain to Source Voltage (Note ) S V Drain to Gate Voltage (R GS = kω) (Note ) V DGR V Gate to Source Voltage V GS ± V Drain Current Continuous (T C = o C, V GS = V) I D 3 Continuous (T C = o C, V GS = V) (Figure ) I D 39 Continuous (T C = o C, V GS = V) I D 7 Continuous (T C = o C, V GS = 4.V) (Figure ) I D 7 Pulsed Drain Current I DM Figure 4 Pulsed Avalanche Rating UIS Figures, 7, Power Dissipation P D Derate Above o C Operating and Storage Temperature T J, T STG to 7 o C Maximum Temperature for Soldering Leads at.3in (.mm) from Case for s T L 3 Package Body for s, See Techbrief TB T pkg NOTES:. T J = o C to o C. CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied A A A A W W/ o C o C o C All ON semiconductor products are manufactured, assembled and tested under ISO9 and QS9 quality systems certification. Semiconductor Components Industries, LLC. September7, Rev. 3 Publication Order Number: HUF733P3F/D

2 HUF733P3F Electrical Specifications T C = o C, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BS I D = µa, V GS = V (Figure ) V I D = µa, V GS = V, T C = 4 o C (Figure ) 9 V Zero Gate Voltage Drain Current I DSS = 9V, V GS = V µa = 9V, V GS = V, T C = o C µa Gate to Source Leakage Current I GSS V GS = ±V ± na ON STATE SPECIFICATIONS Gate to Source Threshold Voltage V GS(TH) V GS =, I D = µa (Figure ) 3 V Drain to Source On Resistance r DS(ON) I D = 39A, V GS = V (Figures 9, ).9.3 Ω I D = 7A, V GS = V (Figure 9).3.3 Ω I D = 7A, V GS = 4.V (Figure 9).3.37 Ω THERMAL SPECIFICATIONS Thermal Resistance Junction to Case R θjc TO and TO3.3 o C/W Thermal Resistance Junction to Ambient R θja o C/W SWITCHING SPECIFICATIONS (V GS = 4.V) TurnOn Time t ON V DD = V, I D = 7A ns TurnOn Delay Time t d(on) V GS = 4.V, R GS = 4.7Ω (Figures,, ) ns Rise Time t r ns TurnOff Delay Time t d(off) 43 ns Fall Time t f ns TurnOff Time t OFF ns SWITCHING SPECIFICATIONS (V GS = V) TurnOn Time t ON V DD = V, I D = 39A 9 ns V GS = V, TurnOn Delay Time t d(on) 7. ns R GS =.Ω Rise Time t r (Figures,, ) ns TurnOff Delay Time t d(off) 3 ns Fall Time t f 3 ns TurnOff Time t OFF ns GATE CHARGE SPECIFICATIONS Total Gate Charge Q g(tot) V GS = V to V V DD = V, 7 nc I D = 7A, Gate Charge at V Q g() V GS = V to V 3 37 nc I g(ref) =.ma Threshold Gate Charge Q g(th) V GS = V to V.4 nc (Figures 4, 9, ) Gate to Source Gate Charge Q gs nc Gate to Drain Miller Charge Q gd nc CAPACITANCE SPECIFICATIONS Input Capacitance C ISS = V, V GS = V, pf Output Capacitance C OSS f = MHz (Figure 3) 4 pf Reverse Transfer Capacitance C RSS pf Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage V SD I SD = 7A. V I SD = 3A. V Reverse Recovery Time t rr I SD = 7A, di SD /dt = A/µs 3 ns Reverse Recovered Charge Q RR I SD = 7A, di SD /dt = A/µs 4 nc

3 HUF733P3F Typical Performance Curves. POWER DISSIPATION MULTIPLIER I D, DRAIN CURRENT (A) 4 3 V GS = V V GS = 4.V T C, CASE TEMPERATURE ( o C) T C, CASE TEMPERATURE ( o C) FIGURE. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE Z θjc, NORMALIZED THERMAL IMPEDANCE.. DUTY CYCLE DESCENDING ORDER SINGLE PULSE 4 3 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE P DM t t NOTES: DUTY FACTOR: D = t /t PEAK T J = P DM x Z θjc x R θjc T C I DM, PEAK CURRENT (A) 3 V GS = V TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION V GS = V 4 3 t, PULSE WIDTH (s) T C = o C FOR TEMPERATURES ABOVE o C DERATE PEAK CURRENT AS FOLLOWS: I = I 7 T C FIGURE 4. PEAK CURRENT CAPABILITY 3

4 HUF733P3F Typical Performance Curves (Continued) I D, DRAIN CURRENT (A) OPERATION IN THIS AREA MAY BE LIMITED BY r DS(ON) T C = o C SINGLE PULSE T J = MAX RATED, DRAIN TO SOURCE VOLTAGE (V) µs ms ms FIGURE. FORWARD BIAS SAFE OPERATING AREA 3 I AS, AVALANCHE CURRENT (A) If R = t AV = (L)(I AS )/(.3*RATED BS V DD ) If R t AV = (L/R)ln[(I AS *R)/(.3*RATED BS V DD ) ]... t AV, TIME IN AVALANCHE (ms) NOTE: Refer to ON Semiconductor Application Notes AN93 and AN93. STARTING T J = o C STARTING T J = o C FIGURE. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY I D, DRAIN CURRENT (A) 4 PULSE DURATION = µs DUTY CYCLE =.% MAX V DD = V T J = o C T J = 7 o C T J = o C I D, DRAIN CURRENT (A) 4 V GS = V V GS = V V GS = 4V V GS = 3.V V GS = 3V PULSE DURATION = µs DUTY CYCLE =.% MAX T C = o C V GS, GATE TO SOURCE VOLTAGE (V), DRAIN TO SOURCE VOLTAGE (V) FIGURE 7. TRANSFER CHARACTERISTICS FIGURE. SATURATION CHARACTERISTICS r DS(ON), DRAIN TO SOURCE ON RESISTANCE (mω) I D = A I D = 39A I D = 7A PULSE DURATION = µs DUTY CYCLE =.% MAX T C = o C NORMALIZED DRAIN TO SOURCE ON RESISTANCE V GS = V, I D = 39A PULSE DURATION = µs DUTY CYCLE =.% MAX V GS, GATE TO SOURCE VOLTAGE (V) T J, JUNCTION TEMPERATURE ( o C) FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 4

5 HUF733P3F Typical Performance Curves (Continued) NORMALIZED GATE THRESHOLD VOLTAGE. V GS =, I D = µa T J, JUNCTION TEMPERATURE ( o C) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE....9 I D = µa 4 4 T J, JUNCTION TEMPERATURE ( o C) FIGURE. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE FIGURE. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE C, CAPACITANCE (pf) C ISS = C GS C GD C OSS C DS C GD C RSS = C GD V GS = V, f = MHz., DRAIN TO SOURCE VOLTAGE (V) FIGURE 3. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE V GS, GATE TO SOURCE VOLTAGE (V) 4 V DD = V 3 4 Q g, GATE CHARGE (nc) NOTE: Refer to ON Semiconductor Application Notes AN74 and AN7. WAVEFORMS IN DESCENDING ORDER: I D = 39A I D = 7A I D = A FIGURE 4. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT 4 V GS = 4.V, V DD = V, I D = 7A V GS = V, V DD = V, I D = 39A SWITCHING TIME (ns) 3 t r t d(off) t f SWITCHING TIME (ns) 4 3 t d(off) t f t r t d(on) 3 4 t d(on) 3 4 R GS, GATE TO SOURCE RESISTANCE (Ω) R GS, GATE TO SOURCE RESISTANCE (Ω) FIGURE. SWITCHING TIME vs GATE RESISTANCE FIGURE. SWITCHING TIME vs GATE RESISTANCE

6 HUF733P3 F Test Circuits and Waveforms BS L t P VARY t P TO OBTAIN REQUIRED PEAK I AS V GS R G V DD I AS V DD DUT V t P I AS.Ω t AV FIGURE 7. UNCLAMPED ENERGY TEST CIRCUIT FIGURE. UNCLAMPED ENERGY WAVEFORMS R L V DD Q g(tot) V GS = V V GS Q g() V DD V GS V GS = V I g(ref) DUT V GS = V Q g(th) Q gs Q gd I g(ref) FIGURE 9. GATE CHARGE TEST CIRCUIT FIGURE. GATE CHARGE WAVEFORMS t ON t d(on) t OFF t d(off) R L t r t f 9% 9% V GS V DD % % V GS R GS DUT V GS % % PULSE WIDTH 9% % FIGURE. SWITCHING TIME TEST CIRCUIT FIGURE. SWITCHING TIME WAVEFORM

7 HUF733P3F PSPICE Electrical Model.SUBCKT HUF733 3 ; rev September999 CA 3.e9 CB 4 3.e9 CIN.7e9 DBODY 7 DBODYMOD DBREAK DBREAKMOD DPLCAP DPLCAPMOD EBREAK EDS 4 EGS 3 ESG EVTHRES 9 EVTEMP IT 7 LDRAIN.e9 LGATE 9.7e9 LSOURCE 3 7.3e9 MMED MMEDMOD MSTRO MSTROMOD MWEAK MWEAKMOD RBREAK 7 RBREAKMOD RDRAIN RDRAINMOD.4e RGATE 9. RLDRAIN RLGATE 9.7 RLSOURCE RSLC RSLCMOD e RSLC e3 RSOURCE 7 RSOURCEMOD 4.e3 RVTHRES RVTHRESMOD RVTEMP 9 RVTEMPMOD SA 3 SAMOD SB 3 3 SBMOD SA 4 3 SAMOD SB SBMOD VBAT 9 DC GATE LGATE RLGATE ESG EVTEMP RGATE 9 CA SA 3 SB EGS DPLCAP RSLC EVTHRES 9 SA CIN RDRAIN MSTRO MMED 7 RBREAK 7 SB RVTEMP CB 9 IT 4 VBAT EDS RSLC ESLC DBREAK EBREAK MWEAK RSOURCE 7 RVTHRES LDRAIN RLDRAIN DBODY LSOURCE SOURCE 3 RLSOURCE DRAIN ESLC VALUE={(V(,)/ABS(V(,)))*(PWR(V(,)/(e*79),3.))}.MODEL DBODYMOD D (IS =.9e RS = 3.7e3 TRS = 9.93e4 TRS = 4.97e CJO =.3e9 TT = 7.4e M =.).MODEL DBREAKMOD D (RS = 3.e TRS =.7e 3TRS = ).MODEL DPLCAPMOD D (CJO =.97e 9IS = e3 M =.7).MODEL MMEDMOD NMOS (VTO =.73 KP =. IS = e3 N = TOX = L = u W = u RG =.).MODEL MSTROMOD NMOS (VTO =.4 KP = IS = e3 N = TOX = L = u W = u).model MWEAKMOD NMOS (VTO =. KP =. IS = e3 N = TOX = L = u W = u RG =. RS =.).MODEL RBREAKMOD RES (TC = 9.74e 4TC = 3.7e7).MODEL RDRAINMOD RES (TC = 9.7e3 TC =.9e).MODEL RSLCMOD RES (TC =.7e3 TC =.7e).MODEL RSOURCEMOD RES (TC = e3 TC = ).MODEL RVTHRESMOD RES (TC =.e3 TC =.e).model RVTEMPMOD RES (TC =.e 3TC =.e7).model SAMOD VSWITCH (RON = e ROFF =. VON =. VOFF=.).MODEL SBMOD VSWITCH (RON = e ROFF =. VON =. VOFF=.).MODEL SAMOD VSWITCH (RON = e ROFF =. VON =. VOFF=.).MODEL SBMOD VSWITCH (RON = e ROFF =. VON =. VOFF=.).ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE SubCircuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 99, written by William J. Hepp and C. Frank Wheatley. 7

8 SABER Electrical Model REV September 999 template huf733 n,n,n3 electrical n,n,n3 { var i iscl d..model dbodymod = (is =.9e, cjo =.3e9, tt = 7.4e, m =.) d..model dbreakmod = () d..model dplcapmod = (cjo =.97e9, is = e3, m =.7 ) m..model mmedmod = (type=_n, vto =.73, kp =., is = e3, tox = ) m..model mstrongmod = (type=_n, vto =.4, kp =, is = e3, tox = ) m..model mweakmod = (type=_n, vto =., kp =., is = e3, tox = ) sw_vcsp..model samod = (ron = e, roff =., von =., voff =.) sw_vcsp..model sbmod = (ron =e, roff =., von =., voff =.) sw_vcsp..model samod = (ron = e, roff =., von =., voff =.) sw_vcsp..model sbmod = (ron = e, roff =., von =., voff =.) c.ca n n = 3.e9 c.cb n n4 = 3.e9 c.cin n n =.7e9 d.dbody n7 n7 = model=dbodymod d.dbreak n7 n = model=dbreakmod d.dplcap n n = model=dplcapmod i.it n n7 = l.ldrain n n = e9 l.lgate n n9 =.7e9 l.lsource n3 n7 =.3e9 m.mmed n n n n = model=mmedmod, l=u, w=u m.mstrong n n n n = model=mstrongmod, l=u, w=u m.mweak n n n n = model=mweakmod, l=u, w=u res.rbreak n7 n =, tc = 9.74e4, tc = 3.7e7 res.rdbody n7 n = 3.7e3, tc = 9.93e4, tc = 4.97e res.rdbreak n7 n = 3.e, tc =.7e3, tc = res.rdrain n n =.4e3, tc = 9.7e3, tc =.9e res.rgate n9 n =. res.rldrain n n = res.rlgate n n9 =.7 res.rlsource n3 n7 =.3 res.rslc n n = e, tc =.7e3, tc =.7e res.rslc n n = e3 res.rsource n n7 = 4.e3, tc =.e3, tc = res.rvtemp n n9 =, tc =.e3, tc =.e7 res.rvthres n n =, tc =.e3, tc =.e spe.ebreak n n7 n7 n =.7 spe.eds n4 n n n = spe.egs n3 n n n = spe.esg n n n n = spe.evtemp n n n n = spe.evthres n n n9 n = sw_vcsp.sa n n n3 n = model=samod sw_vcsp.sb n3 n n3 n = model=sbmod sw_vcsp.sa n n n4 n3 = model=samod sw_vcsp.sb n3 n n4 n3 = model=sbmod v.vbat n n9 = dc= GATE HUF733P3F ESG equations { i (n>n) =iscl iscl: v(n,n) = ((v(n,n)/(e9abs(v(n,n))))*((abs(v(n,n)*e/79))** 3.)) } } DPLCAP RSLC RSLC ISCL RDRAIN EVTHRES 9 LGATE EVTEMP MWEAK DBODY RGATE MMED EBREAK 9 RLGATE MSTRO 7 LSOURCE CIN SOURCE 7 3 RSOURCE RLSOURCE SA SA RBREAK SB SB RVTEMP 3 CA CB 9 IT 4 VBAT EGS EDS RDBREAK 7 DBREAK RVTHRES LDRAIN RLDRAIN 7 RDBODY DRAIN

9 HUF733P3F SPICE Thermal Model th JUNCTION REV 9 September999 HUF733T CTHERM th.9e3 CTHERM.e CTHERM3 4.e CTHERM4 4 3.e3 CTHERM 3.7e CTHERM tl. RTHERM CTHERM RTHERM th 7.4e3 RTHERM.7e RTHERM e RTHERM e RTHERM 3 4.e RTHERM tl.4e RTHERM CTHERM SABER Thermal Model RTHERM3 CTHERM3 SABER thermal model HUF733T template thermal_model th tl thermal_c th, tl { ctherm.ctherm th =.9e3 ctherm.ctherm =.e ctherm.ctherm3 4 =.e ctherm.ctherm4 4 3 =.e3 ctherm.ctherm 3 =.7e ctherm.ctherm tl =. RTHERM4 4 3 CTHERM4 rtherm.rtherm th = 7.4e3 rtherm.rtherm =.7e rtherm.rtherm3 4 = 4.94e rtherm.rtherm4 4 3 =.77e rtherm.rtherm 3 = 4.e rtherm.rtherm tl =.4e } RTHERM RTHERM CTHERM CTHERM tl CASE 9

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