FDS6612A Single N-Channel, Logic-Level, PowerTrench MOSFET

Transcription

1 FDSA Single NChannel, LogicLevel, PowerTrench MOSFET General Description This NChannel Logic Level MOSFET is produced using ON Semiconductor s advanced PowerTrench process that has been especially tailored to minimize the onstate resistance and yet maintain superior switching performance. These devices are well suited for low voltage and battery powered applications where low inline power loss and fast switching are required. SO D D D D D Pin SO S S S G Absolute Maximum Ratings Features.4 A, 3 V. TA= o C unless otherwise noted Fast switching speed Low gate charge R DS(ON) = V GS = V R DS(ON) = 3 V GS = 4. V High performance trench technology for extremely low R DS(ON) High power and current handling capability Symbol Parameter Ratings Units V DSS DrainSource Voltage 3 V V GSS GateSource Voltage ± V I D Drain Current Continuous (Note a).4 A P D Pulsed 4 Power Dissipation for Single Operation (Note a). (Note b). E AS Single Pulse Avalanche Energy (Note 3) 4 mj T J, T STG Operating and Storage Junction Temperature Range to + C Thermal Characteristics R θja Thermal Resistance, JunctiontoAmbient (Note a) C/W R θja Thermal Resistance, JunctiontoAmbient (Note b) R θjc Thermal Resistance, JunctiontoCase (Note ) Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity FDSA FDSA 3 mm units W FDSA Single NChannel, LogicLevel, PowerTrench MOSFET 7 Semiconductor Components Industries, LLC. October7, Rev. 4 Publication Order Number: FDSA/D

2 Electrical Characteristics T A = C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BV DSS Drain Source Breakdown Voltage V GS = V, I D = µa 3 V BVDSS Breakdown Voltage Temperature I T J Coefficient D = µa, Referenced to C mv/ C I DSS Zero Gate Voltage Drain Current V DS = 4 V, V GS = V µa V DS = 4 V, V GS = V, T J= C µa I GSS Gate Body Leakage V GS = ± V, V DS = V ± na On Characteristics (Note ) V GS(th) Gate Threshold Voltage V DS = V GS, I D = µa.9 3 V VGS(th) T J R DS(on) Gate Threshold Voltage Temperature Coefficient Static Drain Source On Resistance I D = µa, Referenced to C V GS = V, I D =.4 A V GS = 4. V, I D = 7. A V GS= V, I D =.4 A, T J= C 4.4 mv/ C I D(on) On State Drain Current V GS = V, V DS = V A g FS Forward Transconductance V DS = V, I D =.4 A 3 S Dynamic Characteristics C iss Input Capacitance V DS = V, V GS = V, pf C oss Output Capacitance f =. MHz 4 pf C rss Reverse Transfer Capacitance mω pf R G Gate Resistance V GS = mv, f =. MHz. Ω Switching Characteristics (Note ) t d(on) Turn On Delay Time V DD = V, I D = A, 7 4 ns t r Turn On Rise Time V GS = V, R GEN = Ω ns t d(off) Turn Off Delay Time 3 ns t f Turn Off Fall Time 3 ns Q g Total Gate Charge V DS = V, I D =.4 A,.4 7. nc Q gs Gate Source Charge V GS = V.7 nc Q gd Gate Drain Charge.9 nc Drain Source Diode Characteristics and Maximum Ratings I S Maximum Continuous Drain Source Diode Forward Current. A Drain Source Diode Forward V SD V Voltage GS = V, I S =. A (Note ).77. V t rr Diode Reverse Recovery Time 9 ns I F =.4 A, d if/d t = A/µs Diode Reverse Recovery Charge 9 nc Q rr FDSA Single NChannel, LogicLevel, PowerTrench MOSFET Notes:. R θja is the sum of the junctiontocase and casetoambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R θjc is guaranteed by design while R θca is determined by the user's board design. a) C/W when mounted on a in pad of oz copper b) C/W when mounted on a minimum pad. Scale : on letter size paper Test: Pulse Width < 3µs, Duty Cycle <.% 3 Starting TJ = C, L = mh, IAS = 7A, VDD = 7V, VGS = V

3 Typical Characteristics R DS(ON), NORMALIZED DRAINSOURCE ONRESISTANCE I D, DRAIN CURRENT (A) V GS = V 4.V.V 4.V 3.V 3.V... 3 V DS, DRAIN TO SOURCE VOLTAGE (V) Figure. OnRegion Characteristics. I D =.4A V GS = V 7 T J, JUNCTION TEMPERATURE ( o C) Figure 3. OnResistance Variation with Temperature. R DS(ON), NORMALIZED DRAINSOURCE ONRESISTANCE R DS(ON), ONRESISTANCE (OHM) V GS = 3.V 4.V 4.V.V.V V 3 4 I D, DRAIN CURRENT (A) Figure. OnResistance Variation with Drain Current and Gate Voltage. T A = o C T A = o C I D = 4.A 4 V GS, GATE TO SOURCE VOLTAGE (V) Figure 4. OnResistance Variation with GatetoSource Voltage. FDSA Single NChannel, LogicLevel, PowerTrench MOSFET I D, DRAIN CURRENT (A) 4 3 V DS = V T A = o C o C o C V GS, GATE TO SOURCE VOLTAGE (V) I S, REVERSE DRAIN CURRENT (A).... V GS = V T A = o C o C o C V SD, BODY DIODE FORWARD VOLTAGE (V) Figure. Transfer Characteristics. Figure. Body Diode Forward Voltage Variation with Source Current and Temperature. 3

4 Typical Characteristics V GS, GATESOURCE VOLTAGE (V) I D, DRAIN CURRENT (A) 4. I D =.4A V DS = V V V 4 Q g, GATE CHARGE (nc) Figure 7. Gate Charge Characteristics. R DS(ON) LIMIT V GS = V SINGLE PULSE R θja = o C/W T A = o C... V DS, DRAINSOURCE VOLTAGE (V) DC s s ms ms ms µs Figure 9. Maximum Safe Operating Area. CAPACITANCE (pf) 4 I AS, AVALANCHE CURRENT (A) C rss C oss C iss f = MHz V GS = V 3 V DS, DRAIN TO SOURCE VOLTAGE (V) Figure. Capacitance Characteristics.... t AV, TIME IN AVALANCHE (ms) Figure. Unclamped Inductive Switching Capability FDSA Single NChannel, LogicLevel, PowerTrench MOSFET P(pk),PEAK TRANSIENT POWER (W) 4 3 SINGLE PULSE R θja = o C/W T A = o C... t, TIME (sec) Figure. Single Pulse Maximum Power Dissipation. 4

5 Typical Characteristics r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE.. D = SINGLE PULSE..... t, TIME (sec) Figure. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note c. Transient thermal response will change depending on the circuit board design. R θja (t) = r(t) * R θja R θja = o C/W P(pk) t t T J T A = P * R θja (t) Duty Cycle, D = t / t FDSA Single NChannel, LogicLevel, PowerTrench MOSFET

6 PSPICE Electrical Model NChannel.SUBCKT FDSA 3 *NOM TEMP= DEG C *REV A JULY 3 CA E9 CB 4 4.E CIN.E DBODY 7 DBODYMOD DBREAK DBREAKMOD DPLCAP DPLCAPMOD EBREAK EDS 4 EGS 3 ESG EVTHRES 9 EVTEMP IT 7 LGATE 9 3.4E9 LDRAIN.E9 LSOURCE 3 7 4E9 RLGATE RLDRAIN RLSOURCE MMED MMEDMOD MSTRO MSTROMOD MWEAK MWEAKMOD RBREAK 7 RBREAKMOD RDRAIN RDRAINMOD E3 RGATE 9 4. RSLC RSLCMOD E RSLC E3 RSOURCE 7 RSOURCEMOD 7.E3 RVTHRES RVTHRESMOD RVTEMP 9 RVTEMPMOD SA 3 SAMOD SB 3 3 SBMOD SA 4 3 SAMOD SB SBMOD VBAT 9 DC GATE LGATE RLGATE + EVTEMP RGATE + 9 CA ESG SA 3 SB EGS DPLCAP RSLC + EVTHRES + 9 SA SB CIN RSLC ESLC RDRAIN MSTRO MMED DBREAK EBREAK MWEAK RSOURCE 7 RBREAK 7 DBODY RVTEMP CB IT EDS VBAT + RVTHRES + 7 LDRAIN RLDRAIN LSOURCE SOURCE 3 RLSOURCE DRAIN FDSA Single NChannel, LogicLevel, PowerTrench MOSFET ESLC VALUE={(V(,)/ABS(V(,)))*(PWR(V(,)/(E*),3))}.MODEL DBODYMOD D (IS=7E RS=.E3 N=.4 TRS=.7E3 TRS=.E + CJO=3.E TT=E9 M=. IKF=.3 XTI=3.).MODEL DBREAKMOD D (RS=E TRS=.E3 TRS=.E).MODEL DPLCAPMOD D (CJO=4E IS=E3 N= M=.34).MODEL MWEAKMOD NMOS (VTO=. KP=. IS=E3 N= TOX= L=U W=U RG=4 RS=.).MODEL MMEDMOD NMOS (VTO=. KP= IS=E3 N= TOX= L=U W=U RG=4.).MODEL MSTROMOD NMOS (VTO=. KP= IS=E3 N= TOX= L=U W=U).MODEL RBREAKMOD RES (TC=.3E3 TC=E7).MODEL RDRAINMOD RES (TC=E3 TC=E).MODEL RSLCMOD RES (TC=.E3 TC=4.E).MODEL RSOURCEMOD RES (TC=.E3 TC=E).MODEL RVTHRESMOD RES (TC=.3E3 TC=7E).MODEL RVTEMPMOD RES (TC=.E3 TC=E).MODEL SAMOD VSWITCH (RON=E ROFF=. VON=4 VOFF=3).MODEL SBMOD VSWITCH (RON=E ROFF=. VON=3 VOFF=4).MODEL SAMOD VSWITCH (RON=E ROFF=. VON=.3 VOFF=.).MODEL SBMOD VSWITCH (RON=E ROFF=. VON=. VOFF=.3).ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE SubCircuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 99, written by William J. Hepp and C. Frank Wheatley.

7 SPICE Thermal Model.SUBCKT FDSA_THERM TH TL *THERMAL MODEL SUBCIRCUIT *REV A JULY 3 *MIN PAD RJA CTHERM TH. CTHERM 7. CTHERM3 7. CTHERM4.3 CTHERM 4.4 CTHERM 4 3. CTHERM7 3. CTHERM TL 3. RTHERM TH. RTHERM 7. RTHERM RTHERM4.7 RTHERM 4. RTHERM RTHERM RTHERM TL 43.7.ENDS RTHERM RTHERM RTHERM3 RTHERM4 RTHERM RTHERM RTHERM7 RTHERM th tl JUNCTION CTHERM CTHERM CTHERM3 CTHERM4 CTHERM CTHERM CTHERM7 CTHERM AMBIENT FDSA Single NChannel, LogicLevel, PowerTrench MOSFET 7

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