HRF3205, HRF3205S. Features. 100A, 55V, Ohm, N-Channel, Power MOSFETs. Symbol. Ordering Information. Packaging. Data Sheet December 2001
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1 HRF325, HRF325S Data Sheet December 2 A, 55V,. Ohm, NChannel, Power MOSFETs These are NChannel enhancement mode silicon gate power field effect transistors. They are advanced power MOSFETs designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. NOTE: Calculated continuous current based on maximum allowable junction temperature. Package limited to 75A continuous, see Figure 9. Ordering Information PART NUMBER PACKAGE BRAND HRF325 TO22AB HRF325 Features A, 55V (See Note) Low OnResistance, r DS(ON) =.Ω Temperature Compensating PSPICE Model Thermal Impedance SPICE Model UIS Rating Curve Related Literature TB334, Guidelines for Soldering Surface Mount Components to PC Boards Symbol G D S HRF325S TO263AB HRF325S NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO263AB variant in tape and reel, e.g., HRF325ST. Packaging JEDEC TO22AB JEDEC TO263AB DRAIN (FLANGE) SOURCE DRAIN GATE GATE SOURCE DRAIN (FLANGE) 2 Fairchild Semiconductor Corporation HRF325, HRF325S Rev. B
2 Absolute Maximum Ratings T C = 25 o C, Unless Othewise Specified Drain to Source Voltage (Note ) S 55 V Drain to Gate Voltage (R GS = 2kΩ) (Note ) V DGR 55 V Gate to Source Voltage V GS ±2V V Drain Current Continuous I D Pulsed Drain Current (Note 2) I DM 39 A A Pulsed Avalanche Rating E AS Figure Power Dissipation P D Derate Above 25 o C W W/ o C Operating and Storage Temperature T J, T STG 55 to 75 o C Maximum Temperature for Soldering Leads at.63in (.6mm) from Case for s T L 3 Package Body for s, See Techbrief T pkg 26 CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. T J = 25 o C to 5 o C. Electrical Specifications T C = 25 o C, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BS I D = 25µA, V GS = V 55 V Gate to Source Threshold Voltage V GS(TH) V GS =, I D = 25µA 2 4 V Zero Gate Voltage Drain Current I DSS = 55V, V GS = V 25 µa = 44V, V GS = V, T C = 5 o C 25 µa Gate to Source Leakage Current I GSS V GS = ±2V na Breakdown Voltage Temperature Coefficient HRF325, HRF325S V (BR)DSS / Reference to 25 o C, I D = 25µA.57 V T J Drain to Source On Resistance r DS(ON) I D = 59A, V GS = V (Figure 4).65. Ω TurnOn Delay Time t d(on) V DD = 2V, I D 59A, 4 ns Rise Time t r R L =.47Ω, V GS = V, R GS = 2.5Ω ns TurnOff Delay Time t d(off) 43 ns Fall Time t f 7 ns Total Gate Charge Q g V DD = 44V, I D 59A, 7 nc Gate to Source Charge Q gs V GS = V, I g(ref) = 3mA (Figure 6) 32 nc Gate to Drain Miller Charge Q gd 74 nc Input Capacitance C ISS = 25V, V GS = V, 4 pf Output Capacitance C OSS f = MHz (Figure 5) 3 pf Reverse Transfer Capacitance C RSS 4 pf Internal Source Inductance L S Measured From the Contact Screw on Tab to Center of Die Measured From the Drain Lead, 6mm (.25in) From Package to Center of Die Internal Drain Inductance L D Measured From the Source Lead, 6mm (.25in) From Header to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances D o C o C 7.5 nh 4.5 nh Thermal Resistance Junction to Case R θjc.5 o C/W G L D L S S Thermal Resistance Junction to Ambient R θja TO22 62 o C/W TO263 (PCB Mount, Steady State) 4 o C/W 2 Fairchild Semiconductor Corporation HRF325, HRF325S Rev. B
3 HRF325, HRF325S Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Continuous Source to Drain Current I SD MOSFET Symbol Showing The Integral Reverse PN Junction Diode (Note Pulsed Source to Drain Current (Note 2) I SDM 39 A G D A S Source to Drain Diode Voltage V SD I SD = 59A (Note 4).3 V Reverse Recovery Time t rr I SD = 59A, di SD /dt = A/µs (Note 4) 7 ns Reverse Recovered Charge Q RR I SD = 59A, di SD /dt = A/µs (Note 4) 45 6 nc NOTE: 2. Repetitive rating; pulse width limited by maximum junction temperature (See Figure ) Typical Performance Curves I D, DRAIN TO SOURCE CURRENT (A) V GS IN DECENDING ORDER 5V V.V 7.V 6.V 5.5V 5.V 4.5V 2µs PULSE WIDTH T C = 25 o C.., DRAIN TO SOURCE VOLTAGE (V) I D, DRAIN TO SOURCE CURRENT (A) V GS IN DECENDING ORDER 5V V.V 7.V 6.V 5.5V 5.V 4.5V 2µs PULSE WIDTH T C = 75 o C., DRAIN TO SOURCE VOLTAGE (V) FIGURE. OUTPUT CHARACTERISTICS FIGURE 2. OUTPUT CHARACTERISTICS I D, DRAIN TO SOURCE CURRENT(A) T J = 25 o C T J = 75 o C = 25V PULSE DURATION = µs DUTY CYCLE =.5% MAX V GS, GATE TO SOURCE VOLTAGE (V) NORMALIZED DRAIN TO SOURCE ON RESISTANCE 2.5 I D = 9A, V GS = V PULSE DURATION = µs 2. DUTY CYCLE =.5% MAX T J, JUNCTION TEMPERATURE ( o C) FIGURE 3. TRANSFER CHARACTERISTICS FIGURE 4. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 2 Fairchild Semiconductor Corporation HRF325, HRF325S Rev. B
4 HRF325, HRF325S Typical Performance Curves (Continued) C, CAPACITANCE (pf) V GS = V, f = MHz C ISS = C GS C GD C RSS = C GD C OSS C DS C GS C ISS C OSS C RSS, DRAIN TO SOURCE VOLTAGE (V) V GS, GATE TO SOURCE VOLTAGE (V) 2 I D = 59A = 2V 6 = V 2 = 44V Q g, GATE CHARGE (nc) FIGURE 5. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 6. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT I SD, REVERSE DRAIN CURRENT(A) PULSE DURATION = µs DUTY CYCLE =.5% MAX T J = 75 o C T J = 25 o C V SD, SOURCE TO DRAIN VOLTAGE (V) I D, DRAIN CURRENT (A) OPERATION IN THIS AREA MAY BE LIMITED BY r DS(ON) µs µs ms ms S(MAX) = 55V, DRAIN TO SOURCE VOLTAGE (V) FIGURE 7. SOURCE TO DRAIN DIODE FORWARD VOLTAGE FIGURE. FORWARD BIAS SAFE OPERATING AREA I D, DRAIN CURRENT (A) CURRENT LIMITED BY PACKAGE T C, CASE TEMPERATURE ( o C) I AS, AVALANCHE CURRENT (A). If R = t AV = (L)(I AS )/(.3*RATED BS V DD ) If R t AV = (L/R)ln[(I AS *R)/(.3*RATED BS V DD ) ] STARTING T J = 5 o C STARTING T J = 25 o C. t AV, TIME IN AVALANCHE (ms) FIGURE 9. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE FIGURE. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 2 Fairchild Semiconductor Corporation HRF325, HRF325S Rev. B
5 HRF325, HRF325S Typical Performance Curves (Continued) Z θjc, NORMALIZED THERMAL IMPEDANCE. DUTY CYCLE DESCENDING ORDER P DM t t 2 NOTES: DUTY FACTOR: D = t /t 2. SINGLE PULSE PEAK T J = P DM x Z θjc x R θjc T C t, RECTANGULAR PULSE DURATION (s) FIGURE. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE Test Circuits and Waveforms BS L t P VARY t P TO OBTAIN REQUIRED PEAK I AS V GS R G V DD I AS V DD DUT V t P I AS.Ω t AV FIGURE 2. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 3. UNCLAMPED ENERGY WAVEFORMS V DD R L Q gd Q g(tot) V GS Q gs V GS V DD I G(REF) DUT I G(REF) FIGURE 4. GATE CHARGE TEST CIRCUIT FIGURE 5. GATE CHARGE WAVEFORM 2 Fairchild Semiconductor Corporation HRF325, HRF325S Rev. B
6 HRF325, HRF325S Test Circuits and Waveforms (Continued) t ON t d(on) t OFF t d(off) R L t r t f 9% 9% V GS V DD % % V GS R GS DUT V GS % 5% PULSE WIDTH 9% 5% FIGURE 6. SWITCHING TIME TEST CIRCUIT FIGURE 7. RESISTIVE SWITCHING WAVEFORMS 2 Fairchild Semiconductor Corporation HRF325, HRF325S Rev. B
7 HRF325, HRF325S PSPICE Electrical Model SUBCKT HRF325P3 2 3 ; rev 7/25/97 CA 2 4.9e9 CB e9 CIN e9 DBODY 7 5 DBODYMOD DBREAK 5 DBREAKMOD DPLCAP 5 DPLCAPMOD EBREAK EDS 4 5 EGS 3 6 ESG 6 6 EVTHRES EVTEMP IT 7 GATE LDRAIN 2 5 e9 LGATE 9 2.6e9 LSOURCE 3 7.e9 K LGATE LSOURCE.5 MMED 6 6 MMEDMOD MSTRO 6 6 MSTROMOD MWEAK 6 2 MWEAKMOD LGATE RLGATE RBREAK 7 RBREAKMOD RDRAIN 5 6 RDRAINMOD 3.5e4 RGATE RLDRAIN 2 5 RLGATE 9 26 RLSOURCE 3 7 RSLC 5 5 RSLCMOD e6 RSLC2 5 5 e3 RSOURCE 7 RSOURCEMOD 4.5e3 RVTHRES 22 RVTHRESMOD RVTEMP 9 RVTEMPMOD CA ESG SB EGS 6 EVTEMP RGATE SA S2A DPLCAP RSLC EVTHRES S2B CIN 5 5 RSLC 5 5 ESLC RDRAIN MMED MSTRO DBREAK EBREAK MWEAK 7 RSOURCE RBREAK 7 DBODY RVTEMP CB 9 IT 4 5 VBAT EDS 22 RVTHRES 7 LDRAIN RLDRAIN LSOURCE SOURCE 3 RLSOURCE DRAIN 2 SA SAMOD SB SBMOD S2A S2AMOD S2B S2BMOD VBAT 22 9 DC ESLC 5 5 VALUE={(V(5,5)/ABS(V(5,5)))*(PWR(V(5,5)/(e6*55),3))}.MODEL DBODYMOD D (IS = 4.25e2 RS =.e3 TRS = 2.75e3 TRS2 = 5e6 CJO = 5.95e9 TT = 4e7 M =.55).MODEL DBREAKMOD D (RS =. 6IKF = 3 TRS = 3e 3TRS2 = 3e6).MODEL DPLCAPMOD D (CJO = 4.45e 9IS = e3 N = M =. VJ =.45).MODEL MMEDMOD NMOS (VTO = 2.93 KP = 9.5 IS = e3 N = TOX = L = u W = u RG = ).MODEL MSTROMOD NMOS (VTO = 3.23 KP = 5 IS = e3 N = TOX = L = u W = u).model MWEAKMOD NMOS (VTO = 2.35 KP =.2 IS = e3 N = TOX = L = u W = u RG = ).MODEL RBREAKMOD RES (TC = e 4TC2 = 4e6).MODEL RDRAINMOD RES (TC = e2 TC2 = 5e6).MODEL RSLCMOD RES (TC = e4 TC2 =.5e6).MODEL RSOURCEMOD RES (TC = e4 TC2 =.5e5).MODEL RVTHRESMOD RES (TC = 2.3e3 TC2 =.2e5).MODEL RVTEMPMOD RES (TC = 2.2e 3TC2 = 7e6).MODEL SAMOD VSWITCH (RON = e5 ROFF =. VON = 9 VOFF= 4).MODEL SBMOD VSWITCH (RON = e5 ROFF =. VON = 4 VOFF= 9).MODEL S2AMOD VSWITCH (RON = e5 ROFF =. VON = VOFF= 2.5).MODEL S2BMOD VSWITCH (RON = e5 ROFF =. VON = 2.5 VOFF= ).ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE SubCircuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 99, written by William J. Hepp and C. Frank Wheatley. 2 Fairchild Semiconductor Corporation HRF325, HRF325S Rev. B
8 HRF325, HRF325S SPICE Thermal Model 7 JUNCTION REV 25 July 97 HRF325 CTHERM e5 CTHERM e3 CTHERM e3 CTHERM e2 CTHERM e CTHERM e RTHERM 6 CTHERM RTHERM e4 RTHERM e3 RTHERM e2 RTHERM e RTHERM e RTHERM e RTHERM2 5 CTHERM2 RTHERM3 CTHERM3 4 RTHERM4 CTHERM4 3 RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 CASE 2 Fairchild Semiconductor Corporation HRF325, HRF325S Rev. B
9 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx Bottomless CoolFET CROSSVOLT DenseTrench DOME EcoSPARK E 2 CMOS TM EnSigna TM FACT FACT Quiet Series STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms FAST FASTr FRFET GlobalOptoisolator GTO HiSeC ISOPLANAR LittleFET MicroFET MicroPak MICROWIRE OPTOLOGIC OPTOPLANAR PACMAN POP Power247 PowerTrench QFET QS QT Optoelectronics Quiet Series SILENT SWITCHER SMART START STAR*POWER Stealth SuperSOT 3 SuperSOT 6 SuperSOT SyncFET TinyLogic TruTranslation UHC UltraFET 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Datasheet Identification Product Status Definition VCX Advance Information Preliminary No Identification Needed Formative or In Design First Production Full Production This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4
10 This datasheet has been download from: Datasheets for electronics components.
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FQP70N10 FQP70N10 100V N-Channel MOSFET August 2000 QFET TM General Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild s proprietary, planar stripe,
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FQP4N80 FQP4N80 800V N-Channel MOSFET September 000 QFET TM General Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild s proprietary, planar stripe,
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500V N-Channel MOSFET General Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild s proprietary, planar, DMOS technology. This advanced technology has
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FQPF7N60 FQPF7N60 600V N-Channel MOSFET April 2000 QFET TM General Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild s proprietary, planar stripe,
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100V LOGIC N-Channel MOSFET General Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild s proprietary, planar stripe, DMOS technology. This advanced
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250V P-Channel MOSFET April 2000 QFET TM General Description These P-Channel enhancement mode power field effect transistors are produced using Fairchild s proprietary, planar stripe, DMOS technology.
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FQA24N60 FQA24N60 600V N-Channel MOSFET April 2000 QFET TM General Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild s proprietary, planar stripe,
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