Device Marking Device Package Reel Size Tape Width Quantity FDB045AN08A0 FDB045AN08A0 D 2 -PAK 330 mm 24 mm 800 units

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1 FDB4ANA NChannel PowerTrench MOSFET 7 V, A, 4. mω Features R DS(on) = 3.9 mω ( V GS = V, I D = A Q G(tot) = 92 nc ( V GS = V Low Miller Charge Low Q rr Body Diode UIS Capability (Single Pulse and Repetitive Pulse) Formerly developmental type 24 D Applications Synchronous Rectification for ATX / Server / Telecom PSU Battery Protection Circuit Motor drives and Uninterruptible Power Supplies D FDB4ANA NChannel PowerTrench MOSFET G S D 2 PAK G MOSFET Maximum Ratings T C = 2 C unless otherwise noted Symbol Parameter FDB4ANA Units V DSS Drain to Source Voltage 7 V V GS Gate to Source Voltage ±2 V Drain Current I D Continuous (T C < 37 o C, V GS = V) 9 A Continuous (T amb = 2 o C, V GS = V, with R θja = 43 o C/W) 9 A Pulsed Figure 4 A E AS Single Pulse Avalanche Energy (Note ) mj Power dissipation 3 W P D Derate above 2 o C 2. W/ o C T J, T STG Operating and Storage Temperature to 7 o C Thermal Characteristics R θjc Thermal Resistance Junction to Case.4 o C/W R θja Thermal Resistance Junction to Ambient (Note 2) 2 o C/W R θja Thermal Resistance Junction to Ambient, in 2 copper pad area 43 o C/W S 22 Semiconductor Components Industries, LLC. October27, Rev. 3 Publication Order Number: FDB4ANA/D

2 Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity FDB4ANA FDB4ANA D 2 PAK 33 mm 24 mm units Electrical Characteristics T C = 2 C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics B VDSS Drain to Source Breakdown Voltage I D = 2μA, V GS = V 7 V I DSS Zero Gate Voltage Drain Current V DS = V V GS = V T C = o C 2 I GSS Gate to Source Leakage Current V GS = ±2V ± na On Characteristics V GS(TH) Gate to Source Threshold Voltage V GS = V DS, I D = 2μA 2 4 V r DS(ON) Drain to Source On Resistance Dynamic Characteristics I D = A, V GS = V.39.4 I D = 37A, V GS = V..4 I D = A, V GS = V, T J = 7 o C.. C ISS Input Capacitance pf V DS = 2V, V GS = V, C OSS Output Capacitance pf f = MHz C RSS Reverse Transfer Capacitance 24 pf Q g(tot) Total Gate Charge at V V GS = V to V Q g(th) Threshold Gate Charge V GS = V to 2V V DD = 4V 7 nc Q gs Gate to Source Gate Charge I D = A 27 nc Q gs2 Gate Charge Threshold to Plateau I g =.ma nc μa Ω 92 3 nc Q gd Gate to Drain Miller Charge 2 nc FDB4ANA NChannel PowerTrench MOSFET Switching Characteristics (V GS = V) t ON TurnOn Time ns t d(on) TurnOn Delay Time ns t r Rise Time V DD = 4V, I D = A ns t d(off) TurnOff Delay Time V GS = V, R GS = 3.3Ω 4 ns t f Fall Time 4 ns t OFF TurnOff Time 2 ns DrainSource Diode Characteristics V SD Source to Drain Diode Voltage I SD = A.2 V I SD = 4A. V t rr Reverse Recovery Time I SD = 7A, di SD /dt = A/μs 3 ns Q RR Reverse Recovered Charge I SD = 7A, di SD /dt = A/μs 4 nc Notes: : Starting T J = 2 C, L =.4mH, I AS = A. 2: Pulse Width = s 2

3 Typical Characteristics T C = 2 C unless otherwise noted POWER DISSIPATION MULTIPLIER Z θjc, NORMALIZED Figure. THERMAL IMPEDANCE 2. T C, CASE TEMPERATURE ( o C) Normalized Power Dissipation vs Ambient Temperature DUTY CYCLE DESCENDING ORDER I D, DRAIN CURRENT (A) Figure 2. CURRENT LIMITED BY PACKAGE T C, CASE TEMPERATURE ( o C) Maximum Continuous Drain Current vs Case Temperature NOTES: DUTY FACTOR: D = t /t 2 SINGLE PULSE PEAK T J = P DM x Z θjc x R θjc T C t, RECTANGULAR PULSE DURATION (s) P DM t t 2 FDB4ANA NChannel PowerTrench MOSFET Figure 3. Normalized Maximum Transient Thermal Impedance I DM, PEAK CURRENT (A) 2 V GS = V TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION T C = 2 o C FOR TEMPERATURES ABOVE 2 o C DERATE PEAK CURRENT AS FOLLOWS: I = 7 T C t, PULSE WIDTH (s) Figure 4. Peak Current Capability 3

4 Typical Characteristics T C = 2 C unless otherwise noted I D, DRAIN CURRENT (A) I D, DRAIN CURRENT (A) 2.. V DS, DRAIN TO SOURCE VOLTAGE (V) Figure OPERATION IN THI AREA MAY BE LIMITED BY r DS(ON) SINGLE PULSE T J = MAX RATED T C = 2 o C DC μs μs ms ms Forward Bias Safe Operating Area PULSE DURATION = μs DUTY CYCLE =.% MAX V DD = V T J = 7 o C T J = 2 o C T J = o C V GS, GATE TO SOURCE VOLTAGE (V) I AS, AVALANCHE CURRENT (A) If R = t AV = (L)(I AS )/(.3*RATED BV DSS V DD ) If R t AV = (L/R)ln[(I AS *R)/(.3*RATED BV DSS V DD ) ].. t AV, TIME IN AVALANCHE (ms) NOTE: Refer to ON Semiconductor Application Notes AN74 and AN7 I D, DRAIN CURRENT (A) Figure. 2 9 STARTING T J = o C STARTING T J = 2 o C Unclamped Inductive Switching Capability V GS = V V GS = V V GS = 7V V GS = V 3 T C = 2 o C PULSE DURATION = μs DUTY CYCLE =.% MAX... V DS, DRAIN TO SOURCE VOLTAGE (V) FDB4ANA NChannel PowerTrench MOSFET Figure 7. Transfer Characteristics Figure. Saturation Characteristics DRAIN TO SOURCE ON RESISTANCE(mΩ) PULSE DURATION = μs DUTY CYCLE =.% MAX V GS = V V GS = V 2 4 I D, DRAIN CURRENT (A) NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = μs DUTY CYCLE =.% MAX V GS = V, I D =A T J, JUNCTION TEMPERATURE ( o C) Figure 9. Drain to Source On Resistance vs Drain Current Figure. Normalized Drain to Source On Resistance vs Junction Temperature 4

5 Typical Characteristics T C = 2 C unless otherwise noted NORMALIZED GATE THRESHOLD VOLTAGE T J, JUNCTION TEMPERATURE ( o C) Figure. C, CAPACITANCE (pf) V GS = V DS, I D = 2μA Normalized Gate Threshold Voltage vs Junction Temperature C OSS C DS C GD C RSS = C GD C ISS = C GS C GD V GS = V, f = MHz. 7 V DS, DRAIN TO SOURCE VOLTAGE (V) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE V GS, GATE TO SOURCE VOLTAGE (V) I D = 2μA T J, JUNCTION TEMPERATURE ( o C) Figure 2. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 4 2 V DD = 4V 2 7 Q g, GATE CHARGE (nc) WAVEFORMS IN DESCENDING ORDER: I D = A I D = A FDB4ANA NChannel PowerTrench MOSFET Figure 3. Capacitance vs Drain to Source Voltage Figure 4. Gate Charge Waveforms for Constant Gate Currents

6 Test Circuits and Waveforms V DS L VARY t P TO OBTAIN REQUIRED PEAK I AS R G V DD V GS DUT t P V I AS.Ω Figure. Unclamped Energy Test Circuit V DS L V GS V DD BV DSS t P V DS I AS V DD t AV Figure. Unclamped Energy Waveforms V DD Q g(tot) V DS V GS V GS = V Q gs2 FDB4ANA NChannel PowerTrench MOSFET I g(ref) DUT V GS = 2V Q g(th) Q gs Qgd Figure 7. Gate Charge Test Circuit I g(ref) Figure. Gate Charge Waveforms V DS t ON t OFF t d(on) t d(off) R L t r t f V DS 9% 9% V GS V DD % % R GS DUT 9% V GS V GS % % PULSE WIDTH % Figure 9. Switching Time Test Circuit Figure 2. Switching Time Waveforms

7 Thermal Resistance vs. Mounting Pad Area The maximum rated junction temperature, T JM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, P DM, in an application. Therefore the application s ambient temperature, T A ( o C), and thermal resistance R θja ( o C/W) must be reviewed to ensure that T JM is never exceeded. Equation mathematically represents the relationship and serves as the basis for establishing the rating of the part. ( T T ) JM A P DM = R θ JA In using surface mount devices such as the TO23 package, the environment in which it is applied will have a significant influence on the part s current and maximum power dissipation ratings. Precise determination of P DM is complex and influenced by many factors:. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias.. Air flow and board orientation. (EQ. ). For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. ON Semiconductor provides thermal information to assist the designer s preliminary application evaluation. Figure 2 defines the R θja for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR4 board with oz copper after seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the ON Semiconductor device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 2 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. R θja ( o C/W) 4 2. R θja = /(.22Area) EQ.2 R θja = 2. 2/(.9Area) EQ.3 (.4) (.4) (4.) AREA, TOP COPPER AREA in 2 (cm 2 ) Figure 2. Thermal Resistance vs Mounting Pad Area FDB4ANA NChannel PowerTrench MOSFET R θja 2. ( 9. 4 =.22 Area) R θja 2. 2 = (.9 Area ) (EQ. 2) Area in Inches Squared (EQ. 3) Area in Centimeters Squared 7

8 PSPICE Electrical Model.SUBCKT FDB4ANA 2 3 ; CA 2.e9 CB 4.e9 CIN.4e9 DBODY 7 DBODYMOD DBREAK DBREAKMOD DPLCAP DPLCAPMOD EBREAK EDS 4 EGS 3 ESG EVTHRES 2 9 EVTEMP 2 22 IT 7 LDRAIN 2 e9 LGATE 9 4.e9 LSOURCE e9 MMED MMEDMOD MSTRO MSTROMOD MWEAK 2 MWEAKMOD GATE RBREAK 7 RBREAKMOD RDRAIN RDRAINMOD 9e4 RGATE RLDRAIN 2 RLGATE 9 4. RLSOURCE RSLC RSLCMOD e RSLC2 e3 RSOURCE 7 RSOURCEMOD 2.3e3 RVTHRES 22 RVTHRESMOD RVTEMP 9 RVTEMPMOD rev March 22 LDRAIN DPLCAP DRAIN 2 RSLC RLDRAIN DBREAK RSLC2 ESLC 7 RDRAIN DBODY ESG EBREAK EVTHRES 9 2 LGATE EVTEMP MWEAK RGATE 22 MMED 9 2 RLGATE MSTRO CIN LSOURCE SOURCE 7 3 RSOURCE RLSOURCE SA S2A 2 RBREAK SB S2B RVTEMP CA 3 CB 9 4 IT EGS VBAT EDS 22 RVTHRES FDB4ANA NChannel PowerTrench MOSFET SA 2 3 SAMOD SB SBMOD S2A 4 3 S2AMOD S2B S2BMOD VBAT 22 9 DC ESLC VALUE={(V(,)/ABS(V(,)))*(PWR(V(,)/(e*2),))}.MODEL DBODYMOD D (IS = 2.4e N =.4 RS =.7e3 TRS = 2.7e3 TRS2 = 2e7 XTI=3.9 CJO = 4.3e9 TT = e M =.4e).MODEL DBREAKMOD D (RS =.e TRS = e3 TRS2 =.9e).MODEL DPLCAPMOD D (CJO =.3e9 IS = e3 N = M =.3).MODEL MMEDMOD NMOS (VTO = 3.7 KP = 9 IS =e3 N = TOX = L = u W = u RG =.3).MODEL MSTROMOD NMOS (VTO = 4.4 KP = 2 IS = e3 N = TOX = L = u W = u).model MWEAKMOD NMOS (VTO = 3. KP =.3 IS = e3 N = TOX = L = u W = u RG =.3e RS =.).MODEL RBREAKMOD RES (TC =.e3 TC2 = 9e7).MODEL RDRAINMOD RES (TC =.9e2 TC2 = 4e).MODEL RSLCMOD RES (TC =.3e3 TC2 = e).model RSOURCEMOD RES (TC = e3 TC2 = e).model RVTHRESMOD RES (TC = e3 TC2 =.9e).MODEL RVTEMPMOD RES (TC = 2.4e3 TC2 = e).model SAMOD VSWITCH (RON = e ROFF =. VON = 4. VOFF=.).MODEL SBMOD VSWITCH (RON = e ROFF =. VON =. VOFF= 4.).MODEL S2AMOD VSWITCH (RON = e ROFF =. VON =. VOFF=.).MODEL S2BMOD VSWITCH (RON = e ROFF =. VON =. VOFF=.).ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE SubCircuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 99, written by William J. Hepp and C. Frank Wheatley.

9 SABER Electrical Model REV March 22 template FDB4ANA n2,n,n3 electrical n2,n,n3 { var i iscl dp..model dbodymod = (isl = 2.4e, n =.4, rs =.7e3, trs = 2.7e3, trs2 = 2e7, xti = 3.9, cjo = 4.3e9, tt = e, m =.4e) dp..model dbreakmod = (rs =.e, trs = e3, trs2 =.9e) dp..model dplcapmod = (cjo =.3e9, isl =e3, nl =, m =.3) m..model mmedmod = (type=_n, vto = 3.7, kp = 9, is =e3, tox=) m..model mstrongmod = (type=_n, vto = 4.4, kp = 2, is = e3, tox = ) m..model mweakmod = (type=_n, vto = 3., kp =.3, is = e3, tox =, rs=.) sw_vcsp..model samod = (ron = e, roff =., von = 4., voff =.) sw_vcsp..model sbmod = (ron =e, roff =., von =., voff = 4.) sw_vcsp..model s2amod = (ron = e, roff =., von =., voff =.) sw_vcsp..model s2bmod = (ron = e, roff =., von =., voff =.) LDRAIN c.ca n2 n =.e9 c.cb n n4 =.e9 c.cin n n =.4e9 dp.dbody n7 n = model=dbodymod dp.dbreak n n = model=dbreakmod dp.dplcap n n = model=dplcapmod i.it n n7 = l.ldrain n2 n = e9 l.lgate n n9 = 4.e9 l.lsource n3 n7 = 4.3e9 GATE LGATE RLGATE EVTEMP RGATE m.mmed n n n n = model=mmedmod, l=u, w=u m.mstrong n n n n = model=mstrongmod, l=u, w=u m.mweak n n2 n n = model=mweakmod, l=u, w=u res.rbreak n7 n =, tc =.e3, tc2 = 9e7 res.rdrain n n = 9e4, tc =.9e2, tc2 = 4e res.rgate n9 n2 =.3 res.rldrain n2 n = res.rlgate n n9 = 4. res.rlsource n3 n7 = 4.3 res.rslc n n= e, tc = e3, tc2 =e res.rslc2 n n = e3 res.rsource n n7 = 2.3e3, tc = e3, tc2 =e res.rvtemp n n9 =, tc = 2.4e3, tc2 = e res.rvthres n22 n =, tc = e3, tc2 =.9e ESG DPLCAP RSLC2 RSLC ISCL RDRAIN EVTHRES 9 2 DBREAK MWEAK DBODY MMED EBREAK CIN MSTRO 7 LSOURCE SOURCE 7 3 RSOURCE RLSOURCE SA S2A 2 RBREAK SB S2B RVTEMP CA 3 CB 9 4 IT EGS VBAT EDS 22 RVTHRES RLDRAIN DRAIN 2 FDB4ANA NChannel PowerTrench MOSFET spe.ebreak n n7 n7 n = 2.3 spe.eds n4 n n n = spe.egs n3 n n n = spe.esg n n n n = spe.evtemp n2 n n n22 = spe.evthres n n2 n9 n = sw_vcsp.sa n n2 n3 n = model=samod sw_vcsp.sb n3 n2 n3 n = model=sbmod sw_vcsp.s2a n n n4 n3 = model=s2amod sw_vcsp.s2b n3 n n4 n3 = model=s2bmod v.vbat n22 n9 = dc= equations { i (n>n) =iscl iscl: v(n,n) = ((v(n,n)/(e9abs(v(n,n))))*((abs(v(n,n)*e/2))** )) } } 9

10 SPICE Thermal Model REV 23 March 22 FDB4ANAT CTHERM th.4e3 CTHERM2 3e2 CTHERM3 4.4e2 CTHERM4 4 3.e2 CTHERM e2 CTHERM 2 tl e RTHERM th 3.24e3 RTHERM2.e3 RTHERM e2 RTHERM4 4 3 e RTHERM 3 2.e RTHERM 2 tl.4e SABER Thermal Model SABER thermal model FDB4ANAT template thermal_model th tl thermal_c th, tl { ctherm.ctherm th =.4e3 ctherm.ctherm2 = 3e2 ctherm.ctherm3 4 =.4e2 ctherm.ctherm4 4 3 =.e2 ctherm.ctherm 3 2 = 4.e2 ctherm.ctherm 2 tl = e rtherm.rtherm th = 3.24e3 rtherm.rtherm2 =.e3 rtherm.rtherm3 4 = 2.2e2 rtherm.rtherm4 4 3 = e rtherm.rtherm 3 2 =.e rtherm.rtherm 2 tl =.4e } RTHERM RTHERM2 RTHERM3 RTHERM4 RTHERM th 4 3 JUNCTION CTHERM CTHERM2 CTHERM3 CTHERM4 CTHERM FDB4ANA NChannel PowerTrench MOSFET 2 RTHERM CTHERM tl CASE

11 Mechanical Dimensions TO23 2L (D 2 PAK) FDB4ANA NChannel PowerTrench MOSFET Figure 22. 2LD, TO23, Surface Mount Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a ON Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor s worldwide terms and conditions, specifically the warranty therein, which covers ON Semiconductor products. Dimension in Millimeters

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