Substrate Noise Isolation Improvement by Helium-3 Ion Irradiation Technique in a Triple-well CMOS Process

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Clementine Underwood
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Pang 1, Rui Wu 1, Kenichi Okada 1, Hitoshi Sakane 2, and Akira Matsuzawa 1 1

1 Substrate Noise Isolation Improvement by Helium-3 Ion Irradiation Technique in a Triple-well CMOS Process Ning Li 1, Takeshi Inoue 2, Takuichi Hirano 1, Jian Pang 1, Rui Wu 1, Kenichi Okada 1, Hitoshi Sakane 2, and Akira Matsuzawa 1 1 Tokyo Institute of Technology 2 S.H.I. Examination & Inspection, Ltd ESSDERC 2015

2 Outline Background Methods to improve isolation Helium-3 ion irradiation Simulation results Experimental results Conclusion Slide 1

3 Background Analog and digital circuits are integrated on the same chip. Increase of digital circuit speed causes more substrate noise coupling problems. Analog circuit supply voltage decreases. Slide 2

4 Methods to Improve Isolation Decreasing noise injection and noise reception uard rings Cutting the propagation path Silicon on insulator (SOI) High cost Proton bombardment High cost Helium-3 ion irradiation Noise injection Digital circuit Digital circuit Noise injection High resistive High resistive Noise propagation Top view Rsub,high»Rsub,low Csub Cross view Noise reception Analog circuit Analog circuit Noise reception Low Resistive Si Substrate Slide 3

5 Helium-3 Ion Irradiation Cutting the propagation path by increasing the substrate resistivity Can be integrated into the standard process The design margin is about 15-mm for active device [1]. Helium-3 Ion Beam from a cyclotron Aggressor circuit High resistive Al mask Victim circuit Low Resistive Si Substrate Helium-3 high irradiation efficiency small dose low process cost Helium-3 bombardment from front side to create a high resistive Ref: [1] Ning Li, et al., TED, vol. 62, no. 4, April Slide 4

Helium-3 Ion Irradiation Machine (a) (b) (f) (g) (h) (i) (c) (d) (j) (e) Configuration of Irradiation System Ion irradiation machine (a), (b): Vertical/horizontal scanning magnets (c),

6 Helium-3 Ion Irradiation Machine (a) (b) (f) (g) (h) (i) (c) (d) (j) (e) Configuration of Irradiation System Ion irradiation machine (a), (b): Vertical/horizontal scanning magnets (c), (d), (e): Turbomolecular pumps (f): Beam shutter (g), (h): wafer gate valves (i): Wafer (j): Automatic wafer handling device Ref: Slide 5

7 Quality Factor Helium-3 Ion Irradiation Applications For inductor Improving inductor quality factor For voltage controlled oscillator 8.5dB improvement in phase noise nH Inductor Irradiated area 270mm Non-irradiation w/ irradiation Frequency [Hz] Voltage controlled oscillator Ref.: Ning Li, et al., TED, vol. 62, no. 4, April Slide 6

8 Resistivity (Ω cm) Substrate Resistivity Resistivity after helium-3 ion irradiation Dose : 2x10 13 cm -2 Non-irradiation w/ irradiation mm Si surface 140mm Depth (μm) Slide 7

9 Resistivity (Ω cm) Substrate Resistivity Cont d Resistivity after annealing at 200ºC and 400ºC for 1h Dose : 2x10 13 cm -2 Non-Annealing 200 1h 400 1h Non-irradiation Si surface 40mm 140mm Depth (μm) Slide 8

10 Isolation Test (a) diffusion taps (b) diffusion tap with guard ring at one side Port1 N+/P+ High resistive Low Resistive Si Substrate Port1 ND N+/P+ High resistive Low Resistive Si Substrate Port2 N+/P+ N+/P+ P+/N+ R Port2 (c) diffusion tap with deep n-well (DNW) guard ring (R) at one side Port1 N+/P+ High resistive ND Low Resistive Si Substrate Port2 N+/P+ Deep N-well Slide 9

50μm Thickness 65μm 130μm P-diffusion 35x70mm 2 130mm 50mm

11 EM Simulation EM simulator HFSS Two-port P-diff. taps Area: 35x70μm 2 Distance: 100μm High resistive Width: 50μm Thickness 65μm 130μm P-diffusion 35x70mm 2 130mm 50mm 100mm Top view 100mm 65mm, 130mm High resistive Cross view Slide 10

12 Simulation Results A 10-dB improvement at 2Hz As frequency increases, the improvement decreases due to the capacitive coupling S 21 (db) Before helium-3 ion irradiation 65-mm thickness 130-mm thickness 10 db improvement Frequency (Hz) Slide 11

13 Test Patterns M1 S W 3 He 2+ irrad. D Top Metal W: diffusion width L: diffusion length D: diffusion taps distance L Top view of test structures S Size (W*L) (mm 2 ) Diff. uard Ring (R) Dist. (mm) 1 35*140 N+ None *140 N+ None *140 N+ None *70 N+ None *35 N+ None *140 N+ P+ R *140 N+ P+ R and DNW *140 P+ None *140 P+ N+ R *140 P+ N+ R and DNW DNW: deep n-well 100 Slide 12

14 Chip Photo A 180-nm standard CMOS process Substrate resistivity about 3~4 Ω cm Chip photo Chip photo Mask Slide 13

15 Measurement Results (1) Measured noise isolation with respect to tap distance Increasing D from 100μm to 150μm improves noise isolation 5dB, from 150μm to 200μm of 3dB at 10Hz Increasing D will increase chip area. S 21 (db) Frequency (Hz) D=100 D=150 D=200 M1 S W 3 He 2+ irrad. D Top Metal L S Slide 14

16 Measurement Results (2) Measured noise isolation with respect to tap size Large diffusion area causes more coupling. -20 S 21 (db) W=35, L=140 W=35, L=70 W=35, L= Frequency (Hz) M1 S W 3 He 2+ irrad. D Top Metal L S Slide 15

17 Measurement Results (3) Isolation is maintained after annealing at 200ºC for 1 hour TE 7 uard Ring (R) P+ R and DNW S 21 (db) Frequency (Hz) Non-irradiation w/ irradiation w/ annealing M1 S W 3 He 2+ irrad. D Top Metal L S Slide 16

18 Measurement Results (4) Isolation is improved for all test patterns after helium-3 ion irradiation. A 10-dB improvement (90% noise reduction) is achieved for patters with R. S 21 (db)@2hz Non-irradiation w/ irradiation Test structrue number M1 S W Dist. (mm) Size (W*L) (mm 2 ) 1 35* * *35 3 He 2+ irrad. D Top Metal L S uard Ring (R) None P+ R P+ R and DNW None N+ R N+ R and DNW Slide 17

19 Conclusions Helium-3 bombardment is proposed to create a local semi-insulated substrate of high resistibility. Noise isolation is improved about 10dB at 2Hz after helium-3 ion irradiation. A 90% noise reduction has been achieved for test structures with guard rings. The noise isolation can be kept even after annealing at 200ºC for 1 hour. Slide 18

20 Acknowledgements This work was partially supported by MIC, SCOPE, and VDEC in collaboration with Cadence Design Systems, Inc., and Mentor raphics, Inc. Slide 19

21 Thank you for your attention Slide 20

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