IMPACCT: Methodology and Tools for Power-Aware Embedded Systems

Transcription

1 IMPCCT: Methodolog nd Tools for Power-wre Emedded Sstems Pi H. Chou, Jinfeng Liu, Dein Li, Nder Bgherzdeh, Deprtment of Eletril & Computer Engineering Universit of Cliforni, Irvine, C US {hou,jinfengl,dli,nder}@ee.ui.edu strt Power-wre sstems re those tht must eploit wide rnge of power/performne trdeoffs in order to dpt to the power vililit nd pplition requirements. The require the integrtion of mn novel power mngement tehniques, rnging from voltge sling to susstem shutdown. However, those tehniques do not lws ompose snergistill with eh other; in ft, the n omine sutrtivel nd often ield ounterintuitive, nd sometimes inorret, results in the ontet of omplete sstem. This n eome serious prolem s more of these power wre sstems re eing deploed in mission ritil pplitions. To ddress the prolem of tehnique integrtion for power-wre emedded sstems, we propose new design tool frmework lled IMPCCT nd the ssoited design methodolog. The sstem modeling methodolog inludes pplition model for pturing timing/power onstrints nd their mode dependen t the sstem level. The tool performs power-wre sheduling nd mode seletion to ensure tht ll timing/power onstrints re stisfied nd tht ll overhed is tken into ount. IMPCCT then snthesizes the implementtion trgeting smmetri multiproessor pltform. Eperimentl results show tht the inresed dnmi rnge of power/performne settings enled Mrs rover to hieve signifint elertion while using less energ. More importntl, our tool orretl omines the stte-of-the-rt tehniques t the sstem level, there sving even eperiened designers from mn pitflls of sstem-level power mngement. Introdution Reent ers hve seen the emergene of power-wre emedded sstems. The re hrterized not onl low power onsumption, ut more generll their ilit to support wide rnge of power/performne trdeoffs. These sstems n e viewed s providing knos tht n e turned one diretion to redue power onsumption or the other diretion to inrese performne. The ilit to mimize the rnge of power-performne trdeoffs is driven new pplitions tht demnd ver high performne while operting under stringent timing nd power onstrints. One suh pplition n e found in the spe domin in the form of rover. Let us onsider the Mrs Pthfinder rover from NS/JPL []. It ws designed to rom on Mrs to tke digitl photogrphs nd perform sientifi eperiments over severl hundred ds. Its energ soures onsist of tter pk nd solr pnel, nd future versions re epeted to inorporte nuler genertor or other energ svenging devies. The initil version ws designed to e low-power, nd this ws omplished serilizing ll tsks, inluding mehnil nd heting s well s omputtion. However, low-power lso mens low performne in this se, s the rover ould move t most m per minute, nd shoot nd wirelessl trnsmit t most three highresolution photos in d. Even though during dtime the solr pnel ould output more power thn ould e onsumed the rover, the rover ws unle to tke dvntge of this power; insted, the etr het ws redireted to heting the wheels. This is n instne where low-power design m e orret, ut power-wre version n do muh etter. We hve proposed power-wre version of the rover: llowing power usge nd performne to trk power vililit, the power-wre sstem with more sstem-level prllelism hieved 33% speedup while sving 33% tter energ [24].

2 Enourged the initil suess, we eplored dditionl power mngement opportunities t the sstem level. Sine the gol is to inrese the dnmi rnge of power/performne urves, we sought ws to inrese performne in one diretion nd to redue power in the other. To inrese performne when more power (suh s solr) is ville, we ttempted sstem-level pipelining, lss of effetive tehniques tht hve een developed for mn different domins rnging from VLIW instrution sheduling to hrdwre snthesis. To redue energ onsumption, we lso ttempted to inorporte other reserhers new power mngement tehniques tht re power wre. These inlude vriet of dnmi voltge sling (DVS) nd sheduling lgorithms for modern emedded proessors, whose voltge nd frequen n e ontrolled. However, somewht surprising result ws tht mn of these performne-enhnement nd power-redution tehniques ield inorret nd rther ounterintuitive results when pplied together t the sstem level. Eisting pipelining tehniques tht tret the power udget s resoure onstrint (e.g., mpping power to the totl register ount) fil to orretl stisf the power onstrints. On the other hnd, DVS tehniques, whih slow down proessors in order to hieve qudrti energ svings, tull end up onsuming more energ t the sstem level. The min reson these tehniques fil is tht mn importnt sstem-level dependenies re not properl modeled or onsidered. In sstem, the omponents do not work independentl; insted, the work ver muh together with eh other, nd power mngement deisions mde on one omponent n hve hin of effets on the power usge of the other omponents. This is further omplited the ft tht different omponents re uilt with different power mngement pilities. In the Mrs rover, not ll omponents re power mngele. In ft, some omponents inlude motors for steering nd driving the rover, heting elements for melting the frozen lurints on the wheels, nd the R/F module. Mn of these omponents nnot sle their voltge or frequen the sme w proessor n. Furthermore, mode hnges re seldom instntneous or free; insted, the inur nontrivil timing nd power overhed tht nnot lws e mortized. s result, the omined effet of these power mngement tehniques n often ontrdit the designer s intuition nd even nel eh other s effets. It is ler tht n integrted design tool is sorel needed to help designers mnge suh multi-dimensionl prolem: funtionl orretness, timing onstrints, nd power wreness. To ddress these diffiult prolems, we develop tool-sed design methodolog lled IMPCCT, for Integrted Mngement of Power-wre Computing nd Communition Tehnologies. s with most sstem-level design tools, IMPCCT strts with high-level modeling of the pplition, seprte from the trget rhiteture. The designer then uses IMPCCT to trnsform nd refine the high-level model towrds implementtion. IMPCCT lso supports power-wre funtionl simultion to help with design vlidtion. This pper fouses on two of the ore design tsks in IMPCCT: power-wre sheduling nd mode seletion. The ojetives re to enhning the power/performne trdeoff rnge nd to orretl ompose different omponentlevel power mngement tehniques t the sstem-level. Power nd timing onstrints n e used s knos to tune the sstem for performne or power, without hrdwiring to either gol. To mimize performne nd resolve power hot spots, we eploit sstem-level pipelining under pir-wise timing nd totl power s onstrints. Wht distinguishes our work from trditionl softwre pipelining nd resoure-onstrined pipelining works is tht we hndle o-tivtion dependenies, n essentil propert for the orret opertion of these emedded sstems. Furthermore, we propose mode seletion s generlized w for full eploiting novel power mngement fetures provided n inresingl intelligent lss of power-wre omponents. The re ple of mnging power nd provide mn more power modes. However, tod s power mngement tehniques often nnot tke full dvntge of these rih fetures, ut insted the use onl two or three modes (e.g., on/off). Our mode seletion methodolog models the dependen nd produes mode shedule tht onsiders restrited trnsitions nd overhed mortiztion. Together these tehniques not onl form the foundtion for integrting mn power mngement tehniques, ut more importntl the help even eperiened designers void mn pitflls with omposing these omponents t the sstem-level. In the net setion, we review work relted to power mngement nd odesign nd present few simple emples to illustrte the pitflls with ppling tod s tehniques t the sstem level. Setion 3 provides n overview of IMPCCT inluding speifition, rhiteture, nd simultion. The setions tht follow will desrie sheduling

3 nd mode seletion, nd summr of results for severl rel-life driving emples. 2 Relted Work To mimize the power/performne rnge in power-wre sstems, we n drw from mn tehniques developed for low power nd high performne. Low power n e hieved shutting down idle omponents, hnging mode, or sling the voltge. In the other diretion, high performne n e hieved vrious pipelining tehniques done for VLIW nd high-level snthesis. This setion surves relted works in these res with disussion on their integrtion t the sstem level. 2. Low-Power Tehniques Mn low-power tehniques hve een developed t ll levels, rnging from iruit nd logi levels nd miro/mrorhiteturl levels to operting sstem nd pplition levels. For sstem-level designs, sine the omponents re lrgel off-the-shelf or lred designed, the pplile tehniques inlude dnmi voltge sling (DVS) nd dnmi power mngement (DPM) with susstem shutdown. 2.. Dnmi Voltge Sling (DVS) DVS tehniques hve een developed for vrile-voltge proessors. Introdued [48], with follow-up [3, 4, 3] nd more, DVS n hieve signifint energ sving while still enling the proessor to ontinue mking progress. Lowering the voltge will lso require redution in frequen, whih hs the effet of reduing dnmi swithing power. lthough DVS mens running slower, the tpill slow down just enough without violting timing onstrints, nd mn re sed on rel-time tsk sheduling ores [3, 38, 39, 36]. It hs een shown tht miml energ sving is hieved running the proessor t the slowest possile onstnt speed, rther thn running tsks t full proessor speed nd hnging the proessor to lower power mode when idle [6]. Hong et l [3] proposed heuristi for sheduling rel-time tsks on single vrile voltge proessor. Shin [38] eploited oth eeution time vrition nd idle time intervls for fi-priorit tsks. Shin s lgorithm in [39] determines the lowest mimum proessor speed for eh jo to hieve power redution. Qun nd Hu [36] further greedil determine the lowest voltge for set of tsks to hieve more energ svings. However, DVS s notion of sstem is urrentl limited to single proessor without onsidering peripherl devies, nd the results re not generlizle to multiple proessors. Wht these DVS tehniques hve in ommon is tht the re greed nd ssume single proessor. power-wre emedded sstem, however, onsists of multiple resoures, whih m e one or more proessors nd peripherl devies. Luo nd Jh [26, 28] presents stti sheduling for multiple proessing elements (PEs) reordering tsks nd ppling voltge sling in this post-proessing step to smooth the sstem-level power profile. Unfortuntel, ll of these greed DVS tehniques fil to generlize to multiple resoures when there re o-tivtion dependenies nd power onstrints, s shown in the following emple. Emple: (DVS fils in multi-resoure) Fig. () shows Gntt hrt (on top) nd the orresponding power profile (ottom) for sstem with three resoures: R is ple of voltge sling, while R 2 nd R 3 re not voltge slle. The tsk t on R hs dedline t time. The sstem lso hs mimum power onstrint of 3W. Furthermore, the ehvior of the pplition dittes tht R nd R 3 e o-tive. Co-tivtion mens the eeution of one tsk requires the power onsumption of other dependent servies or tsks. simple emple is tht when the CPU is running, it imposes o-tivtion dependen on the memor, ut o-tivtion n e muh more generl etween sets of tsks. Fig. () shows the shedule (top) nd the power profile (ottom) otined greedil slowing down R to hieve energ sving. Even though ll timing onstrints re stisfied, it violtes power onstrints nd it is not minimum energ. The m power onstrint is violted euse when tsk t is strethed out, nd when it overlps tsk t 2

4 R t R t R t R2 t2 R2 t2 R2 t2 R3 t R3 6W t R3 t W W Pm t t2 t () 4W 2W t t t () t2 Pm 2.4W 3W W Pm t t2 t Figure : n pplition senrio tht hs resoure dependen. () Initil shedule nd power profile; () greed voltge sling results in power spike tht violte mimum power onstrint; () fesile solution meets oth power nd timing onstrints, nd sves energ s well. () Shedule Timing violtion Power violtion Energ ost Fig. () No No 3 Fig. () No Yes 32 Fig. () No No 288 Figure 2: Comprison of three shedules, greed voltge sling m violte the power onstrint. during the time intervl from 7 nd, their totl power eeeds the m power onstrint. It is not minimum energ due to the o-tivtion dependen etween R nd R 3 : the energ sving R due to voltge sling is more thn offset R 3 whose voltge is not slle (s given), ut its eeution is prolonged R 3. The optiml shedule nd power profile re shown in Fig. (). Resoure R is slowed down without overlpping tsk t 2 on Resoure R 2. This w, no m power is violted. lthough tsk t 3 on resoure R 3 is strethed with tsk t nd therefore onsumes more energ thn in Fig. (), t sves even more energ due to voltge sling of resoure R. s result, the sstem hieves miniml energ while stisfing ll onstrints. Fig. 2 summrizes the energ osts. nother prolem not highlighted with this emple is tht mode hnges m inur nontrivil power or timing overhed. If so, overhed must e onsidered in determining the fesiilit of the mode shedule Dnmi power mngement (DPM) DPM tehniques, whih re sed on timeout or event predition, ssume multiple omponents with multiple modes. Susstem shutdown deision n e sed on fied idle times, dptive timeout, or preditive sed on mi of profile nd runtime histor [44, 4,, 2]. The simplest power mngement poli is time-out sed on fied or predited mount of time efore the sstem s shutdown or power-up [45, 6]. Stohsti models [3, 34] re used to ddress the unertint in sstem ehviors. Simuni et l [4] omines stohsti-modeled power mngement with dnmi voltge sling to hieve signifint power redution in portle sstems. DPM tehniques n e effetive for minimizing energ nd time penlties on verge, ut the hve severl limittions. First, most tret either power or timing s n ojetive or penlt, rther thn onstrint. In rel sstems, the m power is rel, hrd onstrint, whose violtion n led to mlfuntion. M power ws not of entrl onern previousl, ut s we onsider dditionl power soures suh s solr whose mimum output n vr, the must e stritl stisfied. This eomes espeill importnt s we inrese the dnmi rnge of power inresing prllelism. Seond, the hve not onsidered inter-omponent dependen in sstem, with the eeption of Qiu, Qu nd Pedrm in [35], whih models multiple servie providers nd their Generlized

5 DPM DVS MS [45, 6] [3, 34] [3, 38, 39, 36] [26, 28] Timing s onstrint N N Y Y Y Power s onstrint N N N N Y Timing overhed Y Y N N Y Power overhed Y Y N N Y Multiple resoures N Y N Y Y Figure 3: Comprison of dnmi power mngement (DPM), dnmi voltge sling (DVS), nd mode seletion (MS). Stohsti Petri Net (GSPN) n pture some dependenies mong resoures. However, onl one server is modeled to proess n inoming request, nd the GSPN model is minl for the request/dispth ehvior of servers rther thn dependen mong the servers themselves. Without modeling this dependen, energ sved on the CPU m e more thn offset the inresed energ onsumed the rest of the sstem. Fig. 3 summrizes the fetures of the tehniques surveed here. The lst olumn shows our new pproh, mode seletion, whih omines the dvntges of eisting pprohes. It is entirel onstrint driven, enling us to mke power/performne trdeoffs without hrdwiring n speifi gol or poli in the lgorithm. 2.2 High Performne through Pipeline Trnsformtion In ddition to low power, dnmi rnge n lso e inresed towrds high performne drwing from works on retiming nd rottion nd ppling them to the sstem level. Leiserson et l. first estlished the theoretil foundtion for retiming snhronous iruits [2], nd this hs een etended to loop pipelining nd sheduling for VLIW proessors [37, 7, 7]. Shifting or rotting tsks in dt flow grph (DFG) ross the itertion oundr n result in shorter eeution time or llevite the resoure pressure (e.g. numer of registers nd funtionl units). Suh tehniques re lso used in power minimiztion reduing swithing tivities [8, 5]. Eisting tehniques need signifint enhnements efore the n e orretl pplied to our sstem-level power mngement prolem. The min reson is tht new tpes of dependenies must e modeled t the sstem level, nd the nnot e redil hndled eisting tehniques preproessing. The tsks to e sheduled re relted to eh other not onl preedene or dt dependen nd timing, ut lso o-tivtion dependen s mentioned erlier. Preproessing grouping o-tivted tsks will not ield orret results due to the presene of timing onstrints nd lk of interhngeilit in resoures. We illustrte the prolems with ppling eisting low-power nd high-performne tehniques to the sstem level. Fig. 4 shows n emple to illustrte limittion of some eisting tehniques ompred to the optiml. It will e further used to eplin our sstem model nd sheduling lgorithms in the ensuing tet. In this emple, five tsks,,,, re to e sheduled on four eeution resoures,b,x,y. The onstrints re:. The overll dedline is t time The m power is. 3. The eeution resoures,b re not voltge-slle (e.g. the m e non-omputtion tsks). 4. Onl tsk n e voltge-sled on resoure X (e.g. proessor), nd it hs some slk time to finish efore time Tsk must e o-tivte with tsk, nd its resoure Y is lso not voltge-slle (e.g. memor, I/O).

6 B X Y Power tsk o-tivtes with tsk tsk hs dedline eeeding m power udget 2 3 () The shedule is not vlid sine m power udget is eeeded t time slot [,] due to prllel tsks, nd. Time Pm:. Energ: 9. Time B X Y Power 's eeution del inreses o-tivting with 2 3 eeeding m power udget is slowed down to sve power/energ 2 3 Time Pm:. Energ: 2. more energ Time () DVS tehnique redues power nd energ onsumption of tsk. However, it fils to produe vlid shedule to the entire sstem. The energ omsumption of the whole sstem is inresed o-tivtion. B X Y Power prolog loop od n e iterted fter time shift tsks nd to previous itertion [] [] [] [] shift tsks nd from net itertion Time Pm:. Energ: 9. () Our sstem-level loop pipelining tehnique shifts tsk nd its o-tivted tsk to the previous itertion suh tht the m power udget is stisfied. 3 3 Time Figure 4: n emple where DVS fils to redue power nd energ t sstem level, while our tehnique will sueed

7 Lirr Composition Trnsformtion Snthesis softwre timing nlsis Mnger snthesis rhiteturl mpping mode seletion Compiltion power soure models rhiteture uffer sizing Interfe snthesis Vlidtion seletive fous simultion Tested Figure 5: The IMPCCT sstem-level design tool for power-wre emedded sstems. Note tht tsk does not neessril strt nd finish t the sme time with, ut it hs to strt no lter thn strts nd finish no sooner thn finishes. For simpliit, in this emple we ssume nd strt nd finish t the sme time. Fig. 4() shows timing-vlid shedule with m-power violtion during time [, ]. Resheduling nd in [,2] will e timing-vlid ut still violting m power. Fig. 4() shows tht if DVS ws used to slow down tsk until its dedline of time 2, we ut its energ hlf ording to CMOS sling, nd intuitivel this should eliminte the m power violtion. However, it tull inreses totl energ t the sstem level, euse not onl is DVS limited to on the proessor onl, its lengthened eeution time fores its o-tivted tsk to onsume power over longer time. Thus, energ sved slowing down is more thn offset energ inresed. This is nother emple where DVS should not e pplied in isoltion. Fig. 4() shows fesile solution otined sstem-level pipelining, ssuming itertive tsks. Tsks nd re shifted (or rotted) to the previous itertion to overlp tsk insted of or. s result, oth the m power nd the dedline re stisfied. However, the optiml solution nnot e otined unless we eploit domin-speifi knowledge out the tsk set to eliminte preedene dependen, whih uts the le time down to 2 time units. The detils of rottion under min/m timing nd the use of pseudo-itertion onstrints will e eplined in lter setions. 3 Overview of IMPCCT IMPCCT is sstem-level design tool for eploring power/performne trdeoffs in hrd rel-time sstems mens of power-wre sheduling nd rhiteturl onfigurtion. The urrent implementtion inludes n intertive grphil tool for sheduling, mode seletion, nd n interfe to simultion k-end for integrted evlution of the sstem under design. mdhl s lw pplies to power s well s performne. Tht is, the power sving of given omponent must e sled its perentge ontriution to n entire sstem. Furthermore, sstem in the rod sense inludes not onl omputtionl omponents ut lso those in the non-omputtionl domins (e.g., mehnil nd therml susstems), whih re equll ritil in defense pplitions. IMPCCT is the first tool to orretl ddress ll of these sstem-level power mngement issues. Fig. 5 shows the min omponents of the IM- PCCT frmework, nd this setion will highlight eh o in order. The omintion of these fetures in IMPCCT presents ompelling design-time tool for engineers to eplore wide rnge of sstem-level power/performne

8 trdeoffs with onfidene. 3. Input: pplition Model nd Constrints To use IMPCCT, the designer must onstrut model for the pplition nd onstrints. lthough the detiled pplition ehvior is ultimtel written in one of the sstem progrmming lnguges (suh s C, C++, d, Jv, et), IMPCCT does not proess these files diretl; insted, the re pssed to power/timing nlsis or simultion tools for estimtion or vlidtion. IMPCCT epets the designer to onstrut higher-level model for the pplition in our ustom lnguge. s n integrtion desription, it hs ports nd hnnels for dt dependen, s well s timing nd power onstrints. Note tht timing nd power re not neessril intrinsi to the pplition prolem itself, ut the should rell e viewed s udgets whose vlues re seleted sed on engineering deisions. One min purpose of the tool is to help designers with onstrint refinement or djustment (re-udgeting) giving them quik estimte. This pproh llows the designer to strt working with the power/timing udget for vrious tsks to e performed long efore the progrm or omponent is designed. s theses piees eome ville, the will then e used to refine these udgets with more urte estimtion. We urrentl support power onstrints nd timing onstrints. Power onstrints re the min/m ounds on the power dimension of the power profile. The m-power onstrint requires tht the sstem never drw more thn the speified mount of power t n given moment. It m e derived from the mimum urrent rting of the power suppl nd n e hrd onstrint. Even though most sstems to dte ould ssume suffiient power design, the net genertion power-wre emedded sstems will need to work with muh more diverse set of power soures with muh lower power udgets nd redued vililit. This will mke m-power hrd onstrint. On the other hnd, we elieve min-power will e n equll importnt onstrint: it will e w to fore the sstem to mintin tivit ove ertin level. The min nd m onstrints together will e w to eplore power/performne trdeoffs without eing hrdwired to the low-power gol. Both min nd m power onstrints m e funtions over time. Timing onstrints re in the form of min/m timing seprtion etween pirs of events, where n event n e the strt or end of tsk. This is generl w for epressing preedene, solute nd reltive dedlines, nd lso o-tivtion. Furthermore, tsks ssigned to different resoures m run in prllel. We urrentl use simple ustom lnguge to pture these timing onstrints. The snt of this high-level file is not importnt; it just hs to e epressive enough to onstrut grph desription of the pir-wise timing onstrints nd power. 3.2 Trget rhiteture nd Mpping lso input to IMPCCT re model for the trget rhiteture nd pplition-to-rhiteture mpping. The trget sstem rhiteture provides the primitives for power mngement s well s the power/timing ttriutes needed for sheduling nd mode seletion. The elements of the pplition model re mpped to those of the trget rhiteture: tht is, the tsks re mpped to the proessors, nd hnnels mpped to the usses. IMPCCT provides omponent lirr nd sstem rhiteture templte to id the desription of the trget rhiteture. The omponent lirr onsists of models for omponents nd usses tht in the trget rhiteture. The inlude proessors, memor modules, us ontrollers, ommunition modules, sensors nd tutors, digitl mers, nd vrious peripherl devies. The designer instntites nd onfigures these omponents from the lirr. The omponent models will provide n interfe for the rest of the design tool to sk questions out the power/timing ttriutes needed to snthesize or for simultion. Some of these ttriutes suh s modes, lok rtes, or voltge m e stored s fied vlues, ut others suh s the eeution del or the power onsumption m need to e derived either evluting formul or simultion. Eh omponent model m enpsulte n numer of detiled models (RTL, SPICE, power-mromodel), ut the re strted from the designer. IMPCCT ugments these low-level models with higher-level models for supporting sstem-level power mngement. These fetures inlude the power modes, the llowed trnsitions etween modes, the power/timing oeffiients ssoited with eh mode nd the

9 trnsitions, nd the interfe desription for ontrolling these power mngement fetures. This mode model will e desried in more detil in the Mode Seletion setion. Unlike trditionl hrdwre/softwre o-design tht is more out free-form eplortion of n optiml rhiteture, we tke pltform-sed pproh for prtil resons. IMPCCT provides rhiteturl templtes for onfigurle pltforms, nd urrentl supported is smmetri multiproessor rhiteture interonneted with two-tier us. It n e onfigured for different numers of proessors nd omponents from the lirr. The two-tier us inludes the IEEE 394 ( FireWire ) for high-speed, rel-time dt nd the I 2 C for low-speed ontrol. Both re power effiient nd support dnmill dding/removing or powering up/down individul nodes for the purpose of power mngement. 3.3 Power-wre Sheduling The power wre sheduler supports severl lsses of power wre sheduling to ield the widest possile dnmi rnge of power/performne trdeoffs. The ore sheduler hndles oth timing nd power s onstrints, not just gols. Power nd timing re oth treted s min/m onstrints. The dvntge is tht these onstrints eome the knos for tuning the sstem s power/performne trdeoffs. B mking the onstrints trk the ville solr power, the IMPCCT sheduler hs een shown to elerte the sstem while sving energ t the sme time for Mrs rover. This feture will e ritil to lso sstems tht use lterntive energ soures suh s therml tteries s well s those with therml mngement onerns. In ddition, for dt regulr pplitions where the omputtion n e lenl deomposed into stges the IMPCCT sheduler n eploit sstem-level pipelining stges in onjuntion with proessor throttling, the IMPCCT sheduler n further inrese the dnmi rnge of these sstems. Sheduling will e disussed in Setion Mode Seletion nother omplementr feture in IMPCCT is mode seletion. It is the tsk of deriving the mode shedule for onfiguring the omponents of the sstem, suh tht ll rhiteturl effets re properl onsidered. It tkes s input shedule from the previous step, nd it deides wht power mode in whih eh omponent should operte over time. Mode seletion ddresses issues tht fil to e hndled tod s greed dnmi voltge shedulers onsidering the trnsition overhed nd dependenies. It will not hnge mode if the time/power overhed involved nnot e mortized over the tsks to e performed, nd it lso prevents sstem-level power spikes due to greed, isolted voltge sling. More importntl, IMPCCT s mode seletion properl models nd hndles o-tivtion dependenies. For emple, when the proessor is on, the memor must e on, too. B modeling these dependenies in the mode seletion step, IMPCCT will ensure tht the resulting power mngement poli onsiders ll fetures ritil to the orret opertion of the entire sstem. Mode Seletion will e desried in more detil in Setion Simultion Support IMPCCT supports simultion t vrious stges of the design flow. The high-level pplition desription n e simulted funtionll without mpping to n rhiteture. The IMPCCT high-level simultor hs een integrted into the sheduler. It not onl omputes the ordering of the tsks to run on generi resoures, ut lso invokes the ompiled pplition files vi ntive lls to simulte their funtionlit. The high-level simultor is lso responsile for implementing the inter-proess ommunition mehnisms using uffer mngement. This setup lso enles the integrtion of heterogeneous simultion nd emultion models with uniform user interfe. Beuse the simultion models re eternlized, the IMPCCT simultion oordintor n reple the eternl, ntive lls with n other lls, s long s the onform to omptile pplition progrmming interfe. For emple, hrdwre-in-the-loop simultion n e omplished repling these eternl lls with lls to devie drivers tht ontrol emultion hrdwre. Similrl, these lls n lso e mde to detiled simultion models when ur or ontrollilit is required. The k-end is ompletel deoupled from the front-end, whih provides uniform user interfe inluding visuliztion support. Fig. 6 shows sreen shot of the urrent version

10 Figure 6: Sreen shot of the IMPCCT grphil simultion front-end.

11 of the simultion tool running n utomti trget detetion (TR) pplition. In the enter pnel is the power-wre Gntt hrt showing the pipelined tsks nd the simultion ontrol pnel. The left pnel shows the input imges, while the right pnel shows the output imges tgged with potentil trgets deteted the lgorithm. 4 Power-wre Sheduling IMPCCT provides omprehensive sheduling support for miml power/performne trdeoffs. We hve developed stti sheduling lgorithms for stisfing timing nd power onstrints [?, 24], whih vries the mount of prllelism t the sstem level ording to the ville power (e.g., from the solr pnel). In ddition, severl etensions to the ore sheduler hve een implemented, nd the further widen the trde spe mens of sstemlevel pipeline trnsformtion nd ggressive mode seletion. numer of rottion trnsformtions re not onl effetive for smoothing out the worklod orrowing time nd power ross itertions, ut lso enle dditionl mode hnge involving dditionl proessors. This setion summrizes the urrent stte of the sheduler. 4. Sheduling under Power nd Timing Constrints IMPCCT s ore sheduler solves the power/timing-onstrined prolem s n instne of grph prolem. The timing onstrints re modeled with onstrint grph G(V,E), where the verties V represent tsks, nd the edges E V V represent timing onstrints etween tsks. Eh verte v V hs three ttriutes, d(v), p(v) nd r(v), representing tsk v s eeution del, power onsumption nd resoure mpping respetivel. Eh edge (u, v) E hs two ttriutes, δ(u,v) nd λ(u,v). δ(u,v) speifies the min/m timing onstrints on the strt times ssigned the funtion σ to tsks u nd v, suh tht σ(v) σ(u) δ(u,v). If δ(u,v), edge (u,v) is lled forwrd edge tht speifies min timing onstrint. If δ(u,v) <, it is kwrd edge inditing m timing onstrint. λ(u,v) is lled the dependen depth, whih speifies onstrints ross itertions. n itertion is full pss of eeuting of eh of the tsks one in vlid order. δ(u,v) nd λ(u,v) indite tht the eeution of tsk u in itertion i must preede tsk v in itertion i + λ(u,v) δ(u,v) time units. If λ(u,v) =, edge (u,v) speifies n intr-itertion onstrint. Otherwise, it is n inter-itertion onstrint. shedule σ ssigns strt time σ(v) to eh tsk v V. It hs finish time τ σ when ll tsks omplete their eeution. Shedule σ is lled time-vlid if ll the strt time ssignments do not violte n timing onstrints, nd tsks tht shre the sme resoure re serilized. If G represents n itertion of loop, σ must lso stisf inter-itertion onstrints suh tht the must hold ross itertions when multiple opies of σ re ontented. shedule σ hs power profile funtion P σ (t), t τ σ, representing the instntneous power onsumption of ll tsks during the eeution of σ (illustrted the power view of the Gntt-hrt in Fig. 4). The power profile is onstrined two prmeters: P m,p min, suh tht P m P σ (t) P min. The m power onstrint P m speifies the mimum udget of suppl power tht n e provided the power soures. The min power onstrint P min speifies the level of power onsumption to mintin preferred level of tivit. The m power onstrint is hrd onstrint. t n given time t, the vlue of the power profile funtion P σ (t) must not eeed P m. Shedule σ is lled power-vlid (or simpl, vlid) if it is time-vlid nd its power profile does not eeed the m power onstrint. However, we tret the min power onstrint s soft onstrint tht ould e violted osionll in vlid shedule. In ses where the min power onstrint P min represents the free power level, the energ drwn from the nonrenewle energ soures is defined s the energ ost E σ (P min ) of shedule σ. It distinguishes etween ostl power nd free power in suh w tht n power onsumption elow the free power level does not ontriute to the energ ost on non-renewle energ soures, nd therefore should e utilized mimll. Detils of the sheduling lgorithm n e found in [24]. Sine this is n NP-hrd prolem, we hve developed heuristis sed on slks to enle lolized tsk movements, enling the sheduler to quikl find fesile solutions without epensive ktrking.

12 4.2 Dnmi Rnge Enhnement through Pipelining Sstem-level pipelining n e n effetive w to enhne the dnmi rnge of power/performne trdeoffs. We present onstrint model in sstem-level ontet suh tht the omponent-level power mngement tehniques n snergistill ontriute to the improvement in oth power nd performne to the entire sstem. The distinguishing feture of our method from previous loop pipelining works is tht, eisting tehniques either do not hve timing onstrints δ(u,v) in their dte flow grphs (DFG), or the vlue of δ(u,v) is lws or tht onl indites preedene (dt dependen). Moreover, we orretl model nd hndle o-tivtion dependen etween omponents in sstem. In ddition, we propose new lss of timing onstrints lled pseudo-itertion onstrints to enle more ggressive, domin-speifi trnsformtion for non-omputtionl tsks. It is performed in two steps: () trnsforming the prolem into its pipelined versions, nd () power-direted sheduling for eh pipelined version. We first onstrut timing onstrint grph tht epresses the tsks in n emedded sstem with pir-wise onstrints. The pipelined version of sheduling prolem is otined rottion, when intr- nd inter-itertion onstrints re onverted to eh other. We first onstrut n itertion grph G (V,E ): it hs the sme verties s those of the onstrint grph G(V,E), ut edges E onsist of onl intr-itertion onstrints. Formll, E = {(u,v)},(u,v) E suh tht λ(u,v) =,δ (u,v) = δ(u,v). The epeted loop durtion τ is otined from non-pipelined shedule omputed from the initil itertion grph G. Without loss of generlit, we fous our disussion on down-rottions whih the eeution of tsk is shifted to the previous itertion of the loop, nd the instne of the sme tsk in the net itertion is inluded into the new loop od. The proedure for up-rottion n e similrl defined. tsk v is down-rottle if either verte v V does not hve n inoming forwrd edges, or ll of v s inoming forwrd edges in G hve t lest one dependen depth. If σ is vlid non-pipelined shedule of one itertion, we n down-rotte tsk v ording to the epeted loop durtion, whih is the finish time τ σ of σ. When tsk v is rotted down one itertion in grph G, verte v represents the eeution of tsk v in the net itertion. Therefore, the new strt time ssignment σ (v) = σ(v) + τ. When tsk v is eing rotted, its orresponding min timing onstrints (zero or positive vlues) will eome m timing onstrints (negtive vlues), nd its orresponding m timing onstrints will trnsform into new min timing onstrints. Fig. 7 illustrtes the rottion of our emple previousl shown in Fig. 4. Eh edge in the onstrint grph G is denoted s (λ,δ), while in itertion grph G there is onl δ. Inter-itertion onstrints re mrked s dshed rrows. Co-tivtion is denoted s speil pir of timing onstrints. Fig. 7() shows the initil grphs G nd G nd the shedule tht violtes the m power onstrint. The non-pipelined shedule hs finish time τ = 3. Fig. 7() shows rottion to tsk nd its o-tivted tsk to produes new vlid shedule (sme s Fig. 4(), eept tht the prolog is not shown) whih otherwise nnot e hieved without rottion. Tsk n e resheduled to time slot [2, 3] euse its outgoing min onstrints re trnsformed into more reled m onstrints (δ (,) = 3,δ (,) =, ompred to nd 2 in Fig 7()). Tsks nd re rotted together due to o-tivtion, ut the re sheduled s seprte tsks euse the m not strt nd finish t the sme time. Fig. 7() further rottes tsk. The hnges to edges in G in Fig. 7() re reversed, nd some new edges orresponding to re hnged. It gives vrition of the solution in Fig. 7(). If tsks nd re rotted net, the initil onstrint grph in Fig. 7() will e restored. Rottion is sed on the lssifition of inter-itertion nd intr-itertion timing onstrints. However, in some ses, it is diffiult (or unneessr) to deide whether timing onstrint should e inter-itertion or intr-itertion. Suh ses re present in the Mrs rover. For emple, for timing onstrints etween heter nd motor whih the motor is heted periodill, whether to model these onstrints s intr-itertion or inter-itertion is not ler. In ft, whether the heters nd the motors st in the sme itertion does not mtter. This is different from dt dependenies in omputtion domin. We define suh tpe of onstrints s pseudo-itertion timing onstrints, whih mens the onstrints n e epressed s either inter-itertion or intr-itertion. pseudo-itertion onstrint etween two tsks u nd v is lso represented s n edge (u,v) E in onstrint grph G with its dependen depth denoted s λ(u,v) =,

13 Constrint grph G Itertion grph G' Shedule σ o-tive o-tive (,) (,) (,) (,2) (,) (,2) (,) (,) (,) (,) (, -2) () efore pipelining, no vlid solution n e found. (, -2) () fter rotting tsk nd its o-tivting tsk, vlid solution is found. o-tive (,) (,) (,2) (,) (,) o-tive o-tive (, -2) o-tive () fter rotting tsk, vrition of solution () is produed B X Y Power B X Y Power B X Y Power Time Pm:. Energ: Time [] [] 2 3 Time Pm:. [] Energ:9. [] 2 3 Time [] [] [] 2 3 Time Pm:. [] Energ:9. [] [] 2 3 Time Figure 7: Rottion with timing onstrints

14 Constrint grph G Itertion grph G' Shedule σ o-tive o-tive (*,) (,) (,2) (*,) (,) () efore pipelining, no vlid solution n e found. (,) (,2) (,) () fter rotting tsk nd its o-tivting tsk, vlid solution is found. o-tive (*,) (*,) (,) (,2) (*,) (*,) (,) (*, -2) o-tive (*, -2) o-tive (*, -2) o-tive B X Y Power B X Y Power () fter rotting tsk with pseudo-itertion onstrints, new solution with etter performne is found. B X Y Power Time Pm:. Energ: Time [] [] 2 3 Time Pm:. [] Energ:9. [] 2 3 Time [*] [] [] 2 Time [*] Pm:. [] Energ: 9. [] 2 Time Figure 8: Rottion with pseudo-itertion onstrints

15 inditing tht it n e either zero or non-zero; nd it will e inluded in itertion grph G initill. Pseudoitertion onstrints will e lws reled suh tht more sheduling opportunities eome ville. For emple, if resoure in our emple is heter nd resoure B re the motors, then the orresponding onstrints of tsk n ll e modeled s pseudo-itertion ones. This is shown in Fig. 8() where pseudo-itertion onstrints re mrked s different tpe of dshed rrows. Fig. 8() performs rottion to tsks nd, similr to Fig. 7(). In Fig. 8(), when tsk with pseudo-itertion onstrints is rotted, the orresponding onstrint vlues in grph G re different from those in Fig. 7() in omprison. Speifill, we hve the edge δ (,) = 2 s opposed to, nd δ (,) = 3 insted of. Sine the seriliztion hin formed min onstrints is roken, tsks,, (fter rottion to, the hin eomes,, in Fig. 7()) no longer hve to e serilized. Now tsk, smll power onsumer, n overlp with suh tht surprising solution with shorter eeution time (τ = 2) is produed, nd it lso stisfies m power onstrint. This optiml solution nnot e otined without modeling pseudo-itertion onstrints, whih ggressivel rel the onstrints in the prolem ut re provl orret. 5 Mode Seletion s new omponents re eing uilt with more intelligent power mngement fetures, it will e importnt to tke full dvntge of these fetures. Unlike esterd s omponents tht offer onl ver simple modes suh s on, off, nd sleep, new omponents n tull e n entire sstem on hip nd n hve more thn dozen modes. For emple, tod s tpil hrd disk offers over fifteen power modes. Unfortuntel, most of tod s power mngement tehniques re le to hndle onl two or three modes. We propose mode seletion s sstemti w for optimizing the power/performne settings t the omponent level to est mth the eeution ontet of the sstem. It is generl euse it susumes voltge slling nd it n lso enompss tehniques t other levels of strtion, inluding seletion of lterntive lgorithms nd dt strutures s new ws of mnging power. The ke prolems in mode seletion inlude () the modeling of the ttriutes ssoited with the modes nd trnsitions etween pirs of modes; (2) pturing the interdependen etween modes of different omponents in sstem; (3) define the ost funtion sed on the energ-del produt; nd (4) effiientl generte fesile progression of these mode settings while stisfing ll timing nd power onstrints. 5. Mode ttriutes Modes re ttriutes of resoure, whih is generlized term for omponent in sstem. resoure γ is defined s grph R γ (M γ,h γ ), where M γ is set of verties, nd H γ M γ M γ is set of edges. verte m M γ is power mode of resoure γ. n edge (m,n) H γ represents mode hnge from mode m to mode n. we define the timing nd energ funtion for mode hnge s: F : M γ M γ T En, where M γ is the set of modes of resoure γ, nd T, En re time nd energ, respetivel. The verge power n e otined from energ nd time informtion. For emple, proessor m hve tive, idle, nd sleep modes. Chnging from n mode to other modes inurs time nd energ overhed. Usull wkeup from sleep to tive mode needs more time nd energ thn from idle to tive mode. t rhiteturl levle, mode hnge overhed m e time nd energ of hnging hrdwre onfigurtions onl. t pplition level, it m inlude overhed to retore the ontet, reinitilize the OS or lod progrm. The modes re not limited to simple power modes like on, off, doze, np, or sleep, ut lso enompss he onfigurtions for proessors, different enoding/deoding tehniques for rdio ntenn, vritions of ompiling tehniques for softwre omponents, nd different trnsmission protools for us drivers. Eh omponent is modeled s power nd del funtions on modes nd trnsitions. We define the mode set of omponent, µ, whih is the set of ll the power mode m µ. Power onsumption is represented s funtion, π, mpping from power mode to power numer. Formll, π : µ R +. Del of mode trnsition is defined s funtion, δ, mpping from strt mode nd end mode of trnsition to del numer. Formll, δ : µ µ R +. Given N resoures (γ,γ 2,...,γ N ), mode omintion π Π of the resoures (tsks) is omintion of N modes π = (m,m 2,...,m N ). m i is mode ssigned to resoure γ i (tsk τ i ), i N.

16 mem.on pu.tive Figure 9: Mode dependen emple: the memor is on onl if the CPU is in tive mode. ND OR XOR B C B C B C T T T T T T T T F T F F T F T T F T F T F F T T F T T F F F F F F F F F X U U X U U X U U U X U U X U U X U Figure : Truth tle for ND, OR, nd XOR opertors. C is the output of op B. T: True; F:Flse; X: don t re; U: undetermined. The output of the prolem is n optiml onfigurtion sheme with the minimum ost in terms of the powerdel-produt. onfigurtion sheme is tle tht mps eh omponent to gloll optiml power mode over time. 5.2 Mode Dependen Grph Seleting (or not seleting) mode of resoure m impt the modes tht other resoures re llowed to selet. The impt m e o-tivtion, whih fores nother resoure to selet given mode; it m lso e elusion, enling, nd mn other possile tpes of dependen. These dependenies m e etrted from pplition level speifitions or poliies for sfet, seurit, fult-tolernt, power-sving, or m e epliitl speified s mode orreltion [5]. In n se, legl mode omintion of the resoures is one tht respets ll of these dependenies, nd fesile mode omintion is one tht is legl nd stisfies ll the onstrints (nmel timing nd power). We use dt struture lled the mode dependen grph (MDG) tht enles effiient genertion of legl mode omintions in n order tht filittes the serh for fesile omintions tht re lso low ost. mode dependen grph (MDG) G m (V,E) represents the inter-resoure dependen reltionships, where verte V is resoure mode, nd direted edge E onnets two verties. Eh verte is represented irle with lel in the formt of res.mod, where res is the resoure nd mod is the mode of the resoure. If two verties hve the sme lels, we onsidered them identil. The vlue of verte V is defined s: True V = Flse Undetermined if res is in mod mode, if res is in other mode, if res hs not een seleted mode. n edge in the MDG represents dependen etween two modes. Suppose n edge (u,v) E, u = res.mod, v = res2.mod2. The two modes mod nd mod2 stisf the mode dependen grph if u is True onl if v is True. For emple, we n represent the dependen etween CPU nd memor hip suh tht the memor is on onl if the CPU is in tive mode (see Fig. 9). If the CPU is in sleep mode nd the memor is on, then it violtes the mode dependen. If the CPU is in sleep mode, nd the memor is off, then it does not violte the mode dependen. Of ourse, if the CPU is in tive mode nd the memor is on, it stisfies the mode dependen. In ddition, we lso support logi opertors s nother kind of verties. n opertor verte is represented squre with n opertor lel in it. n opertor verte V op hs t lest two fn-in, nd t lest one fn-out, mening tht V op hs t lest two verties pointing to it nd it points to t lest one verte. The vlue of n opertor verte n e otined evluting the logi funtions tht the grph represents. We define the opertors ND, OR, XOR, nd MUT EX. The truth tles of opertor ND, OR, nd XOR re listed in Fig.. The mening of ND, OR nd XOR follows the norml oolen funtions in the sme nmes eept when ()

17 R.r R.r_t S.off R.off S.off MUTEX ND XOR.sleep.sleep.idle ().tive M.on M.on.tive : proessor M: memor R: rdio S: sensor S R R R S M M I => S R V M S R M III Figure : () n Mode Dependen Grph emple: miro sensor. () Redue n MDG to resoure list for generting mode omintions. Bo I: from the MDG, shrink eh opertor verte to point, nd remove mode nme in eh mode verte. Bo II: remove the redundent verties nd edges. Bo III: rek the le ing removing one edge in the le, nd ppl topologil sort to otin resoure list. () II n input is undetermined, the output is undetermined. When the opertion of MUT EX (not listed in Fig. ) is inr, its mening is the sme s XOR; when MUT EX hs multiple inputs (more thn two), the output is True if nd onl if one input is True nd the rest of input re Flse. The etended mode dependen grph lso follows onl-if interprettion. For emple, the top left item in Fig. () shows the dependen mong sensor (S), rdio devie (R) nd proessor (). The semntis epressed here is tht S nd R re oth off onl if is in sleep mode. If, for emple, S is off, R is off, nd is in tive mode, it violtes the dependen. If S is on, R is off, nd is in sleep mode, it does not violte the dependen. Fig. () shows the mode dependen grph of the mirosensor emple[42]. The mirosensor sstem onsists of sensor to sense the environment, proessor, memor module, nd rdio modem. In this sstem, the ehviors nd dependenies of the devies n e derived from high-level power mngement poliies: the sensor nd the rdio re oth off onl if the proessor is in sleep mode; either of them is on onl if the proessor is in sleep mode or idle mode; oth the sensor nd the rdio re on onl if the proessor is in tive mode; the memor is on if nd onl if the proessor is tive. 5.3 Cost Funtion We define the ost funtion to represent the sstem ost for the shedule. B ompring the osts of different onfigurtions, we determine n optiml solution for the prolem. The ost funtion is in the form of powerdel produt with two min prts: operting energ E op nd trnsition energ E tr. We hve E = E op + E tr = P op T op + P tr T tr. Operting energ is the energ onsumed when the omponent is in ertin mode. Trnsition energ is the energ onsumed when the omponent is swithed from one onfigurtion step to the net. Trnsition time is the del on mode hnge. Sometimes either the trnsition power or trnsition time is lrge, whih mkes the trnsition ost high. We eplore n optiml solution to hve n onfigurtion with minimum vlue of ost funtions. 5.4 Mode Seletion lgorithm The mode dependen grph (MDG) ptures enough informtion to enle the effiient genertion of fesile mode omintions. The detils of this lgorithm is in [?], ut sill it is speil version of topologil trversl on the MDG with ktrking. In prtie, however, ktrking is not neessr nd the MDG hs lred pruned out ll of the infesile omintions. The serh speed is muh loser to liner thn eponentil. This setion illustrtes its pplition to mirosensor node in distriuted sensor network. It onsists of sensor, proessor, memor hips, rdio frequen module nd other uilir prts. When the sensor otins informtion from environment, it sends dt to the proessor, the dt is proessed nd sent to sesttion or other network node vi RF module.

18 omponent sensor (S) proessor () memor (M) Rdio (R) mode on, off tive, idle, sleep on, off r, t r, off mode S R M M on t r tive on M2 on r idle off M3 on r sleep off M4 on off sleep off *M5 off t t tive on *M6 off r idle off *M7 off r sleep off M8 off off sleep off Figure 2: Modes of omponents in mirosensor. Figure 3: Mode omintions generted from MDG. The modes for the omponent is summrized in Fig. 2. The sensor nd the memor eh hs two modes, on nd off. The proessor hs three modes, tive, idle nd sleep. The rdio hs three modes, reeive-onl (r), trnsmit-nd-reeive (t r), nd off. There re totl of 36 mode omintions for these omponents. The inter-omponent reltionships re speified using MDG s shown in Fig. (). The grph follows the onlif interprettion, nd the grph semntis omes from sstem level power sving poliies. For emple, the sensor nd rdio re oth off onl if the proessor is in sleep mode. Either of them (not oth) is on onl if the proessor is in sleep or idle mode. The proessor is tive onl if the memor is on, nd vise vers. Using the MDG, our lgorithm utomtill generte eight mode omintions tht stisf the given MDG (see Fig. 3). The generted mode omintions n e used sstem power mnger s legl modes in sstem level power mngement. This simple emple demonstrted our lgorithm s ilit to sstemtill generte legl mode omintions tht stisf inter-omponent dependenies, nd editing the mode dependen grph, we n otin mode omintions without mnull going through ll possile mode omintions. 6 Eperimentl Results 6. Sheduling We use the NS/JPL Mrs rover [] to evlute the effetiveness our sstem-level pipelining tehnique. We onstrut sstem-level representtion tht inludes the omputtionl, mehnil nd therml susstems. The timing onstrints on the heters n e modeled with pseudo-itertion onstrints. We lso onsider the dul energ soures: solr pnel nd non-rehrgele tter. We onsider three senrios with different solr power output levels: 4.9W (noon time), 2W, nd 9W (dusk). The min power onstrints re set to the respetive solr outputs, while the m power onstrints re set to the solr power plus W, whih is the mimum tter power rting. Tle ompres the results of four tehniques using the energ ost to non-rehrgele tter nd the eeution time s metris: () the eisting mnul solution, (I) previous power-wre sheduling [24], (II) sstem-level pipelining without pseudo-itertion onstrints, (III) sstem-level pipelining with pseudo-itertion onstrints. In senrio, sine the power udget is suffiient, fst shedule is omputed ll shedulers. However, solution I is quite epensive in terms of energ ost; II is heper. III delivers sme performne with lower energ ost thn oth I nd II, nd it would not hve een possile without pseudo-itertion onstrints.