A Low Power Parallel Sequential Decoder for Convolutional Codes

Transcription

1 Int. J. Com. Dig. Sys. 2, No. 2, 95-(23) 95 Interntionl Journl of Computing n Digitl Systems 23 UOB SPC, University of Bhrin A Low Power Prllel Sequentil Deoer for Convolutionl Coes Ail EL Bourihi Ntionl Shool of Applie Sienes, In Tofil University, Kenitr, Moroo e-mil: ilelourihi@gmil.om Reeive 8April 22, Revise 3 Ot. 22, Aepte 5 De 22 Astrt: A novel eoing lgorithm hving simple hrwre reliztion is propose for onvolutionl oes. The propose eoer epts simple implementtion in hrwre in terms of re oupny n power onsumption ompre to other eoers for onvolutionl oes suh s those se on the Viteri lgorithm (VA). Furthermore, the proessing elys ue to looking k n forwr in trellis s in sequentil eoing lgorithms re voie, whih mkes the propose eoer suitle for fst high t rtes wireless ommunition systems. Simultion results show omprle it error rte (BER) performne to optiml eoers with reution of power onsumption of 6% ompre to Viteri eoers. Keywors: Convolutionl oes, low power eoers, sequentil eoing, wireless ommunition. I. INTRODUCTION Error ontrol oing (ECC) is lssi pproh to inrese link reliility n lower the require trnsmitte power. However, lowere power t the trnsmitter omes t the ost of inresing power onsumption of the reeiver euse strong n effiient oes require omplex eoers with high power onsumption. Convolutionl oes re one of the most importnt ECC tehniques. Deoing of onvolutionl oes (CC) is generlly lssifie in two tegories: Mximum Likelihoo (ML) eoing of whih the Viteri Algorithm (VA) [] is well known exmple n su-optiml lgorithms suh s sequentil lgorithms. The Viteri eoer hs een prove to e mximum-likelihoo eoer [2]. However, it hs een reporte tht more thn 3% of power onsumption in wireless system is ue to the Viteri eoer [3][4][5][9]; moreover Viteri eoing is imprtil for onstrint lengths >=7 require for high t rte pplitions [6][7][8][]. Sequentil eoing lgorithms, on the other hn, try heuristilly to fin the most prole pth in tree or trellis struture. While these lgorithms hve lower omplexity thn VA, they re su-optiml n suffer from vrile eoing time whih mkes them non suitle for fst high t rte wireless pplitions. In this pper, we propose prllel sequentil eoing lgorithm where ll prole pths in tree re uilt in prllel n the est pth is eie for t the en of the lgorithm. Low power onsumption of this lgorithm, its fixe proessing time n its suitility for hrwre implementtion mke it strong nite for fst n high t rte eoing in next genertion wireless networks. II. RELATED WORK A. Convolutionl Coes A onvolutionl oe is n error orreting oe in whih eh k it informtion symol to e enoe is trnsforme into n n it symol, where n k is the oe rte ( n k ), n the trnsformtion is funtion of the lst l informtion symols, where l is the onstrint

2 96 A.EL Bourihi: A Low Power Prllel Sequentil length or memory of the oe. Suh oe is enote y the three-tuple ( n, k, l). A onvolutionl enoer is esrie s mehnism of shift registers n moulo-2 ers, where the output its re moulr-2 itions of seletive shift register ontents n present input its. Figure shows the enoer of inry (2,,2) oe s one shift register onsisting of two ely elements n two outputs: ( t) t) t ) t 2) ( t) t) t 2) 2 During the enoing proess, the ontents of shift registers in the enoer re initilly set to zero. The k input its re then fe into the enoer in prllel forming the input messge u onsisting of k its, to generte n output its oring to the shift-register frmework, these n outputs re interleve to otin the finl oewor. u D D v v = = Figure 2. FSM for the enoer of figure Stte Trnsition Tle Coewor Stte Trnsition Messge it Input Input v 2 Figure 3. Stte trnsition tle for the enoer of figure Figure. Enoer for the (2,,2) onvolutionl oe with genertors g=() n g2=() The stte igrm of this system is epite in Figure 2. The sttes re efine s u( t ), u( t 2) pirs n the stte trnsitions outputs re efine s t), ( ). A ( 2 t trnsition shown s otte rrow in the figure orrespons to it input of n ol trnsition orrespons to it input of. The output its of the enoer re shown for eh trnsition. The stte igrm n lso e represente s stte trnsition tle, shown in figure 3. The stte igrm offers omplete esription of the system. However, it shows only the instntneous trnsitions. It oes not illustrte how the sttes hnge in time. To inlue time in stte trnsitions, trellis igrm is use (Figure 4). Eh noe in the trellis igrm enotes stte t point in time. The rnhes onneting the noes enote the stte trnsitions. Figure 4. Trellis for the oe of figure

3 A.EL Bourihi: A Low Power Prllel Sequentil 97 In theory, oe sequenes of onvolutionl oes re of hlf infinite length. But for prtil pplitions, usully finite sequenes re use. There re three ifferent methos to otin finite oe sequenes: Truntion: We stop enoing fter ertin numer of its without ny itionl efforts. This les to high error proilities for the lst its in sequene. Termintion: We some til its to the oe sequene in orer to ensure preefine en stte, whih les to low error proilities for the lst its in sequene. Til iting: We hoose strting stte whih ensures tht strting n en stte re the sme. This les to equl error protetion. In generl we prefer termintion or til iting, where til iting inreses the eoing omplexity n for termintion itionl reunny is require. In this pper, we onsier only terminte oe sequenes, where we strt enoing in the ll-zero enoer stte n we ensure tht fter the enoing proess ll memory elements ontins zeros gin; this n e one y ing kl zero its to the informtion sequene of length N. B. The Viteri eoing lgorithm The Viteri eoer [] exmines n entire reeive sequene of given length. The eoer omputes metri for eh pth n mkes eision se on this metri. All pths re followe until two pths onverge on one noe. Then the pth with the higher metri is kept n the one with lower metri is isre. The pths selete re lle the survivors. The most ommon metri use is the Hmming istne metri. This is just the ot prout etween the reeive oewor n the llowle oewor. Other metris re lso use. These metris re umultive so tht the pth with the lrgest totl metri is the finl winner. Given oe vetor Z, the Viteri lgorithm s ojetive is to fin pth through the trellis strting t the ll-zero stte n ening t the ll-zero stte so tht the istne mesure etween Z n sequene U orresponing to the esire pth is minimize. The Viteri lgorithm relies on the oservtion tht of two pths entering ertin stte in trellis in given time instnt, only one of them is goo. Therefore, the si ie of the lgorithm is to ientify whih pth shoul e erse. This is one using the follwing proeure: If ertin stte s(t) t time t n e rehe from two sttes s (t) n s (t) vi rnhes v (t) n v (t) respetively, then: A est pth to s(t) = est of (est pth to s (t) extene y v (t), est pth to s (t) extene y v (t)). Figure 5. Pth elimintion in VA C. Sequentil eoing lgorithms A onvolutionl oe with n ritrrily long onstrint length my e eoe y reursive treeserh tehnique lle sequentil eoing. There exist vrious sequentil eoing lgorithms, of whih the fstest is proly the Fno lgorithm [9]. In generl, sequentil lgorithms follow the est oe pth through the oe trellis (whih eomes tree for long onstrint lengths) s long s the pth metri exees its expete vlue for the orret pth. When wrong rnh is tken, the pth egins to look n the lgorithm then ktrks n tries lterntive pths until it gin fins goo one. Sequentil eoing hieves symptotilly the sme error proility s mximum likelihoo eoing ut without serhing ll possile sttes. In ft, with sequentil e oing the numer of sttes serhe is essentilly inepenent of onstrint length, thus mking it possile to use very lrge (K = 4) onstrint lengths. This is n importnt ftor in proviing suh low error proilities. The mjor rwk of sequentil eoing is tht the numer of stte metris serhe is rnom vrile. For sequentil eoing, the expete numer of poor hypotheses n kwr serhes is funtion of the hnnel SNR. With low SNR, more hypotheses must e trie thn with high SNR. Beuse of this vriility in omputtionl lo, uffers must e provie to store the rriving sequenes. The lrge vritions in the require eoing effort of onventionl sequentil eoers hve me them onsiere to e unsuitle for pplitions tht inlue perioi, hr elines suh s rel-time pplitions.

4 98 A.EL Bourihi: A Low Power Prllel Sequentil III. PROPOSED DECODER Supposing tht messges were enoe using the termintion tehnique, i.e. zeros re e t the en of the messge to flush the enoer s ontents, onvolutionl eoer eies tht given oewor is vli when the prsing in trellis or tree orresponing to tht oewor strts n finishes t the ll zero stte. When suh pth is unique, the eoer is hr eision eoer. The propose eoer in this pper is hr eision eoer tht ims t reuing the hrwre omplexity relte to metri lultions n omprisons in VA while voiing the elys in eoing time ue to looking k n forwr in trellis or tree s in sequentil eoers. A. Deoing lgorithm The propose lgorithm uils tree of sttes hving s root the ll-zero stte. At the strt of the lgorithm, the tree onsists of single noe tht is the root noe equl to the ll-zero stte. Upon reing the first oewor, the eoer looks t the trnsition tle to fin trnsition tht hs the stte t the root s strting stte n tht outputs the urrent oewor; if suh trnsition exists, the eoer extrts the finl stte from it n s it s hil to the root noe. The orresponing messge it is lso extrte n store ppropritely. Now, the tree onsists of the root noe n one lef noe tht represents the next stte of trnsition tht hs the ll-zero stte s originting stte n the first oewor of the reeive oe vetor s output; the lef noe will e use s the strting stte of possile trnsition tht outputs the next oewor; if suh trnsition exists, then its finl stte is e to the tree s hil stte of the previous lef stte. If ll the next oewors re orret, the lgorithm outputs tree tht onsists of single pth tht is the orret pth tht woul hve een output y lssi sequentil lgorithm. Now, let s suppose tht n error h ourre n tht the first oewor hs een erroneous; tht mens there is no trnsition strting t the root stte tht outputs tht oewor. The eoer then looks t ll n-it oewors n fins those tht re output y trnsition strting t the root stte. For inry oes, there shoul e two of these oewors n for eh one the finl stte is extrte from the orresponing trnsition n e s hil to the root stte. Now, the tree onsists of root noe n two leve noes. On reing the next oewor, the eoer looks t trnsitions strting t eh of the two new leves tht output tht oewor n for eh leve pproprite hilren re rete. After ll oewors hve een re, the eoer output is tree onsisting of multiple pth, eh pth orresponing to sequene of stte trnsitions tht efine possile oewor sequene. The pth whose orresponing finl stte is the ll zero stte is eie to e the orret one n the orret messge it is eoe ppropritely. The next exmple illustrtes the working of the propose eoer for the (2,,2) oe isusse erlier. Let s suppose the messge m is enoe into oe vetor U=whih is trnsmitte through the hnnel tht inues n error into its 4 th it n the oe vetor reeive t the eoer is Z=.The eoer uils tree hving s root the ll zero stte. The eoer res the first oewor n, oring to the trnsition tle in figure 3, fins tht it is output to trnsition orresponing to messge it of ; therefore the first rnh of the tree is rete hving s root stte n s single hil stte ; the eoe messge it of is eqully store ppropritely. It is importnt to note here tht the eoer oes not store the tree entirely ut stores only the leves (the new finl sttes) n their orresponing eoe messges. For this purpose, set of 2-it registers re rete (in implementtion, the set of 2-it registers n e reple y long register onsisting of 2-it loks) n upte eh time 2-it oewor is re. Tht is, in the exmple ove, on reing the first 2-it oewor n etermining its orresponing trnsition ( ), the new stte is store in the sme ple where stte ws store efore, n eoe it of is store in n pproprite register to store eoe messges. At the next lok yle, the 2-it oewor is re. Looking t the trnsition tle, there is no trnsition tht outputs n hs s strting stte mening tht n error hs ourre n orretion is neessry. The eoer looks t ll possile oewors tht oul hve een originlly sent: two wors with Hmming istne of to erroneous wor, these re n, n one wor with Hmming istne of 2 to erroneous tht is. This ltter oes not orrespon to ny trnsition strting t stte ut n o orrespon respetively to trnsitions with messge it n with messge it. The new finl sttes re therefore n, n they orrespon respetively to eoe messge n. One of these sttes (sy, stte ) will e store in the sme lok where originl stte use to e store efore (in implementtion, the first two its

5 ... A.EL Bourihi: A Low Power Prllel Sequentil 99 from the left of the finl sttes register) while the other finl stte (here, stte ) will e store in the susequent lok (the 3 r n 4 th it of the finl sttes register). This sme proeure is repete for every 2-it oewor. After ll oewors hve een re, i.e. fter 6 lok yles in this exmple, it is time for the eoer to mke the hr eision on the sent messge, this is one simply y tking the messge orresponing to the finl stte equl to the ll zero stte. In this prtiulr exmple, the orret messge is the 9 th messge sine the 9 th stte is the only one tht is equl to the ll-zero stte. More speifilly, the eoer outputs numer of finl sttes, 9 sttes in the exmple:,,,,,,, n n numer of messge its (9) orresponing to these finl sttes:, n. These outputs re the two registers finl_sttes_register n eoe_messges whose ontents fter the 6 th lok yle re: finl_ sttes_ register eoe _ messges... m m2... m9 where, m m 2... m 9 The 9 th finl stte is equl to the ll zero stte, n therefore the 9 th messge is the orret one. The orret pth n orret messge re shown in ol in the tree in figure 6 showing the exeution tre of the lgorithm for the stuie exmple. lok yle # of finl Finl Sttes Deoe its sttes Input V t eh lok yle{ w re _ next _ nit_ oewor for eh finl sttes in finl_ sttes_ register{ if( TrnsitionS ( S, w)) then S S elsefor eh k it w if( TrnsitionS ( S, w)) then S to n pproprit e plein finl_ sttes_ register if thislok yleisthelst onethen{ for I to numer_ of _ finl_ sttes if finl_ sttes_ registeri [ : I l ]... (with pproprit e shiftingto preserveolontent) then : oevetor, N : numer of n itsoeworsin V i w{ finl_eoe_messge eoe_ messgesi [ : I N ] Figure 7. Propose eoing lgorithm B. Ciruit for the propose eoer The notion of mintining list of ll possile finl sttes t eh point of time is essentil to the propose lgorithm, sine t the en of the proessing when ll oewors hve een re, only one finl stte in this list will equl the ll-zero stte n therefore give the finl eoe messge. This list of finl sttes n e represente y single register onsisting of loks of l its ( l eing the memory or onstrint length of the oe), eh lok of l its representing prtiulr stte. Likewise, the eoer shoul mintin list of eoe messges, eh messge orresponing to one prtiulr finl stte. Therefore, it is essentil to use n pproprite inexing mehnism to mth eh finl stte with its orresponing eoe messge. For resons of revity, the mehnism of upting the eoe messges n the inexing mehnism re not shown in the funtionl esription of the iruit in figure 8 elow euse the unerstning of their existene n funtionlity is intuitive. The iruit shown in figure 8 represents the min prt of the propose eoer tht is the mehnism of uiling the tree of sttes s in the exmple of figure 5. Figure 6. Exeution tre for the exmple The min working of the lgorithm is shown in figure 7.

6 BER A.EL Bourihi: A Low Power Prllel Sequentil for eh stte Si in the finl sttes register: Current Coewor w Finl Stte Si for eh oewor wj : wj Si Chek in the trnsition tle if there is trnsition strting t stte Si n tht outputs w Upte Si with the finl stte of the orresponing trnsition Chek in the trnsition tle if there is trnsition strting t stte Si n tht outputs wj Upte Si with the finl stte of the orresponing trnsition No No Yes No Yes Compute w, w2,, hving Hmming istnes of to k from oewor w o nothing Hs Si lrey een upte? Yes Upte Si with the finl stte of the orresponing trnsition Figure 8. Funtionl esription of the eoer s iruitry e- e-2 e-3 e-4 e-5 e-6 e-7 e E/N (B) Figure 9. BER versus E/N VA Propose Algorithm Unoe The iruitry shown in figure 8 onsists of two prts tht re shown together euse they hppen in the sme lok yle, i.e. for one n -it oewor. Every time oewor is re, for ll finl sttes eing presently mintine y the eoer, the ltter nees to look t the trnsition tle to fin if there is trnsition tht outputs this oewor n hs s strting stte tht prtiulr finl stte. If there is one then no orretion nees to e one n the new finl stte simply reples the ol one. If there is no trnsition strting from tht prtiulr stte n outputting the present oewor, then the funtionlity shown in the lower prt of figure 8 is performe: the oewor is ssume to e erroneous n orretions re neessry; first, ll possile oewors hving Hmming istnes from to n re store (tht is ll n -it wors exept the erroneous oewor) n then for eh of these oewors the existene of vli trnsition is heke n pproprite etermintion of the next finl stte n its storge s well s upting the eoe messge re one ppropritely. IV. SIMULATION AND RESULTS The propose eoing lgorithm hs een simulte using C lnguge n ompre to VA in terms of it error rte (BER) performne n verge power onsumption. Constrint lengths were hosen etween 7 n n n itive white Gussin noise (AWGN) hnnel ws ssume with BPSK (Binry Phse Shift Keying) moultion. Results were verge over 2 simultion runs to otin the BER performne shown in figure 9. Results speifi to power onsumption were otine for the (2,,2) oe presente erlier in the pper. Design Compiler from Synopsis ws use to otin gte level iruit from RT level esription in Verilog. The tehnology use in our experiments is CMOS 9nm with supply voltge.v. The propose eoer issiptes 42 miro-wtts ompre to 23 miro-wtts issipte y register exhnge (RE) implementtion of the Viteri eoer, resulting in out 6% improvement in power effiieny. V. CONCLUSION Deoing of onvolutionl oes using prllel sequentil lgorithms is promising lterntive to omputtionlly expensive Viteri lgorithm n to suoptiml ely inurring lssi sequentil lgorithms espeilly euse next genertion wireless networks re expete to hve strong low power n proessing spee requirements. To the est of our knowlege, there hsn t een enough work on effiient implementtions of prllel sequentil eoers for onvolutionl oes n we elieve tht improvements of the propose eoer in this pper re possile to llow more spee n lower power onsumption. REFERENCES [] A. Viteri, Error ouns for onvolutionl oes n n symptotilly optimum eoing lgorithm, IEEE Trnstions on Informtion Proessing, 3:26-269, 967. [2] D. Forney, The Viteri lgorithm, Proeeings of the IEEE, vol. 6, pp , Mrh 973. [3] I. Kng n A. N. Wilson, Low power Viteri eoer for CDMA moile terminls, IEEE Journl of Soli Stte Ciruits, vol. 33, No. 3, pp , Mrh 998.

7 A.EL Bourihi: A Low Power Prllel Sequentil [4] S.J. Li, T. L. Brnon, D. G. Elliott, n V. C. Guet, "Power Chrteriztion of Git/s FPGA Convolutionl LDPC Deoer," in Signl Proessing Systems (SiPS), 22 IEEE Workshop on, 22, pp [5] H. Shen-Rei n C. Su-Gee, "A novel pipeline CCK eoer for IEEE 82. system," in Soli-Stte n Integrte-Ciruit Tehnology, 28. ICSICT 28. 9th Interntionl Conferene on, 28, pp [6] Sun, Yng, n Joseph R. Cvllro. "A low-power - Gps reonfigurle LDPC eoer esign for multiple 4G wireless stnrs."soc Conferene, 28 IEEE Interntionl. IEEE, 28. [7] S. Yng, J. R. Cvllro, n L. Ti, "Slle n low power LDPC eoer esign using high level lgorithmi synthesis," in SOC Conferene, 29. SOCC 29. IEEE Interntionl, 29, pp [8] H. L. Lou, Implementing the Viteri lgorithm, funmentl n rel time issues for proessor esigners, IEEE Signl Proessing Mgzine, pp , Septemer 975. [9] R. Henning n C. Chkrti, Low power pproh for eoing onvolutionl oes with ptive Viteri lgorithm pproximtions, ISPLED 2, August 2-4, 22, Monterey, Cliforni, USA. [] X. Wng, Y. Zhng n H. Chen, Design of Viteri Deoer se on FPGA, 22 Interntionl Conferene on Applie Physis n Inustril Engineering, pulishe y Elsevier in Physis Proei 24, pp