DESIGN AND IMPLEMENTATION OF 32 BIT HIGH LEVEL WALLACE TREE MUTIPLIER

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1 uinput0(7:0) uinput1(7:0) U2 x(7:0) P00 y(7:0) P01 P10 P02 P1 P20 P03 P12 P21 P30 Pe04 Pe13 Pe22 Pe31 Pe40 Pf05 Pf14 Pf23 Pf32 Pf41 Pf50 Pg06 Pg15 Pg24 Pg33 Pg42 Pg51 Pg60 Ph07 Ph16 Ph25 Ph34 Ph43 Ph52 Ph61 Ph70 Pi17 Pi26 Pi35 Pi44 Pi53 Pi62 Pi71 Pj27 Pj36 Pj45 Pj54 Pj63 Pj72 Pk37 Pk46 Pk55 Pk64 Pk73 Pl47 Pl56 Pl65 Pl74 Pm57 Pm66 Pm75 Pn67 Pn76 Po77 inputn1 hlf_er U3 U4 U1 U12 U8 U7 U6 U5 U19 U9 U11 um 2 um 2 U13 U62 U63 U49 U20 um rry rryout um rry rryout um rry rryout um 2 um rry rryout U10 U35 hlf_er U23 U24 U25 U17 U26 U60 um 2 hlf_er U22 U29 hlf_er U34 U33 U30 hlf_er hlf_er hlf_er U61 U52 um U47 2 U42 U37 U21 um rry rryout um U14 2 U31 U28 um 2 um rry rryout um rry rryout Output0 U32 U16 Output1 Output2 U66 hlf_er U38 U39 hlf_er U40 hlf_er U41 hlf_er U36 hlf_er U43 Output3 Output4 hlf_er U44 U45 hlf_er U46 hlf_er hlf_er U15 Output5 hlf_er U50 U51 hlf_er U48 hlf_er Output6 hlf_er U53 Output7 U55 U18 U56 U58 U57 U65 Output14 Output10 Output11 Output13 Output15 Output8 Output12 Output9 Interntionl Journl of Tehnil Reerh n pplition e-in: , Volume 1, Iue 4 (ept-ot 2013), PP DEIGN ND IMPLEMENTTION OF 32 IT HIGH LEVEL WLLCE TREE MUTIPLIER M.RVINDR KUMR 1, G.PRMEWR RO 2 1 Dept. of ECE C E, Chilkplem rikkulm, Ini. 2 o. Prof. Dept. of E C E C E, Chilkplem rikkulm, Ini. trt --- Deigning multiplier tht re of peey, low power, n tnr in lyout re of generou reerh interet. Wlle tree multiplier i one of the multiplier, whih i ue to omplih high pee n low power multiplier n to onene the numer of prtil prout generte in multiplition proe. To trim own the time Wlle Tree er truture hve een ue to um the prtil prout.in generl Wlle tree multiplier re exiting in 8*8 it multiplier n 16 it multiplier. In thi pper we put forwr 32 it high level Wlle tree multiplier truture i invetigte n ee. 32 it Wlle high-pee multiplier ue full er n hlf er, 4:2 ompreor, 3:2 ompreor in their elining phe. The Wlle tree multiplier i oniting of 64 regiter, 64 flip flop n 3 hlf er well 960 full er with logi time ely i n n off et time ely i 7.6 n, hving totl memory uge i M. The eign i effiiently mppe to Hrwre Reoure in PRTN-3 FPG. The eign i implemente, imulte n yntheize y uing Verilog. Inex term---multiplier, Wlle tree er (WT), Compreor, Prtil Prout. I. INTRODUCTION In the mintrem of igitl ignl proeing ( DP ) pplition the ruil opertion hitully engge mny multiplition n/or umultion. For rel-time ignl proeing, high pee n high throughput Multiplition n umultor lwy key to pull off high performne igitl ignl proeing ytem. In the lt few yer, the min ontempltion of MC eign i to improve it peeine. For the reon tht, ttery energy eile for thee portle prout onfine the power onumption of the ytem. To omplih high pee MC, it i inipenle to inten high pee multiplier. To ttin high pee, the renowne Wlle highpee multiplier utilize Wlle tree er to iminih n N-row it prout mtrix to orreponing two row mtrix o to umme y men of rry propgting er to provie the prout. The Wlle tree er re preitle full er whoe rrie re not onnete, oringly tht three wor re tken in n two wor re output. The Wlle multiplier lo ue full er n hlf er, 4:2 ompreor, 3:2 ompreor in their reution phe. Thi pper preent high level wlle tree multiplier eign tht gretly reue the numer of hlf er for progreive pee. II. WLLCE TREE MULTIPLIER high-pee proeure for multiplition of two numer w evelope y Wlle. It exeute the umultion opertion in imilr, onequentil in le ely. In Wlle tree multiplier, ivere wy of omprle ition of the prtil prout it y tree of rry ve er, whih i well-known Wlle tree. Wlle tree i ompetent hrwre exeution of igitl iruit tht multiplier two integer.in orer to exeute the multiplition of two numer with the Wlle metho, prtil prout mtrix i ompte to two-row mtrix y uing rry ve er n the left over two row re umme vi ft rry-propgte er to form the prout. Thee improvement turn into more prominent i now. The itne of the Wlle tree i tht there re only O(log(n)) eline lyer, n eh lyer O( 1 ) h trnmiion ely. mking the prtil prout i O (1 ) n the ultimte ition i O (log n ) the multiplition i only O( log n ), not muh lower thn ition. Honetly ing prtil prout with tnr er woul nee O(log2 n ) time. From omplexity theoreti perpetive, the Wlle tree lgorithm ple multiplition.thee multiplition only oniere gte ely n on't el with wire ely, whih n lo onierle. The eneth figure how tht the ommon lok igrm of Wlle tree multiplier. It onit of Hlf er n full er. 86 P g e

Interntionl Journl of Tehnil Reerh n pplition e-in: 2320-8163, www.ijtr.om Volume 1, Iue 4 (ept-ot 2013), PP. 86-90 Fig 2.1 lok Digrm of Wlle tree multiplier.

2 Interntionl Journl of Tehnil Reerh n pplition e-in: , Volume 1, Iue 4 (ept-ot 2013), PP Fig 2.1 lok Digrm of Wlle tree multiplier.. Wlle tree Reution Proeure In Wlle tree propol, ll the it of ll of the prtil prout in eh olumn re e imultneouly mong et of ounter in prllel not inluing propgting ny rrie. n itionl et of ounter then reue thi new mtrix n o on, witing two-row mtrix i generte. Wlle tree multiplier ue three -tep proeure for the multiplition. tep 1: Formtion of it prout. tep 2: The it prout mtrix i reue to 2-row mtrix y uing Wlle tree er. tep 3: The remining two row re umme uing ft rry propgte er to Proue the prout. The eneth figure emontrte out the proeure of Wlle tree multiplier. Fig.2.2: Wlle tree multiplition reution proeure. WLLCE TREE DDER Wlle tree h een ue in thi projet in orer to pee up the multiplition y ontriting the numer of prtil prout. Thi eign i one uing hlf er, full er Wlle tree er pee up the multiplition. Let u onier 4 it wlle tree er hown in the figure elow there re four ign extenion vlue generte nmely ign 1E, 2E, 3E n 4E for the prtil prout PP1, PP2, PP3 n PP4 orreponingly. The Prtil prout line rrngement of totl four prtil prout i hown in figure2.3. Fig 2.3: Prtil Prout Initil rrngement The eon prtil prout h to e hifte left y two it efore ing to the firt prtil prout. Hene the thir will e hifte left y four where for fourth it will e hifte left y fifth n o on. Hene fter proper rrngement ll the four prtil prout will e e long with the ign extenion. Fig 2.4: Wlle Tree Multiplition Metho Firt of ll, the prtil prout initil rrngement i rerrnge into firt tge hown in figure 2.4. It n e een like tree hpe here. The tge from PP36 till 1 from the 4th prtil prout i timulte to the firt row n 3E together with 1 i move up to the row prtil prout 2. ehin rerrngement, the firt three row will e e uing hlf er n Wlle tree er. The fourth prtil prout will not e e firt ut will e ent iretly to the eon tge. Hene, there totl up to nine Wlle tree er n four hlf er. For eon tge, the ummtion of the firt hlf er in right hn ie of the firt tge i exmine. fter the ummtion i one to up PP02 n PP10, The UM (10) will e generte in the me olumn the eon tge how where the CRRY (1C0) will e hift left into next level of ummtion. In thi tge, the it PP30-PP35 i ultimtely eing e uing Wlle tree er. t thi tge, it 4E i lo eing e y uing hlf er. Hene, there re totl ix Wlle tree er n even hlf er neee in thi tge. In thir tge, it i finl tge er n ine there re only remining two input to e e inte of three, thu ition opertion i ue to perform the finl ummtion e on the um n Cout ignl in whih h een propgte y the eon tge. The it PP00 n PP01 re iretly ent to the output without going through ny gte level. Hene, Wlle tree er will hve 17 it length output inluing the rry from the finl it. Like in thi wy the me proe w performe y the wlle tree er for 8 it wlle tree multiplier n 16 it wlle tree multiplier. n the me onept i ue in high level 32 it wlle tree multiplier lo. C. Hlf er: In the reution proe of wlle tree multiplier the hlf er re ue frequently. The hlf er two ingle 87 P g e

Interntionl Journl of Tehnil Reerh n pplition e-in: 2320-8163, www.ijtr.om Volume 1, Iue 4 (ept-ot 2013), PP. 86-90 inry it n. It h two output, um () n rry (C).

The hlfer two input it n generte rry n um whih re the two output of hlf er hown in elow figure 2.5. thn two term in one olumn re e uing full er expline ove in Wlle tree reution proeure.

it Wlle high level multiplier, the prout output i hown. 3:2 ompreor tke four input n generte two output with rry given to next tge.

hlf er oe not ontriute muh more in iminution phe, it i eentil to eree the numer of hlf er. The utomize Wlle tree ontrution reue the numer of hlf er therefore iffiulty reue.

3 Interntionl Journl of Tehnil Reerh n pplition e-in: , Volume 1, Iue 4 (ept-ot 2013), PP inry it n. It h two output, um () n rry (C). The rry ignl ignifie n overflow into the next igit of multi-it ition. The vlue of the um i 2C +. The implet hlf-er eign i hown in elow figure. Integrte n XOR gte for um n n ND gte for Crry. The hlfer two input it n generte rry n um whih re the two output of hlf er hown in elow figure 2.5. thn two term in one olumn re e uing full er expline ove in Wlle tree reution proeure.. The um otine fter eh ition i enote y where vrie from 1 to 991. imilrly rrie re enote y where vrie from 1to 991 n enote next rrie, where vrie from 1 to 32. it Wlle high level multiplier, the prout output i hown. 3:2 ompreor tke four input n generte two output with rry given to next tge. Full er tke three input to generte two output whih ontin um n rry while hlf er tke two input n proue two output ontining um n rry. hlf er oe not ontriute muh more in iminution phe, it i eentil to eree the numer of hlf er. The utomize Wlle tree ontrution reue the numer of hlf er therefore iffiulty reue. 32*32 it multiplition preent 1024 prtil prout whih re reue uing Wlle tree y uing ove omponent. D. Full er Fig 2.5: Hlf er logi igrm In the proe of wlle tree multiplier reution full er re lo ue frequently. full er inry numer n ount for vlue rrie in well out hown in elow figure 2.6. ingle it full er three one-it numer, renowne,, n C in ; n re the opern, n C in i it rrie in from the next le ignifint tge. The full-er i uully omponent in e of er, whih 8, 16, 32, et. it wie inry numer. The iruit proue two-it output, output rry n um typilly repreente y the ignl C out n. Fig it Wlle tree multiplier. RTL CHEMTIC VIEW OF HIGH LEVEL WLLCE TREE MULTIPLIER Fig 2.6: Full-er logi igrm III. DEIGN OF 32 IT HIGH LEVEL WLLCCE TREE MULYTIPLIIER The multiplition of two numer X n Y eh one hving 32 it n proug it reult Prout of 64it explin the metho of ition of ifferent intermeite term. The ifferent intermeite term forme fter the multiplition of two 32-it numer re. Two intermeite term in one olumn re e uing hlf er n more Fig: Full RTL hemti View of 32 it wlle tree multiplier. LOOK UP TLE look-up tle i n rry tht reple runtime omputtion with impler rry inexing opertion. The ving in term of proeing time n e ignifint, ine retrieving vlue from memory i often fter thn unergoing n expenive omputtion or input/output opertion. The tle my e prelulte n tore in tti progrm torge.the 88 P g e

Interntionl Journl of Tehnil Reerh n pplition e-in: 2320-8163, www.ijtr.om Volume 1, Iue 4 (ept-ot 2013), PP.

IMPLEMENTTION OF 32 IT WLLCE TREE MULTIPLIER IN VERILOG HDL Verilog Hrwre Deription Lnguge i enormou low level lnguge. truturl moel re troule-free to eign n ehviourl RTL oe i ppeling goo.

4 Interntionl Journl of Tehnil Reerh n pplition e-in: , Volume 1, Iue 4 (ept-ot 2013), PP elow figure how tht the look up tle whih re exiting in high level wlle tree multiplier. Fig 3.3: LUT in the wlle tree multiplier IV. IMPLEMENTTION OF 32 IT WLLCE TREE MULTIPLIER IN VERILOG HDL Verilog Hrwre Deription Lnguge i enormou low level lnguge. truturl moel re troule-free to eign n ehviourl RTL oe i ppeling goo. The yntx i tnr n imple to rememer. It i the et HDL lnguge to lern n ue. Neverthele Verilog require uer efine t type n require the interfe-ojet eprtion of the VHDL' entity-rhiteture moel. Thi pper i implemente in Verilog HDL in ehviourl RTL oe. V. YNTHEIZED REULT The 32 it high level Wlle tree multiplier i implemente on PRTN 3 FPG evie n it i yntheize on Xilinx 8.2i Verion y uing Verilog hr wre eription lnguge oe. The yntheize report n Devie ummry Utiliztion report hown elow. The Wlle tree multiplier i oniting of 64 regiter, 64 flip flop n 3 hlf er well 960 full er with logi time ely i n n off et time ely i 7.6 n, hving totl memory uge i M. Fig 5.1: yntheize report of Wlle tree multiplier.device UTILITION UMMRY VI. MPRIION TLE I. Differentiting the Reult 89 P g e

5 Interntionl Journl of Tehnil Reerh n pplition e-in: , Volume 1, Iue 4 (ept-ot 2013), PP NME OF THE MULTIPLIER RRY MULTIPLIER OOTH MULTIPLIER POWER VLUE 140mw 125mw work. The uthor woul lo like to knowlege the upport provie y the tehnil tff of Elet. & Comm. Engg., ri ivni College Of Engineering, JNTUK proviing him with the mple menitie, wy & men through whih he w ple to inluive thi tk. REFERENCE PROPOED WLLCE TREE MULTIPLIER If we evlute the ove vlue long with eh other we n exmine tht the rry Multiplier i the wort e multiplier overwhelming highet mount of power. Then ome the Rix 2 ooth multiplier whih onume leer power thn rry multiplier. The Wlle Tree multiplier onuming leer power thn the other. Hene we reh to onluion tht the Wlle tree multiplier i one of the et for itution requiring Low power pplition. VII. NCLUION The 32 it high level Wlle tree multiplier n e reolve & nlyze uing metho of Wlle tree ontrution. The high level tree h omewht le ignifint ritil pth n ome extent lrger wiring overhe ut it entil low power n high pee. There i no requirement of logi regiter, regiter, pin memory it n PLL. Thi high level wlle tree multiplier, whih onit of full er n reue no. of hlf er n reue the omplexity n ve the power. CKNOWLEDGMENT 94mw The uthor woul like to thnk MR.G. PRMEWR RO, o. Profeor, Eletroni & Communition Engineering (pelz n in VLI D e i g n ),ri ivni College Of Engineering, JNTUK, for hi ontinuou upport n enourgement for thi [1]. Rvi Chnr Kihore, K.V. Rmn Ro Implementtion of rry-ve er in FPG IJET IN: , Volume-1, Iue-6, ugut [2] M. V.N. CHUDHRY,PROF. DR. P.R. DEHMUKH NLYI ND IMPLEMENTTION OF LOW POWER WLLCE TREE MULTIPLIER JIKRECE NOV 10 TO OCT 11 VOLUME 01,IUE-02. [3] imrn Kur n Mr. Mnul nr FPG IMPLEMENTTION OF EFFICIENT MODIFIED OOTH WLLCE MULTIPLIER Thipur Univerity,Pune,June [4] J.-L. euht n J.-M. Muller, utomti genertion of moulr mul-tiplier for fpg pplition, IEEE Trntion on Computer, vol. 57, no. 12, pp , Deemer,2008. [5] J. Detrey, F. e Dinehin, n X. Pujol, Return of the hrwre floting-point elementry funtion, in Proeeing of the 18th IEEE ympoium on Computer rithmeti (Montpellier, Frne), Kornerup n Muller, E. Lo lmito, C: IEEE Computer oiety Pre, June 2007, pp [6] H. Eerle, G. N.,. hntz, V. G upt, L. Rrik, n. unrm, puli-key ryptogrphi proeor for R n ECC, in Proeeing of the Interntionl Conferene on pplition-peifi ytem, rhiteture n Proeor (P2004), eptemer [7] H. R. Imil, R.C., High performne omplex numer multiplier uing ooth-wlle lgorithm, in IEEE Interntionl Conferene on emionutor Eletroni ICE, Novemer [8] K. Mnohehri n. Pourmozfri, Moifie rix-2 montgomery moulr multiplition to mke it fter n impler, in IEEE Interntionl Conferene on Informtion Tehnology: Coing n Computing, ITCC 2005pril. 90 P g e

ECE 274 Digital Logic Fall Digital Design. RTL Design RTL Design Method: Preview Example. RTL Design RTL Design Method

ECE 274 Digital Logic Fall Digital Design. RTL Design RTL Design Method: Preview Example. RTL Design RTL Design Method ECE 274 igitl ogi Fll 2 ntroution to igitl eign 5. 5.2 igitl eign Chpter 5: lie to ompny the textbook igitl eign, Firt Eition, by Frnk Vhi, John Wiley n on Publiher, 27. http://www.vhi.om Copyright 27