Seamless Integration of SER in Rewiring-Based Design Space Exploration

Transcription

1 Semless Integrtion of SER in Rewiring-Bsed Design Spe Explortion Soeeh Almukhizim* & Yiorgos Mkris Eletril Engineering Dept. Yle University New Hven, CT 62, USA Astrt Rewiring hs een used extensively for optimizing the re, the power onsumption, the dely, nd the testility of iruit. In this work, we demonstrte how rewiring n lso e used for reduing the Soft Error Rte (SER). We employ n ATPG-sed rewiring method to generte funtionlly-equivlent yet struturlly-different implementtions of logi iruit sed on simple trnsformtion rules. This rewiring pility, long with n off-the-shelf methodfor ssessing the SER of iruit, enle the integrtion of the SER in unified serh lgorithm tht itertively evolves the design in order to stisfy given set of ojetives. Experimentl results on ISCAS'89 nd ITC'99 enhmrk iruits verify tht rewiring n indeed e suessfully used to redue the SER of iruit nd, thus, it filittes design-spe explortion frmework for trding off re, power onsumption, dely, testility, nd SER. Introdution Soft errors re emerging s serious reliility thret to the opertion of logi iruits. When high-energy neutrons or lph prtiles strike sensitive region in semiondutor devie, they generte Single Event Trnsient (SET) whih my lter the stte of the system, resulting in soft error. Wheres soft errors hve trditionlly een of muh greter onern in memories, smller feture sizes, lower voltge levels, higher operting frequenies, nd redued logi depth re projeted to use drmti inrese in soft error filure rte in ore omintionl logi in su-loonm tehnologies []. Thus, designers re fed with the hllenging tsk of implementing pproprite reliility mehnisms to shield eletroni iruits ginst soft errors. To this end, vrious methods hve een proposed in the literture [2, 3, 4,, 6,, 8, 9,, ] to redue the Soft Error Rte (SER) of iruit nd, thus, improve its reliility. The ide ehind most of these methods revolves round developing solutions t the physil level, wherein individul trnsistor hrteristis re pertured to redue the sensitivity of logi gtes to SETs. While these methods re prtiulrly * The uthor is supported through sholrship from Kuwit University. Yu-Shen Yng & Andres Veneris Eletril nd Computer Engineering Dept. University of Toronto Toronto, Ontrio MS 3G4, Cnd effetive in reduing the SER of design, they re tehnology dependent, i.e. they rely on informtion ville only fter mpping of iruit to trget tehnology. In ontrst, in this work we re interested in investigting tehnologyindependent methods, i.e. logi-level methods tht selet, mong the mny possile gte-level implementtions of iruit, the one tht minimizes its SER. While suh logilevel methods nnot enefit from the detiled informtion ville t the physil level, nd, thus, my not e le to provide omprle levels of SER redution, they offer two unique dvntges. First, they enle design modifitions for SER redution tht re eqully effetive independent of the tehnology to whih the iruit will e mpped. Seond, they provide the ility to onsider SER s design ojetive muh erlier in the design yle. Moreover, the mehnisms through whih soft errors n e verted t the logi level re typilly orthogonl to those t the physil level; hene, logi-level SER redution methods do not intend to sustitute their physil-level ounterprts ut, rther, to provide etter strting point. Yet the literture lks solutions for reduing the SER of iruit t the logi level. In this pper, we propose systemti logi-level SER redution method through the use of rewiring. Rewiring methods hve een extensively used for trnsforming logi iruit to meet design onstrints suh s minimizing re [2, 3, 4], reduing power onsumption [], stisfying timing requirements [6, ], nd improving testility [8]. Herein, we lso demonstrte how rewiring n e used to minimize the soft error rte of design. Thus, we dvote tht rewiring n e used s the ornerstone of ommon frmework for exploring the trde-off spe etween re, power onsumption, dely, testility, nd SER. We strt, in Setion 2, y desriing n ATPG-sed rewiring method whih we use to generte funtionlly-equivlent yet struturlly-different gte-level iruit implementtions through set of simple trnsformtion rules. We then illustrte using simple exmples, in Setion 3, how these trnsformtion rules my redue the soft error rte of iruit. Then, in Setion 4, we propose n lgorithm whih evolves design through itertive seletion of rewiring opertions, in order to optimize ost funtion refleting oth the soft error rte nd the rest of the design prmeters of iruit. Finlly, in Setion, we evlute the proposed method using ISCAS'89 nd ITC'99 enhmrks.

2 2 ATPG-sed Rewiring Ciruit Err;o= The underlying priniple of rewiring is the explortion of the spe of funtionlly-equivlent ut struturlly-different implementtions of iruit, in order to optimize given ost funtion. Typilly, rewiring methods [2, 3, 4,, 6,, 8, 9, 2, 2] trget wire tht violtes some onstrint(s), lled the trget wire, nd delete it from the implementtion. Susequently, they pply the trnsformtions neessry for orreting the funtionlity of the design. For the purpose of the work desried in this pper, we use s strting point the ATPG-sed rewiring method desried in [22]. This method first introdues design error sed on suset of the ommon design error models proposed in [23]. In prtiulr, this rewiring tool supports the following design error models, whih re illustrted in Fig. :. Missing Input Wire: This is the design error tht is ommonly performed y most rewiring tools. The error is introdued y removing the trget wire. 2. Inorret Input Wire: The trget wire is repled y nother wire tht hs similr logi vlues (i.e. wire tht, with proility of. or higher, otins the sme vlue s the trget wire). 3. Gte Replement: The type of the gte driven y the trget wire is hnged depending on the proility of the logi vlues of the trget wire. If the proility of Logi (Logi ) on the trget wire is higher thn., the gte is hnged to (N) AND ( (N) OR). This error model is novel to the work desried herein. 4. Extr Input Wire: A wire with similr logi vlues to the trget wire is dded to gte driven y the trget wire. This error model is lso novel to this work. After the design error is introdued, the rewiring tool ttempts to orret the design using simultion-sed Design Error Dignosis nd Corretion (DEDC) lgorithm, whih returns list of orretions tht retify the design. The orretions returned y the rewiring tool n only orret design y performing single orreting opertion. Therefore, DEDC will fil to find orretions if: * The trget wire is stem. In this se, the error models Missing Input Wire, Gte Replement, nd Extr Input Wire re not pplile sine the design error will introdue multiple errors t the rnhes of the stem. * The gte driven y the trget wire is n inverter or uffer. In this se, the error models Gte Replement nd Extr Input Wire nnot e pplied. In oth ses, dditionl informtion is required to omplete the error injetion. For exmple, hnging uffer to NAND gte requires n dditionl input wire to e speified. Hene, the iruit will hve two design errors. Missing Input Wire Inorret Input Wire Corret Inorret Gte Replement Extr Input Wire Figure. Supported Design Error Models * The gte driven y the trget wire is 2-input gte. In this se, the Missing Input Wire error model nnot e pplied sine the iruit will lso hve two design errors, i.e. Missing Input Wire nd Gte Replement. Finlly, the orretions re verified using ATPG. Verifition is neessry sine the DEDC lgorithm ensures the vlidity of orretion using suset of the omplete input vetor spe nd, therefore, the orretions returned re only vlid for this prtiulr suset of vetors []. Detils regrding the implementtion of the ATPG-sed verifition step re eyond the sope of this pper nd n e found in [22]. 3 Impt of Rewiring on SER The SER of omintionl iruit is proportionl to three ftors [, ]: i) the rte of ourrene of n SET t gte (RSET), ii) the proility of n SET rehing n output sed on the urrent inputs to the iruit (P8,n,), nd iii) the proility tht n SET is lthed in storge element (lth). Among these ftors, rewiring primrily impts PSS.,. The proility of n SET rehing n output, Psens, is mesured y performing fult-simultion of the iruit for tht SET nd omputing the perentge of times tht the output responses were erroneous. Sine rewiring hnges the sensitiztion pths through whih SETs my propgte to the outputs, the Psen,s of ny given SET my either inrese or derese, depending on the tivtion likelihood of its new sensitiztion pths. Thus, in order to ssess the effetiveness of rewiring opertion, its impt on the P,,,, of ll SETs in the iruit should e tken into ount [, ]. Throughout this work, omputtion of the SER is performed using SERA [], whih tkes into ount ll the forementioned ftors. 2

3 () () () ) Design Error Model: Missing Input Wire. The SER Redues y.6%. () () () 2) Design Error Model: Inorret Input Wire. The SER Redues y 3.3%. () () () 3) Design Error Model: Reple Gte. The SER Redues y 3.3%. () () () 4) Design Error Model: Extr Input Wire. The SER Redues y.6%. Figure 2. Exmples of Rewiring Opertions tht Redue the SER Using the 4 Design Error Models (() Trget of Error, () Ciruit After Error, nd () Ciruit After DEDC). In the following, we provide simple exmples to demonstrte tht eh of the four error models supported y the rewiring tool my result in orretions tht redue the SER. 3. Missing Input Wire Error Model In the missing input wire error model, the trget wire is removed from the iruit nd the DEDC lgorithm retifies the design using single orreting opertion. The Psens of ny wire my either inrese or derese in the orreted iruit nd, thus, the ggregte impt might e fvorle, reduing the SER of the iruit. For exmple, in the iruit shown in Fig. 2.., rewiring deletes G3 -- G, whih results in the inorret implementtion in Fig During the DEDC stge, -s G is identified s possile orretion nd is dded to the iruit, s illustrted in Fig The SER of the orreted iruit in Fig. 2.., redues y.6% over the initil iruit in Fig Inorret Input Wire Error Model In the inorret input wire error model, the trget wire is repled y nother wire in the iruit nd the DEDC lgorithm retifies the design using single orreting opertion. Thus, the ritrry impt on the Pserts of the wires in the orreted iruit my result in n overll redution of the SER. For exmple, in the iruit shown in Fig. 2.2., rewiring sustitutes G2 - G with - G, resulting in the iruit shown in Fig DEDC identifies - G s possile orretion nd dds it to the iruit, s shown in Fig The SER of the orreted iruit in Fig. 2.2., redues y 3.3% over the SER of the initil iruit in Fig

4 Primry Inputs Primry Outputs XI Primry Outputs Primry Inputs Xl ) Modified Ciruit XIX o IXx x3 o x- x3 xix x- I lxx o o f g 9g2 g4 l g3 ) Definition of the Input (gl-g3), Output (f) nd Inteml Signls (g4-g) XX2\ ) Modified Ciruit o I Figure 3. Exmple Illustrting the Intuition Behind the Gte Replement Error Model. 3.3 Gte Replement Error Model The gte replement error model, whih ws dded to the rewiring tool implementtion of [22] for the purpose of this work, hnges the type of the gte driven y the trget wire. This, in turn, redues the Psens of one of the two pos nd sile SETs (i.e. ) tht n ffet the trget wire for the following reson. If the trget wire hs high proility of otining non-ontrolling vlue of the gte tht it drives, then n SET tht flips the trget wire to the ontrolling vlue of the gte hs high proility of propgting to its output. Consequently, Psen, will e high for tht prtiulr SET. By introduing n error tht hnges the type of the gte, the trget wire will now hve high proility of otining ontrolling vlue of this gte. Therefore, the sme SET will now flip the trget wire to the non-ontrolling vlue of the gte nd, hene, hs low proility of propgting to its output. By extension, Psen8 will now e redued for this prtiulr SET. The intuition ehind the gte replement error model is illustrted using the exmple in Fig. 3, whih shows prt of logi iruit. Let f e the output funtion of this su-iruit nd gl, 92 nd g3 e the input funtions, expressed in terms of the primry inputs xl, x2 nd X3, s illustrted in the Krnugh mps of Fig. 3., nd ssume tht 92 is the trget wire for rewiring. Sine 92 hs high proility of otining logi vlue of ( non-ontrolling vlue of the OR gte tht it SET on 92 hs high proility of propdrives), gting to the output of the OR gte. Conversely, SET on 92 hs low proility of propgting to the output of the s x x o xik I XIx,XIx i l x T l o x I [ Ijj g g3 g2 xix o g4 f ) Definition of the Input (gig3) nd Output (f) Signls Figure 4. Exmple Illustrting the Intuition Behind the Extr Input Wire Error Model. OR gte. When the error is introdued y hnging the gte type to n AND gte, nd fter orreting the design error in the modified iruit of Fig. 3.l, the proility of -> SET on 92 propgting to the output of the AND gte redues, while the proility of SET propgting to the output inreses. Yet, it is possile tht the ggregte impt will e fvorle, reduing the SER of the iruit. For exmple, onsider the iruit shown in Fig. 2.3., wherein the AND gte G3 is repled y n OR gte, resulting in the inorret iruit of Fig Then, the DEDC lgorithm orrets the design y repling G3 with G3, s shown in Fig nd the SER of the orreted iruit redues y 3.3% over the SER of the initil iruit Extr Input Wire Error Model The extr input wire error model dds similr wire to the gte driven y the trget wire. This, in turn, redues the Psen of one of the two possile SETs on the trget wire for the following reson. If the trget wire hs high proility of otining ontrolling vlue of the gte, n SET tht flips the trget wire to the opposite (non-ontrolling) vlue will propgte to the output of the gte, unless nother input of the gte lso hs ontrolling vlue. Thus, y dding similr wire s n extr input to the gte, we inrese the proility tht suh ontrolling vlue will exist nd, y extension, the proility tht the SET will e msked. 'The output of the iruit in the exmple is not ffeted y the hnge in the gte type nd, thus, no orretion is neessry. 4

5 The intuition ehind the extr input wire error model is illustrted using the exmple in Fig. 4. Let 92 e the trget wire for rewiring nd let g9 - g4 e defined s illustrted in Fig. 4.. The funtionlity of g4 is similr to 92 (identil for % of the possile input omintions) nd is dded s n input to the OR gte in the modified iruit in Fig. 4.. Sine 92 hs high proility of otining logi vlue of ( ontrolling vlue of the OR gte tht it drives), -- SET on 92 hs high proility of propgting to the output of the OR gte. When g4 is dded in the modified iruit, however, the proility of -- SET propgting to the output of the OR gte is redued sine g4 will hve ontrolling vlue of the OR gte with high proility. While the ddition of g4 introdues new lotion where SETs might pper, the -h SET on g4 will often e msked t the output of the OR gte s g2 will lso hve the ontrolling vlue of the gte with high proility. On the other hnd, -- SET on g4 might propgte to the output of the OR gte with high proility. Yet, it is possile tht the overll effet will e redution in the SER of the iruit. For exmple, onsider the trget wire G2 -- G in the iruit of Fig Wire -- G, whih is similr to G2 -- G sine it otins the sme vlue in % of the input omintions, is dded in the implementtion of Fig The DEDC lgorithm orrets the iruit y deleting G2 -i G, s shown in Fig. 2.4., thus reduing the SER y.6%. 4 Rewiring-Bsed Optimiztion Algorithm As demonstrted in the previous setion, rewiring opertions my, indeed, redue the SER of iruit. Furthermore, rewiring opertions hve previously lso een shown to signifintly improve re, power onsumption, dely, nd testility [3, 4,, 6, ]. Bsed on these oservtions, in this setion we devise n lgorithm tht itertively selets effetive rewiring opertions nd evolves the iruit implementtion in order to optimize ost funtion refleting given set of design ojetives. The seletion of n optiml set of rewiring opertions is NP-omplete nd, thus, omputtionlly infesile. In the proposed lgorithm, we follow simple greedy heuristi, wherein, t eh step, rewiring is ttempted for the wire with the highest Psens in the iruit tht hs not een tried so fr. In order to identify the most suseptile wire, we employ fult simultion of rndom ptterns nd ompute the Psens for eh wire y tking the rtio of the numer of times tht fults on the wire re sensitized to n output over the numer of simulted input ptterns. Then, the list of wires is sorted (SortWires() in deresing order of their Psen, nd the first wire in the list is seleted s trget wire (TrgetWire). One the trget wire is seleted, we perform rewiring using the four design error models of Fig. nd the DEDC lgorithm genertes list of ki orretions to fix the design. For eh ndidte orretion j, we onstrut the orreted ir- Figure. Flowhrt of the Proposed Algorithm uit (Designi ), evlute the ost funtion (CFi;y), nd keep the design (Design,,t) tht hs the est improvement to the ost funtion (CFest) over the previous design (Designld). The proess is itertively repeted until ll the wires hve een tried without improvement to the ost funtion. The lgorithm is summrized in Fig.. Experimentl Results In this setion, we evlute experimentlly the SER redution nd ssoited overheds for the proposed rewiringsed design spe explortion method. First, in setion., we desrie the setup of the experiments. Next, in setion.2, we disuss four ost funtions tht we used to drive the optimiztion lgorithm in our experiments. Then, in setion.3, we present, nlyze, nd ompre the results for these ost funtions. Finlly, in setion.4, we disuss the shortomings of existing SER estimtion tools, eluding to the ft tht the effetiveness nd slility of rewiring-sed SER redution will drstilly improve s these tools mture.

6 . Experimentl Setup We experiment with set of ISCAS'89 nd ITC'99 enhmrk iruits. The SER is omputed using SERA [], whih ounts for the rewiring effet on RSET, Pserns nd Plth, nd reports the SER for eh output of the iruit. The re overhed is omputed sed on trnsistor ounts of the originl nd finl iruits. Power nd dely overhed omputtion is performed using SIS []. The internl BDD-sed power simultor in SIS is used to ompute the power overhed ssuming zero-dely model. The iruit is, then, mpped to the stndrd li2.genli lirry, nd the dely of the most ritil pth is used for omputing the dely overhed. Finlly, ATALANTA [28] is used to perform Automti Test Pttern Genertion (ATPG) nd ompute ny loss in fult overge during prodution testing. Finlly, the funtion JointOptimiztion enles the joint optimiztion of ll the design prmeters, with the ility to prioritize the vrious optimiztion ojetives using different weights for the orresponding design prmeters. Thus, it enles the designer to optimize the overhed of the design sed on the trget pplition of the produt. The JointOptimiztion ost funtion is defined s: JointOptimiztion wi - mx{wl improu(ser) (4) + w2* improv(are) H w3* improv(dely) H w4 * improv(power) H w* irnprov(testility)} i=.2 Optimiztion Cost Funtions where < Rewiring hs lredy een shown to e effetive in optimizing re, power, dely nd testility [3, 4,, 6, ]. Therefore, we minly fous on ost funtions tht redue the SER while vrying the onstrints pled on the other design prmeters. Thus, the first ost funtion we onsider ims t minimizing the soft error rte, regrdless of the impt of rewiring on the other design prmeters suh s re, dely, power nd testility. Let improv(x) e funtion tht returns the rtio etween prmeter x of the initil iruit over the sme prmeter of the iruit fter the rewiring opertion. Then, the first ost funtion, lled OnlySER, n e expressed s: these experiments to w, =., w2 = W3 = W4 =., nd W =.2, giving higher priority to the SER redution nd the improvement in testility of iruit implementtion over the redution in re, dely nd power onsumption. While we only present results using the ove four ost funtions, ny other ost funtion n e used to drive the serh lgorithm refleting the onstrints pled y the designer on the overhed of the finl design. OnlySER mx{improv(ser)} () The seond ost funtion, lled SERndTest, ims t reduing the SER of the iruit s long s no dditionl untestle fults re introdued in the iruit fter the rewiring opertion. Hene, the SERndTest ost funtion n e represented s: mx{improv (SER) } SERndTest improu(testility) > Sujet to: The third ost funtion, lled SERndAll, redues the SER s long s ll the design prmeters of the modified iruit fter the rewiring opertion re etter thn or equl to the design prmeters of the initil iruit. The SERndAII ost funtion is defined s: SERndAII Sujet to: mx{improv(ser)i} improv(testility) (3) improv(are) > improv(dely) > improv(power) > > < nde wi =. The weights were set in.3 Anlysis nd Comprison The results re presented in Tle for the OnlySER nd SERndTest ost funtions, nd in Tle 2 for the SERndAll nd JointOptimiztion ost funtions, respetively. Under the first mjor heding, we provide detils out the iruits tht were used: nme, numer of primry inputs, numer of primry outputs, nd gte ount. Under the next two mjor olumns, we report the perentile SER redution2, re overhed, power overhed, dely overhed, nd fult overge loss for the OnlySER nd SERndTest ost funtions (SERndAlI nd JointOptimiztion ost funtions) in Tle (Tle 2), respetively. The key points reveled y these results re summrized elow: * The results for OnlySER indite tht rewiring n redue sustntilly the SER of the iruit. For exmple, the SER of Ol, O6 nd s is redued y more thn %. However, when the serh is driven y the sole ojetive of reduing SER, the impt of rewiring on other design prmeters suh s re, power, dely, nd testility n e signifint. For exmple, the dely of O6 nd s inreses y more thn 4%. 2We note tht the omputtion of SER redution tkes into ount ll possile SET lotions, inluding the ones in the dditionl re inurred y the rewiring method, if ny. 6

7 Nme Ol O2 O3 O6 O8 9 lo s298 s382 s344 s349 s s444 s Originl Ciruit PI P Gtes SER.62%.63%.9%.9% 9.94%.4% 2.42% 2.4% 9.3%.4%.%.% 4.2%.39% Are 8.29% 9.3%.4% 22.3% 2.2% 2.9%.% -3.69% 8.2% 2.6% 6.96%.%.99% 2.4% OnlySER Dely 4.92% 29.3% 3.2%.6% 62.99% 4.86% 48.% 6.3% 3.6%.62% -.% -8.49% -9.8% 48.% Power -.92% -6.2%.% -.93%.94% -.63%.% 6.8% -9.42% 29.%.% -8.% -.8%.% F. C. Loss 4.3% 3.% 9.%.% 2.8%.3%.8%.% 6.2%.2% 3.% 6.29%.3% SER.4%.66%.9% 9.84% 2.%.6%.44% 4.9% 4.% 3.2%.8% 8.22% 2.9%.3% Are.32% 6.98%.4%.9%.34% -.48%.92% -.39%.86% -3.2% -.28% 2.8% SERndTest Dely -2.8% 3.2% -6.% 3.6% -2.% 22.23% -.99% -2.89% -.98% 2.2%.4% -.3% 8.2% Power -3.% -2.69%.% -28.% -.68% -8.89% -.6% -.3% -.6%.%.36% % -.9%.42% F. C. Loss Tle. Experimentl Results on ISCAS89 & ITC99 Benhmrk Ciruits (OnlySER nd SERndTest) Nme Ol O2 O3 O6 O8 O9 lo s298 s382 s344 s349 s s444 s Originl Ciruit PI PO Gtes SER.6%.%.% 3.6% 6.46%.32% 2.%.%.% 3.2% 6.3%.62% 8.98% Are -.8% -.4% -.9% -.% -.63% -.86% -4.68% -.% SERndAll Dely -8.8% -2.3% -.93% -4.46% -3.% -.% -8.% -4.3% -.84% -2.3% -4.2% -.48% -4.6% Power E C. Loss -6.2% -.32% -3.4% -9.33% -2.6% -3.9% -.36% -2.% -.6% -.64% -4.9% -.8% -3.% SER 9.93%.44% 3.84% 9.9% 2.68%.28%.88%.%.4%.49% 2.9%.2% 9.%.3% JointOptimiztion Are.22%.9%.3% 6.4% 3.% -6.% -.32%.49%.4% 2.86%.6% 4.2% Dely -4.4% -9.%.8% -.49% -.% -.43% -8.48% -3.% -3.3% -.6% -3.9% -6.84% -.2% Power -.22% -2.63% -.8% -2.3% -.84% -2.94%.38% -9.8% -9.3% 2.64% -6.69% -.6% -2.68% -.89% F.C. Loss.92%.94%.84%.96%.29%.8%.4% 2.8% Tle 2. Experimentl Results on ISCAS89 & ITC99 Benhmrk Ciruits (SERndAll nd JointOpltimizltion) * By monitoring the impt on other design prmeters during the serh lgorithm, we n moderte its effet. The results for SERndTest indite tht when no fult overge loss is llowed during rewiring, the SER of the iruit n still e signifintly redued. For exmple, this is the se for O6 nd s298. While this redution is smller thn in the OnlySER se, the impt on the remining design prmeters, i.e. re, dely, nd power, is lso less severe. * Even when the serh lgorithm is onstrined to only llow rewiring opertions tht do not use negtive impt to ny of the design prmeters, the SER of the iruit is still redued, s indited y the results for the SERndAIl ost funtion. As expeted, however, the dditionl onstrints pled on the serh lgorithm diminish the ttined SER redution. Nevertheless, this redution is overhed-free nd, s suh, highly desirle. Moreover, this onstrined design-spe explo- rtion often results in signifint redution in one or more of these design prmeters. For exmple, the dely of O9 is redued y more thn 2%G, nd the re overhed of O6 is redued y %. * When design prmeters re used s n inherent prt of the ost funtion, rther thn onstrints, logi rewiring enles more effiient explortion of the design spe of the iruit under optimiztion. This is demonstrted through the results for JointOptimiztion, where SER is given the highest weight during the serh, testility is given the next highest weight, nd re, power, nd dely re given the smllest weight. As result, the finl rewired iruit exhiits high SER redution nd miniml loss in fult overge, while moderte impt -either positive or negtive- is effeted on re, power, nd dely. For exmple, the SER of iruits O9, s382 nd s is redued y more thn O% while the overhed of other design prmeters is lso redued.

8 .4 Disussion 3 The ove results demonstrte tht rewiring n indeed e used to redue the SER of logi iruit nd to filitte ommon optimiztion frmework for logi-level designspe explortion. While the ttined SER redution is signifint, we would like to point out tht it is very onservtive nd pessimisti indition of wht rewiring n hieve. The underlying reson for this hs to do with limittions relted to SERA, the SER ssessment tool tht we used in our experiments. To the est of our knowledge, SERA is the only puli-domin SER estimtion tool, whih is the reson for using it. SERA supports generi.8um CMOS lirry omposed of stndrd gtes tht hve mximum of three inputs. Therefore, in order to ssess the SER of iruit tht utilizes gtes with more thn three inputs, we need to split these gtes into n equivlent struture tht only uses gtes with mximum of three inputs. Suh deomposition, however, hs very negtive effet. First, the numer of lotions where SETs my our in the iruit inreses. Seond, gte with k inputs hs, in generl, lower proility of msking SETs on its inputs thn the sme type of gte with n inputs, where n > k. Thus, gte deomposition inreses the Psen, nd, y extension, the SER of iruit. To mke things even worse, the limited numer of gte inputs results in fewer rewiring opportunities. This hppens euse the numer of inputs to gte fter rewiring nnot exeed three, therefore preventing lrge numer of potentil orretions from eing onsidered. Overll, the potentil of rewiring in reduing Psens is preluded y the input width of the ville gtes. Hene, the results reported herein reflet very onservtively the SER redution tht rewiring would hieve on the enhmrk iruits, should lirry of gtes with more thn three inputs e supported y SERA. Our onjeture is tht the SER redution hieved y rewiring on logi iruit onstruted out of gtes with up to n inputs is higher thn the SER redution of rewiring on logi iruit onstruted out of gtes with up to k inputs, where k < n. To support this lim, we plot in Fig. 6 the SER redution otined when the lirry is restrited to 2input gtes only, long with the SER redution when the lirry is restrited to ll of the supported gtes in the lirry of SERA (i.e. oth 2-input nd 3-input gtes), for severl enhmrk iruits. As n e seen from the figure, the SER redution otined using 2-input gtes only is, on verge, 6.46% of the SER redution otined using 2-input nd 3-input gtes. This result orroortes the onjeture tht rewiring-sed SER redution is expeted to inrese if the supported lirry ontins wider gtes. As finl note, we would like to omment on the ury nd slility of our method to ddress the onerns of the oservnt reder who my hve notied tht results for the lrger of the ISCAS'89 nd ITC'99 enhmrks re not inluded in the experiments. The optimiztion lgorithm relies - ~ ~ ~ ~~UD2-Input nd 3-Input Gtes 2-Input Gtes W ~~~ 3-3 n U - 2 Ol O6 s382 s444 Figure 6. Comprison Between the SER Redution Ahieved y Rewiring Using 2-input Gtes Only v.s. Using 2-Input nd 3-Input Gtes. on two distint tools, rewiring tool nd n SER estimtion tool. In its present form, the lgorithm employs the ATPGsed method desried in [22] for rewiring nd SERA [] for SER estimtion. The ury of the SER redution results depends on the pproximtion nd estimtion methods of the underlying SER estimtion tool. In terms of slility, ATPG-sed rewiring hs een shown to require less thn seond to perform rewiring for iruits with more thn 3K gtes [22], so slility is not onern. SERA, on the other hnd, requires signifint mount of time for lrger iruits, hene the lk of results for suh enhmrks. However, development of SER estimtion tools hs een very tive reserh re in reent yers [3,, 6, 4]. As these tools mture nd eome more effiient, methods employing them, suh s the rewiring-sed SER redution desried in this pper, will lso e positively ffeted. 6 Conlusion In ddition to the vrious design prmeters tht rewiring hs een shown to improve in the pst, this work demonstrted tht rewiring n lso e used to redue the SER of iruit. Thus, rewiring provides n exellent sis for onstruting unified optimiztion frmework for exploring the trde-offs etween re, power onsumption, dely, testility, nd SER. To this end, we desried n ATPG-sed rewiring method tht genertes funtionlly-equivlent yet struturlly-different implementtions of logi iruit using set of simple trnsformtion rules. We demonstrted how these trnsformtions result in iruit implementtions with redued SER nd we presented serh lgorithm tht itertively evolves design in order to stisfy given set of design ojetives. Experimentl results on ISCAS'89 nd ITC'99 enhmrk iruits verify tht SER redution n e semlessly nd effetively integrted in the list of ojetives supported y rewiring-sed design-spe explortion. 8

9 Referenes [4] W. Kunz, D. Stoffel, nd P. R. Menon, "Logi optimiztion nd equivlene heking y implition nlysis,"' IEEE [] P. Shivkumr, M. Kistler, S. W. Kekler, D. Burger, nd L. Alvisi, "Modeling the effet of tehnology trends on the soft error rte of omintionl logi," in Interntionl Conferene on Dependle Systems nd Networks, 22, pp [2] M. Oke, M. Ttsuki, Y. Arim, T. Hiro, nd Y. Kurmitsu, "Design for reduing lph-prtile-indued soft errors in ECL logi iruitry," IEEE Journl of Solid-Stte Ciruits, vol., no., pp , 989. [3] Y. S. Dhillon, A. U. Diril, A. Chtterjee, nd A. D. Singh, "Sizing CMOS iruits for inresed trnsient error tolerne.," in IEEE Interntionl On-Line Testing Symposium,,pp.-6. [4] Q. Zhou nd K. Mohnrm, "Cost-effetive rdition hrdening tehnique for logi iruits,"' in IEEE/ACM Interntionl Conferene on Computer-Aided Design,, pp. -6. [] H. Deogun, D. Sylvester, nd D. Bluw, "Gte-level mitigtion tehniques for neutron-indued soft error rte,"' in ACM/IEEE Interntionl Symposium on Qulity Eletroni Design,, pp. -8. [6] S. Krishnmohn nd N. R. Mhptr, "Comining error msking nd error detetion plus reovery to omt soft errors in stti CMOS iruits," in Interntionl Conferene on Dependle Systems nd Networks,, pp [] S. Mitr, M. Zhng, T.M. Mk, N. Seifert, V. Zi, nd K.S. Kim, "Logi soft errors: A mjor rrier to roust pltform design," in Interntionl Test Conferene,, pp [8] C. Zho, X. Bi, nd S. Dey, "A slle soft spot nlysis methodology for noise effets in nno-meter iruits," in ACM/IEEE onferene on Design utomtion,, pp [9] Y. S. Dhillon, U. Diril, nd A. Chtterjee, "Soft-error tolerne nlysis nd optimiztion of nnometer iruits," in Design, Automtion nd Test in Europe,, pp [] S. Krishnswmy, G. F. Vimonte, I. L. Mrkov, nd J. P. Hyes, "Aurte reliility evlution nd enhnement vi proilisti trnsfer mtries," in Design, Automtion nd Test in Europe,, pp [] N. Miskov-Zivnov nd D. Mrulesu, "MARS-C: Modeling nd redution of soft errors in omintionl iruits," in Design Automtion Conferene, To Apper,. [2] S. C. Chng, K. T. Cheng, N. S. Woo, nd M. MrekSdowsk, "Postlyout logi restruturing using lterntive wires,"' IEEE Trnstions on Computer-Aided Design of Integrted Ciruits nd Systems, vol. 6, no. 6, pp. 8-96, 99. [3] L. A. Entren nd K. T. Cheng, "Comintionl nd sequentil logi optimiztion y redundny ddition nd removl," IEEE Trnstions on Computer-Aided Design of Integrted Ciruits nd Systems, vol. 4, no., pp , 99. [] [6] [] [L8] [9] [2] [2] [22] [23] [] [] [] [] [28] Trnstions on Computer-Aided Design of Integrted Ciruits nd Systems, vol. 6, no. 3, pp. 6-28, 99. B. Rohfleish, A. Koll, nd B Wurth, "Reduing power dissiption fter tehnology mpping y struturl nlysis," in Design Automtion Conferene, 996, pp Y. M. Jing, A. Krsti, K. T. Cheng, nd M. Mrek-Sdowsk, "Postlyout logi restruturing for performne optimiztion,"' in Design Automtion Conferene, 99, pp G. Stenz, B. M. Riess, B. Rohfleish, nd F. M. Johnnes, "Performne optimiztion y interting netlist trnsformtions nd plement,"' IEEE Trnstions on Computer-Aided Design ofintegrted Ciruits nd Systems, vol. 9, no. 3, pp. 3-38, 2. M. Chtterjee, D. Prdhn, nd W. Kunz, "LOT: Logi optimiztion with testility - new trnsformtions using reursive lerning,"' in IEEE/ACM Interntionl Conferene on Computer-Aided Design, 99, pp. -8. S. Ymshit, H. Swd, nd A. Ngoy, "SPFD: A new method to express funtionl flexiility," IEEE Trnstions on Computer-Aided Design of Integrted Ciruits nd Systems, vol. 9, no. 8, pp , 2. S. P. Khtri, S. Sinh, R. K. Bryton, nd A. SngiovnniVinentelli, "SPFD-sed wire removl in stndrd-ell nd network-of-pla iruits," IEEE Trnstions on ComputerAided Design ofintegrted Ciruits nd Systems, vol. 23, no., pp. 2-3,. J. Cong, J. Y. Lin, nd W. Long, "A new enhned SPFD rewiring lgorithm,"' in IEEE/ACM Interntionl Conferene on Computer-Aided Design, 22, pp A. Veneris nd M. Adir, "Design Rewiring Using ATPG," IEEE Trnstions on Computer-Aided Design of Integrted Ciruits nd Systems, vol. 2, no. 2, pp , 22. M. S. Adir, J. Ferguson, nd T. E. Kirklnd, "Logi Verifition vi Test Genertion,," IEEE Trnstions on Computer-Aided Design of Integrted Ciruits nd Systems, vol., no., pp , 988. A. Veneris nd I. N. Hjj, "Design Error Dignosis nd Corretion Vi Test Vetor Simultion," IEEE Trnstions on Computer-Aided Design of Integrted Ciruits nd Systems, vol. 8, no. 2, pp , 999. K. Mohnrm nd N. A. Tou, "Cost-effetive pproh for reduing soft error filure rte in logi iruits," in Interntionl Test Conferene, 23, pp M. Zhng nd N. R. Shnhg, "A soft error rte nlysis (SERA) methodology," in IEEE/ACM Interntionl Conferene on Computer-Aided Design,, pp. 8. E. M. Sentovih et l., "SIS: system for sequentil iruit synthesis," ERL MEMO. No. UCB/ERL M92/4, EECS UC Berkeley CA 942, 992. H. K. Lee nd D. S. H, "Atlnt: n effiient ATPG for omintionl iruits," Tehnil Report, 93-2, Deprtment of Eletril Engineering, Virgini Polytehni Institute nd Stte University,