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1 Wijnhoven, T.; Deonink, G., "Flexile fult urrent ontriution with inverter interfed distriuted genertion," in IEEE Power nd Energy Soiety Generl Meeting (PES), Vnouver, BC, Cnd, -5 July, 5 p. doi:.9/pesmg URL: mer=66765 IEEE. Personl use of this mteril is permitted. Permission from IEEE must e otined for ll other users, inluding reprinting/ repulishing this mteril for dvertising or promotionl purposes, reting new olletive works for resle or redistriution to servers or lists, or reuse of ny opyrighted omponents of this work in other works. (elow follows the epted version)

2 Flexile fult urrent ontriution with inverter interfed distriuted genertion Thoms Wijnhoven, GSM, IEEE, nd Geert Deonink, SM, IEEE ELECTA, Deprtment of Eletril Engineering, KU Leuven, Belgium Astrt This pper desries ontrol sheme to flexily ontrol the positive nd negtive sequene fult urrent ontriution of inverter interfed distriuted genertion (IIDG). This flexile ontrol n e enefiil to limit the impt of distriuted genertion (DG) on existing grids. This wy, lrge sle integrtion of DG eomes possile in existing grids. A doule synhronous referene frme (DSRF) ontrol strtegy is hosen. The phse loked loop (PLL) nd urrent ontroller re sed on ville tehniques nd re desried riefly. The performne of the ontrol system is illustrted in PSCAD simultion environment. Both symmetril nd symmetril fults re pplied on generi Europen medium voltge grid. Only the setpoints during fults hve to e hnged to otin speifi fult response, reting the required flexiility. Index Terms distriuted power genertion, fult urrents, inverter, power system protetion I. INTRODUCTION Comined het nd power (CHP) units, wind turines nd solr instlltions re often instlled ner onsumers nd ner open spes, nd their lotion is not determined y the presene of suitle high voltge (HV) grid onnetion point. By integrting them in neighouring distriution grids, ostly HV grid onnetion n e voided nd distriuted genertors (DG s) eome more ost effiient. If lrge mounts of DG ould e integrted in existing grids, this would enle ost effiient (intermedite) step towrds lower ron, more renewle power system for the st entury. In this pper, inverter interfed distriuted genertors (IIDG s) re onsidered, s their power eletroni interfe llows flexile ontrol of the DG. More speifilly, the retion of IIDG s during grid fults is onsidered. It is shown tht it is possile to ontrol the positive nd negtive sequene fult urrent response within time frme tht is relevnt for the protetion system. The pper is orgnised s follows: Setion II desries phse loked loop (PLL) strutures tht re le to give n urte estimtion of positive nd negtive sequene ngles. Both ngles re required for the urrent ontroller in the doule synhronous referene frme (DSRF) tht is explined in setion III. Finlly, in setion IV this ontrol system is evluted in simultions of smll medium voltge (MV) network to illustrte its performne nd its pilities. T. Wijnhoven hs Ph. D. fellowship of the Reserh Foundtion - Flnders (FWO) nd wishes to knowledge the finnil support of the FWO. E-mil ontt: thoms.wijnhoven@est.kuleuven.e II. PLL DURING FAULTS In generl, the only grid informtion DG unit hs, is its lol voltge nd frequeny. Only when the phse ngles of the positive nd negtive sequene voltge t the point of ommon oupling (PCC) re known, DG is le to injet speifi mount of tive (in-phse) nd retive (qudrture) positive/negtive sequene urrent. Sine DSRF ontroller will e used in setion III, PLL is required to trk the phse ngles. During fult situtions, positive, negtive nd zero sequene voltges pper. Using stndrd (positive sequene) PLL strutures results in d estimtion of the positive sequene ngle []. Severl methods to seprte positive nd negtive sequene fundmentl frequeny omponents hve een developed nd re desried in literture [] [5]. The positive sequene ngle n then e determined from the positive sequene voltge with stndrd PLL. The fundmentl frequeny negtive sequene ngle θ is relted to this positive sequene ngle θ + y eqution, where γ is onstnt in stedy stte. The zero sequene ngle is usully not required, ut n e determined with stndrd PLL fter using eqution to determine the zero sequene voltge. θ = θ + + γ () u = (u + u + u ) () The min ide of the different methods is to pply filter to otin the fundmentl frequeny omponents nd 9 degree phse shifted signl. Afterwrds, the instntneous symmetril omponents trnsformtion, s desried in [6], n e pplied. These methods differ in speed (with respet to hnges) nd in roustness (with respet to hrmoni distortion). In this pper, the seprtion of positive nd negtive sequene omponents is mde fter the Clrke trnsformtion ( αβ), similr to [5]. Although more dvned filtering tehniques hve etter performne with distorted voltge signls, this simple delyed signl method ws hosen in this pper euse hrmoni distortions only ply minor role in the simultions performed in setion IV. III. CURRENT CONTROLLER After PLL is onstruted, the positive nd negtive sequene phse ngles re known. As [7] pointed out, DSRF ontroller is ple of ontrolling voltge soure onverter s positive nd negtive sequene urrents. In Fig. the generl struture of DSRF urrent ontroller is shown. First,

3 i dq+ + Hz F SRF v dq+ i dqi dq+ θ + i dq+, SP -θ + Lfilter IIDG /5 5/.69 U grid U inv i i αβ v αβ v,ref i θ - i dq- + Hz F SRF v dqi dq-, SP -θ - Fig.. θ + i αβ Generl priniple of DSRF urrent ontroller i dq- + Hz SRF v dqi dq+, SP i dq+ + Hz SRF v dq+ θ - v αβ Fig.. i dqi dq+ θ + -θ - Δi dqθ - -θ F F Δi dq+ i dq-, SP -θ + -θ - Priniple of the deoupled DSRF urrent ontroller v,ref Clrke ( αβ) trnsformtion is pplied. Afterwrds, two synhronous referene frmes re mde y trnsforming these urrents to the positive sequene synhronous referene frme (with ngle θ + ) nd to the negtive sequene synhronous referene frme (with ngle θ ). This mens tht the totl urrent is trnsformed to oth referene frmes. Therefore, there is DC omponent, the positive sequene urrent, nd seond hrmoni omponent ( Hz for nominl grid frequeny of 5 Hz) in the positive sequene referene frme. Likewise, the negtive sequene frme ontins DC omponent, the negtive sequene urrent, nd seond hrmoni omponent. By removing the seond hrmoni omponents with nd stop filter (see Fig. : F ), lssi DC ontrol system n e uilt to ontrol the positive nd negtive sequene urrents towrds their setpoints i dq+,sp nd i dq-,sp (see Fig. : SRF ). This mens tht simple PI ontrollers n e used to void stedy stte errors. The referene signl for the onverter, v,ref, is lulted y trnsforming the positive nd negtive sequene referene frmes k to the sttionry frme, dding oth nd pplying the inverse Clrke trnsformtion (see Fig. ). However, the nd stop filters, tht were used in [7] to suppress the positive sequene omponents in the negtive sequene frme nd vie vers, led to phse dely nd instility of the ontroller when fst urrent ontrol is required [8]. This results in reltively slow urrent ontrol, unsuitle for the purposes of fult urrent ontrol within few fundmentl periods ( ms). Reyes et l. [9] reently developed n interesting deoupled Fig.. Grid model TABLE I GRID DATA Element Property Vlue HV grid Rted voltge (L-L) kv Short-iruit power MVA X/R rtio Frequeny 5 Hz MV trnsformer Rting 4 MVA Voltge rtio kv / 5 kv Connetion Yd Impedne voltge % Copper losses.5% LV trnsformer Rting MVA Voltge rtio 5 kv / 69 V Connetion Dy (solidly erthed) Impedne voltge 6% Copper losses.95% Inverter Rting kva DC voltge 65 V (onstnt) Filter L mh R mω DSRF urrent ontroller. This ontroller no longer uses nd stop filters, ut insted uses deoupling system to remove the seond hrmoni omponents in the positive nd negtive sequene ontrol frmes. This method ws pplied here nd its priniple is illustrted in Fig.. The feedk filters for the error signls i dq+ nd i dq- in the deoupling loop (see Fig. : F ), were tuned to otin fster urrent ontrol, even for high power ( MVA) IIDG. More detils out the deoupled DSRF sheme re found in [9]. IV. ILLUSTRATION OF FLEXIBLE FAULT CURRENT A. Simultion model CONTROL The simultion model is uilt in PSCAD. Fig. shows the grid model tht is used nd tle I summrizes the grid properties. The MV voltge level ws hosen to e 5 kv. Any voltge round - kv is relisti for Europen MV distriution networks: e.g. the CIGRE enhmrk grid for integrting DG in MV distriution networks is sed on Germn MV grid nd hs voltge level of kv [], while other studies of Europen MV grids hve lower voltge levels: kv in the Netherlnds [] nd kv in the UK []. The IIDG is onneted to 69 V nd is modelled s n verged vlue model (AVM) []. It uses the PLL nd deoupled DSRF urrent ontroller tht re desried in the previous setions II nd III. In situtions without negtive

4 sequene voltge, the inverse of the positive sequene phse ngle is used for the negtive sequene phse ngle, though this pproh is not orret if the gol is to ontrol the inphse nd qudrture negtive sequene urrents individully. Therefore, the negtive sequene phse ngle is trked y the PLL when there is negtive sequene voltge. As n dditionl simplifition the DC us voltge is kept onstnt. This llows evluting the performne of the deoupled DSRF urrent ontroller without onsidering the impt of the DC us voltge in the simultions. This DC us voltge is hosen reltively high euse of two resons: ) Pulse width modultion is hosen (s opposed to spe vetor modultion) ) The IIDG must e ple of delivering % retive urrent (see eqution, with U inv nd U grid s indited in Fig. nd U d the required DC us voltge) U inv = I inv Z filter + U grid = 674 e j π (. + j.4) + 69 U d = U inv = 64 V () B. Two phse fult t LV In ll simultions, the IIDG is delivering hlf of its rted urrent with power ftor equl to.95 efore the fult (P =.95 MW, Q =. MVAr). Then, in the first simultion, n idel two phse fult (R fult Ω) is pplied t the low voltge (LV) side of the step-up trnsformer t t = 5 s nd the fult is removed t t = 5. s. Only the filter impedne is etween the fult nd the IIDG. To illustrte tht the IIDG n ret in rndom wy, three different urrent setpoint strtegies re pplied. All strtegies hnge the urrent setpoints during the fult, sed on the positive nd negtive sequene voltge mesured y the PLL. In strtegy A (Fig. 4), only positive sequene urrents re injeted (mximl retive urrent). Fig. 4-4 show the grid voltges t LV nd MV efore nd during the fult. Fig. 4 shows the voltges s mesured y the PLL (positive nd negtive sequene voltge re equl t the lotion of the fult) nd Fig. 4d gives the setpoints of the urrent ontroller efore, during nd fter the fult. Fig. 4e then gives the inverter output urrent. As n e seen, oth the settling time t the strt (t = 5 s) nd t the end (t = 5. s) of the fult re very fst. The PLL voltges hve fst settling time, ut exhiit some trnsients. In strtegy B (Fig. 5), other setpoints re hosen during the fult: the negtive sequene qudrture urrent is relted to the negtive sequene voltge ording to eqution 4 nd the positive sequene in-phse urrent is redued during fults. = u d u d+ (4) In strtegy C (Fig. 6), the urrent setpoints re unltered during the fult. For oth strtegy B nd C, the voltge during the fult is not shown s it is very similr to strtegy A. This is voltge [kv] voltge [kv] () u d+ () u d voltge [kv] () (e) Fig. 4. Two phse fult t LV, strtegy A (no negtive sequene urrent injetion): () Voltge t the LV side nd () t the MV side of the stepup trnsformer. () Positive nd negtive sequene voltge s mesured y the PLL. (d) Setpoints (in the synhronous referene frmes) of ll sequene omponents. (e) Inverter output urrent t LV (efore the step-up trnsformer) () (d) Fig. 5. Two phse fult t LV, strtegy B (with negtive sequene urrent injetion): () Inverter output urrent t LV. () Setpoints (in the synhronous referene frmes) of ll sequene omponents. due to the limited short-iruit power of the IIDG ompred to the grid. This topi will e ddressed further in setion IV-F. The fult urrent responses nd the setpoints tht re pplied (see Fig. 5 nd Fig. 6) illustrte tht totlly different fult urrent response, with fst settling time, is otined y pplying different setpoints. This mens tht the fult ehviour n e hnged in flexile wy ording to the grid requirements. ()

5 () Fig. 6. Two phse fult t LV, strtegy C (no hnge in urrent setpoints): () Inverter output urrent t LV. () Setpoints (in the synhronous referene frmes) of ll sequene omponents. () () Fig. 8. Two phse fult t MV, strtegy B (with negtive sequene urrent injetion): () Inverter output urrent t LV. () Setpoints (in the synhronous referene frmes) of ll sequene omponents. () voltge [kv] () () voltge [kv] () Fig. 7. Two phse fult t MV, strtegy A (no negtive sequene urrent injetion): () Voltge t the LV side nd () t the MV side of the step-up trnsformer. () Inverter output urrent t LV. (d) Setpoints (in the synhronous referene frmes) of ll sequene omponents. (d) voltge [kv] () () voltge [kv] () Fig. 9. Three phse fult t MV, strtegy A (no negtive sequene urrent injetion): () Voltge t the LV side nd () t the MV side of the step-up trnsformer. () Inverter output urrent t LV. (d) Setpoints (in the synhronous referene frmes) of ll sequene omponents. (d) C. Two phse fult t MV In the next simultion, n idel two phse fult (R fult Ω) is pplied t the MV side of the step-up trnsformer. The sme setpoint strtegies A nd B re used here nd the results re given in Fig. 7 (strtegy A) nd Fig. 8 (strtegy B). Agin it is shown tht just y pplying different setpoint strtegy during the fult, totlly different fult response is otined. D. Three phse fult t LV The results of the simultion for three phse fult t the LV side of the step-up trnsformer re not shown in this pper. In this se, the voltge t the IIDG is out zero nd the PLL is unle to trk the phse ngles. Beuse most fults t the LV side of the step-up trnsformer re permnent, these fults will usully require disonnetion of the IIDG from the grid. In other ses, the IIDG s inverter should e loked nd kept off-line to restrt s soon s the voltge is normlised gin. E. Three phse fult t MV Next, three phse fult is pplied t the MV level (R fult =.5 Ω). In this fult se, there is no negtive sequene voltge. Two different strtegies re shown: strtegy A (Fig. 9) is the sme s in the previous ses, ut strtegy B (Fig. ) is ltered to illustrte the flexiility of the ontrol sheme. Here, the injeted qudrture negtive sequene urrent during fult is set to e the sme s the qudrture positive sequene urrent. In these simultions, the PLL settling time is it lrger, whih is notiele in the injeted urrents of oth Fig. 9 nd Fig.. The fult response of the ltter (strtegy B) is ompletely different from the former (strtegy A), gin demonstrting the flexiility of the ontrol sheme. F. Remrk on fult ontriutions The simultions show the performne of the urrent ontroller nd the flexile fult urrent ontriution of the IIDG. On the MV grid, the impt of one MVA IIDG unit is very

6 () Fig.. Three phse fult t MV, strtegy B (with negtive sequene urrent injetion): () Inverter output urrent t LV. () Setpoints (in the synhronous referene frmes) of ll sequene omponents () () Fig.. Exmples of the fult urrent responses on MV: () MV fult urrent ontriution of the IIDG for two phse fult t MV (strtegy B) nd () for three phse fult t MV (strtegy A). limited, s it n only deliver out 77 A without overloding the IGBT s of the inverter. Fig. shows two exmples of the limited MV urrent ontriution of the IIDG during MV fult. The simulted MV grid hs short-iruit levels of out ka. Therefore, the urrent ontriution of IIDG n e onsidered s not importnt t tody s low integrtion levels, whih is in line with the onlusions of []. In future grids, with high mounts of DG s in the MV grid, these onlusions hve to e verified. The impt of the IIDG will lso inrese if the short-iruit levels of the MV grid re redued. As ws indited in the introdution, the settling time of the urrent ontroller is well elow ms (5 yles t 5 Hz). For ll protetions tht do not deide immeditely (< ms), this is relevnt nd thus the flexile ontrol is relevnt for the protetion system. The limited fult urrent ontriution n lso e seen s n dvntge. Whenever stndrd DG units (with synhronous or (douly fed) indution genertors) pose integrtion hllenges to the MV grid or when they re unle to omply with fult ride-through (FRT) requirements, IIDG re likely to provide solution. A full evlution of the impt of the different strtegies is outside the sope of this pper nd is prt of future reserh. V. CONCLUSIONS This pper desries urrent ontroller for flexile fult urrent ontriution of IIDG. It ws shown tht, when the phse ngles re trked with n dequte PLL, deoupled DSRF urrent ontroller is ple of flexily ontrolling oth positive nd negtive sequene urrent injetions. () Severl simultions were performed in PSCAD to illustrte the performne of the urrent ontroller. It ws seen tht the ontriution of IIDG to the fult urrents in MV grid is very limited. Even with onsiderle mount of IIDG, protetion prolems seem unlikely. Future work will fous on solutions this flexile ontrol of IIDG fult urrent ontriutions n ring to inrese the mount of DG tht n e integrted in MV distriution grids. ACKNOWLEDGEMENTS The uthors would like to thnk Agusti Ege Alvrez from Cite UPC, Brelon, Spin, who helped implementing the simplified positive / negtive sequene PLL filter during his reserh sty t Elet, KU Leuven. REFERENCES [] P. Rodriguez, J. Pou, J. Bergs, J. I. Cndel, R. P. Burgos, nd D. Boroyevih, Deoupled Doule Synhronous Referene Frme PLL for Power Converters Control, IEEE Trnstions on Power Eletronis, vol., no., pp , Mr. 7. [] G. Somndo nd J. Svensson, Trnsient opertion of grid-onneted voltge soure onverter under unlned voltge onditions, in IEEE 6th Industry Applitions Soiety (IAS) Annul Meeting, vol. 4,, pp [] T. Wijnhoven, J. Tnt, nd G. Deonink, Inverter Modelling Tehniques for Protetion Studies, in rd IEEE Interntionl Symposium on Power Eletronis for Distriuted Genertion Systems (PEDG), Alorg, Denmrk, Jun., pp [4] P. Rodriguez, A. Lun, M. Ciootru, R. Teodoresu, nd F. Bljerg, Advned Grid Synhroniztion System for Power Converters under Unlned nd Distorted Operting Conditions, in IEEE nd Annul Conferene on Industril Eletronis (IECON), Nov. 6, pp [5] J. Svensson, M. Bongiorno, nd A. Snnino, Prtil Implementtion of Delyed Signl Cnelltion Method for Phse-Sequene Seprtion, IEEE Trnstions on Power Delivery, vol., no., pp. 8 6, Jn. 7. [6] M. Irvni nd M. Krimi-Ghrtemni, Online estimtion of stedy stte nd instntneous symmetril omponents, IEE Proeedings - Genertion, Trnsmission nd Distriution, vol. 5, no. 5, pp. 66 6,. [7] H.-S. Song nd K. Nm, Dul urrent ontrol sheme for PWM onverter under unlned input voltge onditions, IEEE Trnstions on Industril Eletronis, vol. 46, no. 5, pp , 999. [8] F. D. Freijedo, A. G. Yepes, O. López, A. Vidl, nd J. Dovl-Gndoy, Three-Phse PLLs With Fst Postfult Retrking nd Stedy-Stte Rejetion of Voltge Unlne nd Hrmonis y Mens of Led Compenstion, IEEE Trnstions on Power Eletronis, vol. 6, no., pp , Jn.. [9] M. Reyes, P. Rodriguez, S. Vzquez, A. Lun, R. Teodoresu, nd J. M. Crrso, Enhned Deoupled Doule Synhronous Referene Frme Current Controller for Unlned Grid-Voltge Conditions, IEEE Trnstions on Power Eletronis, vol. 7, no. 9, pp , Sep.. [] K. Rudion, A. Orths, Z. Styzynski, nd K. Strunz, Design of enhmrk of medium voltge distriution network for investigtion of DG integrtion, in IEEE Power Engineering Soiety Generl Meeting, 6, p. 6. [] E. J. Coster, J. Morren, J. Myrzik, nd W. Kling, Comprison of MV-grid strutures on fult ride through ehvior of MV-onneted DG-units, in CIRED th Interntionl Conferene on Eletriity Distriution, Prgue, 9, p. 4. [] K. Jennett, F. Coffele, nd C. Booth, Comprehensive nd quntittive nlysis of protetion prolems ssoited with inresing penetrtion of inverter-interfed DG, in th IET Interntionl Conferene on Developments in Power Systems Protetion (DPSP ),, p. 6.