Asynchronous Circuits

Transcription

1 Asynhronous Ciruits Mithm Shms Deprtment of Eletril nd Computer Engineering University ofwterloo, Wterloo, Ont, CANADA Jo C. Eergen Sun Mirosystems Lortories Mountin View, CA, USA Mohmed I. Elmsry Deprtment of Eletril nd Computer Engineering University ofwterloo, Wterloo, Ont, CANADA Digitl VLSI iruits re usully lssied into synhronous nd synhronous iruits. Synhronous iruits re generlly ontrolled y glol synhroniztion signls provided y lok. Asynhronous iruits, on the other hnd, do not use suh glol synhroniztion signls. Between these extremes there re vrious hyrids. Digitl iruits in tody's ommeril produts re lmost exlusively synhronous. Despite this ig dierene in populrity, there re numer of resons why synhronous iruits re of interest. In this rtile, we presentriefoverview of synhronous iruits. First we ddress some of the motivtions for designing synhronous iruits. Then, we disuss dierent lsses of synhronous iruits nd riey explin some synhronous design methodologies. Finlly, we present typil synhronous design in detil. 1 Motivtions for Asynhronous Ciruits Throughout the yers reserhers hve hd vrious resons for studying nd uilding synhronous iruits. Some of the often mentioned dvntges of synhronous iruits re speed, low energy dissiption, modulr design, immunity to metstle ehvior, freedom from lok skew, nd low genertion of nd low suseptiility to eletromgneti interferene. We elorte here on some of these potentils nd indite when they hve een demonstrted through omprtive se studies. 1

2 1.1 Speed Speed hs lwys een motivtion for designing synhronous iruits. The min resoning ehind this dvntge is tht synhronous iruits exhiit worst-se ehvior, wheres synhronous iruits exhiit verge-se ehvior. The speed of synhronous iruit is governed y its lok frequeny. The lok period should e lrge enough to ommodte the worst-se propgtion dely in the ritil pth of the iruit, the mximum lok skew, nd sfety ftor due to ututions in the hip frition proess, operting temperture, nd supply voltge. Thus, synhronous iruits exhiit worst-se performne. This worstse ehvior is ditted y the glol lok nd, in spite of the ft tht the worst-se propgtion in mny iruits, prtiulrly rithmeti units, is improle nd my emuh longer thn the verge-se propgtion. Mny synhronous iruits re ontrolled y lolommunitions nd re sed on the priniple of inititing omputtion, witing for its ompletion, nd then inititing the next one. When omputtion is ompleted erly, the next omputtion n strt erly. For this reson, the speed of synhronous iruits equipped with ompletion-detetion mehnisms depend on the omputtion time of the dt eing proessed, not the worst-se timing. Aordingly, suhsynhronous iruits exhiit verge-se performne. An exmple of n synhronous iruit where the verge-se potentil is niely exploited is reported in [1], n synhronous divider tht is twie s fst s its synhronous ounterprt. Nevertheless, to dte, there re few onrete exmples demonstrting tht the verge-se performne of synhronous iruits is higher thn tht of synhronous iruits performing similr funtions. The reson is tht the verge-se performne dvntge is often ounterlned y the overhed in ontrol iruitry nd ompletion-detetion mehnisms. Besides demonstrting the verge-se potentil, there re se studies in whih the speed of n synhronous design is ompred to the speed of orresponding synhronous version. Molnr et l. report se study of n synhronous FIFO tht is every it s fst s ny synhronous FIFO using the sme dt lthes [2]. Furthermore, the synhronous FIFO hs the dditionl enets tht it opertes under lol ontrol nd is esily expndle. At the end of this rtile we give n exmple of FIFO with slightly dierent ontrol iruit. 1.2 Immunity to Metstle Behvior Any iruit with numer of stle sttes lso hs metstle sttes. When suh iruit gets into metstle stte, it n remin there for n indenite period of time efore 2

3 resolving into stle stte [3, 4]. Metstle ehvior ours, for exmple, in iruit primitives tht relize mutul exlusion etween proesses, lled riters, nd omponents tht synhronize independent signls of system, lled synhronizers. Although the proility tht metstle ehvior lsts longer thn period t dereses exponentilly with t, it is possile tht metstle ehvior in synhronous iruit lsts longer thn one lok period. Consequently, when metstle ehvior ours in synhronous iruit, erroneous dt my e smpled t the the omputtion time of the lok pulses. An synhronous iruit dels grefully with metstle ehvior y simply delying the omputtion until the metstle ehvior hs disppered nd the element hs resolved into stle stte. 1.3 Modulrity Modulrity in design is n dvntge exploited y mny synhronous design styles. The si ide is tht n synhronous system is omposed of funtionl modules ommuniting long well-dened interfes. Composing synhronous systems is simply mtter of onneting the proper modules with mthing interfil speitions. The interfil speitions desrie only the sequenes of events tht n tke ple nd do not speify ny restritions on the timing of these events. This hrteristi redues the design time nd omplexity of n synhronous iruit, euse the designer does not hve toworry out the delys inurred in individul modules or the delys inserted y onnetion wires. Designers of synhronous iruits, on the other hnd, often py onsiderle ttention to stisfying the detiled interfil timing speitions. Besides ese of omposility, modulr design lso hs the potentil for etter tehnology migrtion, ese of inrementl improvement, nd reuse of modules [5]. Here the ide is tht n synhronous system dpts itself more esily to the dvnes in tehnology. The osolete prts of n synhronous system n e repled with new prts to improve system performne. Synhronous systems nnot tke dvntge of new prts s esily, euse they must e operted with the old lok frequeny or other modules must e redesigned to operte t the new lok frequeny. One of the erliest projets tht exploited modulrity in designing synhronous iruits is the Mromodules projet [6]. Another nie exmple where modulr design hs een demonstrted is the TANGRAM ompiler developed t Philips Reserh Lortories [7]. 3

4 1.4 Low Power Due to rpid growth in the use of portle equipment nd the trend in high-performne proessors towrds unmngele power dissiption, energy eieny hs eome ruil in VLSI design. Asynhronous iruits re ttrtive for energy-eient designs, minly euse of the elimintion of the lok. In systems with glol lok, ll of the lthes nd registers operte nd onsume dynmi energy during eh lok pulse, in spite of the ft tht mny of those lthes nd registers might nothve new dt to store. There is no suh wste of energy in synhronous iruits, euse omputtions re initited only when they need to e done. Two notle exmples tht demonstrted the potentil of synhronous iruits when in energy-eient design re the work done t Philips Reserh Lortories nd t Mnhester University. The Philips group designed fully synhronous digitl ompt-ssette (DCC) error detetor whih onsumed 80% less energy thn similr synhronous version [8]. The AMULET group t Mnhester University suessfully implemented n synhronous version of the ARM miroproessor, one of the most energy-eient synhronous miroproessors. The synhronous version hieved power dissiption omprle to the fourth genertion of ARM, round 150 mw [9], in similr tehnology. Reently, power mngement tehniques re eing used in synhronous systems to turn the lok on nd o onditionlly. However, these tehniques re only worthwhile implementing t the level of funtionl units or higher. Besides, the omponents tht monitor the environment for swithing the lok ontinue dissipting energy. It is lso worth mentioning tht unlike synhronous iruits, most synhronous iruits do not wste energy on hzrds, whih re spurious hnges in signl. Asynhronous iruits re essentilly designed to e hzrd-free. Hzrds n e responsile for up to 40% of energy loss in synhronous iruits [10]. 1.5 Freedom from Clok Skew Beuse synhronous iruits generlly do not hve loks, they do not hve mny of the prolems ssoited with loks. One suh prolem is lok skew, the tehnil term for the mximum dierene in lok rrivl time t dierent prts of iruit. In synhronous iruits, it is ruil tht ll modules operting with ommon lok reeive this signl simultneously, tht is, within tolerle period of time. Minimizing lok skew is diult prolem for lrge iruits. Vrious tehniques hve een proposed to ontrol lok skew, ut 4

5 generlly they re expensive in terms of silion re nd energy dissiption. For instne, the lok distriution network of the DEC Alph, 200 MHz miroproessor t 3.3 V supply, oupies 10% of the hip re nd hs 40% shre in the totl hip power onsumption [11]. Although synhronous iruits do not hve thelokskew prolem, they hve their own set of prolems in minimizing the overhed needed for synhroniztion mong the prts. 2 Models nd Methodologies There re mny models nd methodologies for nlyzing nd designing synhronous iruits. Asynhronous iruits n e tegorized y the following riteri: signling protool nd dt enoding, underlying dely model, mode of opertion, nd formlism for speifying nd designing iruits. This setion presents n informl explntion of these riteri. 2.1 Signling Protools nd Dt Enodings Modules in n synhronous iruit ommunite dt with some signling protool onsisting of request nd knowledgment signls. There re two ommon signling protools for ommuniting dt etween sender nd reeiver: the four-phse nd the two-phse protool. In ddition to the signling protool, there re dierent wys to enode dt. The most ommon enodings re single-ril nd dul-ril enoding. We explin the two signling protools rst nd then disuss the dt enodings. If the sender nd reeiver ommunite through two-phse signling protool, then eh ommunition yle hs two distint phses. The rst phse onsists of request initited y the sender. The seond phse onsists of n knowledgment y the reeiver. The request nd knowledgment signls re often implemented y voltge trnsitions on seprte wires. No distintion is mde etween the diretions of voltge trnsitions. Both rising nd flling trnsitions denote signling event. The four-phse signling protool onsists of four phses: request followed y n- knowledgment, followed y seond request, nd nlly seond knowledgment. If the request nd knowledgment re implemented y voltge trnsitions, then t the end of every four phses, the signling wires return to the sme voltge levels s t the strt of the four phses. Beuse the initil voltge is usully zero, this type of signling is lso lled return-to-zero signling. Other nmes for two-phse nd four-phse signling re two-yle nd four-yle signling, respetively, ortrnsition nd level signling, respetively. 5

6 Both signling protools n e used with single nd dul-ril dt enodings. In singleril dt enoding eh it is enoded with one wire, wheres in dul-ril enoding, ehit is enoded with two wires. In single-ril enoding, the vlue of the it is represented y the voltge on the dt wire. When ommuniting n dt its with single-ril enoding, during periods where the dt wires re gurnteed to remin stle, wesy tht the dt re vlid. During periods where the dt wires re possily hnging, we sy the dt re invlid. Atwo-phse or four-phse signling protool is used to tell the reeiver when dt re vlid or invlid. The sender informs the reeiver out the vlidity of the dt through the request signl, nd the reeiver, in turn, informs the sender of the reeipt of the dt through the knowledgment signl. Therefore, to ommunite n its of dt, totl numer of (n+2) wires re neessry etween the sender nd the reeiver. The onnetion pttern for single-ril enoding nd two or four-phse signling is depited in Figure 1(). S E N D E R Request n DATA Aknowledge R E C E I V E R S E N D E R 2n DATA Aknowledge R E C E I V E R () Bundled Dt Convention () Dul-Ril Dt Enoding Figure 1: Two dierent dt ommunition shemes Figure 2() shows the sequene of events in two-phse signling protool. The events inlude the times when the dt eome vlid nd invlid. The trnsprent rs indite the period when dt re vlid, during the other periods, dt re invlid. Notie tht request signl ours only fter dt eome vlid. This is n importnt timing restrition ssoited with these ommunition protools, nmely, the request signl tht indites tht dt re vlid should lwys rrive t the reeiver fter ll dt wires hve ttined their proper vlue. The restrition is referred to s the undling onstrint. For this reson the ommunition protool is often lled the undled dt protool. Figure 2() shows sequene of events in four-phse protool nd single-ril dt enoding. Other sequenes re lso pplile for the four-phse protool. The dul-ril enoding sheme uses two wires for every dt it. There re severl dulril enoding shemes. All omine the dt enoding nd signling protool. There is no expliit request signl, nd the dul-ril enoding shemes ll require (2n + 1) wires s 6

7 Request Request Dt Dt Aknowledge Ahnowledge () One Cyle () One Cyle Figure 2: Dt trnsfer in two-phse signling (), nd four-phse signling () illustrted in Figure 1(). In the se of four-phse signling, there re severl enodings tht n e used to trnsmit dt it. The most ommon enoding hs the following mening for the four sttes in whih eh pir of wires n e in: 00 = reset, 10 = vlid 0, 01 = vlid 1, nd 11 is n unused stte. Every pir of wires hs to go through the reset stte efore eoming vlid gin. In the rst phse of the four-phse signling protool, every pir of wires leves the reset stte for vlid 0 or 1 stte. The reeiver detets the rrivl of new set of vlid dt when ll pirs of wires hve left the reset stte. This detetion reples n expliit request signl. The seond phse onsists of n knowledgment to inform the sender tht dt hs een onsumed. The third phse onsists of the reset of ll pirs of wires to the reset stte, nd the fourth phse is the reset of the knowledgment. In two-phse signling protool, dierent dul-ril enoding is used. An exmple of n enoding is s follows. Eh pir of wires hs one wire ssoited with 0 nd one wire ssoited with 1. A trnsition on the wire ssoited with 0 represents the ommunition of 0, wheres trnsition on the other wire represents ommunition of 1. Thus, trnsition on one wire of eh pir signls the rrivl of new it vlue. A trnsition on oth wires is not llowed. In the rst phse of the two-phse signling protool, every pir of wires ommunites 0 or 1. The seond phse is n knowledgment sent y the reeiver. Of ll dt enodings nd signling protools, the most populr re the single-ril enoding nd four-phse signling protool. The min dvntges of these protools re the smll numer of onnetion wires nd the simpliity of the enoding, whih llows using onventionl tehniques for implementing dt opertions. The disdvntges of these protools re the undling onstrints tht must e stised nd the extr energy nd time wsted in the dditionl two phses ompred with two-phse signling. Dul-ril dt enodings hve een used to ommunite dt in synhronous iruits free of ny timing onstrints. Dul-ril enodings, however, re expensive in prtie, euse of the mny interonne- 7

8 tion wires, the extr iruitry to detet ompletion of trnsfer, nd the diulty in dt proessing. 2.2 Dely Models An importnt hrteristi distinguishing dierent synhronous iruit styles is the dely model on whih they re sed. For eh iruit primitive, gte or wire, dely model stipultes the sort of dely it imposes nd the rnge of the delys. Dely models re needed to nlyze ll possile ehvior of iruit for vrious orretness onditions, like the sene of hzrds. A iruit is omposed of gtes nd interonnetion wires, ll of whih impose delys on the signls propgting through them. The dely models re tegorized into two lsses: pure dely models nd inertil dely models. In pure dely model, the dely ssoited with iruit omponent produes only time shift in the voltge trnsitions. In relity, iruit omponent my shift the signls nd lso lter out pulses of smll width. A dely model whih ptures this ft is lled n inertil dely model. Both lsses of dely models n hve severl rnges for the dely shifts. We distinguish the zero-dely, xed-dely, oundeddely, ndunounded-dely models. In the zero-dely model, the vlues of the delys re zero. In the xed-dely model, the vlues of the delys re onstnt, wheres in the oundeddely model the vlues of the delys vry within ounded rnge. The unounded-dely model does not impose ny restrition on the vlue of the delys exept tht they nnot e innite. Sometimes two dierent dely models re ssumed for the wires nd the gtes in n synhronous iruit. For exmple, the opertion of lss of synhronous iruits is sed on the zero-dely model for wires nd the unounded-dely model for gtes. Forml denitions of the vrious dely models re given in [12]. A onept losely relted to the dely model of iruit is its mode of opertion. The mode of opertion hrterizes the intertion etween iruit nd its environment. Clssil synhronous iruits operte in the fundmentl mode [13,14], whih ssumes tht the environment hnges only one input signl nd wits until the iruit rehes stle stte. Then the environment is llowed to pply the next hnge to one of the input signls. Mny modern synhronous iruits operte in the input-output mode. In ontrst to the fundmentl mode, the input-output mode llows for input hnges immeditely fter reeiving n pproprite response to previous input hnge, even if the entire iruit hs not yet stilized. The fundmentl mode ws introdued in the sixties to simplify the nlysis nd design of gte iruits with Boolen lger. The input-output mode evolved in the eighties 8

9 from event-sed formlisms to desrie modulr design methods tht strted from the internl opertion of iruit. 2.3 Formlisms Just s in ny other design disipline, designers of synhronous iruits use vrious formlisms to mster the omplexities in the design nd nlysis of their rtifts. The formlisms used in synhronous iruit design n e tegorized into two lsses: formlisms sed on Boolen lger nd formlisms sed on sequenes of events. Most design methodologies in synhronous iruits use some mixture of oth formlisms. The design of mny synhronous iruits is sed on Boolen lger or its derivtive swithing theory. Suh iruits often use the fundmentl mode of opertion, the oundeddely model, nd hve, s primitive elements, gtes tht orrespond to the si logi funtions, like nd, or, nd inversion. These formlisms re onvenient for implementing logi funtions, nlyzing iruits for the presene of hzrds, nd synthesizing fundmentl-mode iruits [12, 14]. Event-sed formlisms del with sequenes of events rther thn inry logi vriles. Ciruits designed with n event-sed formlism operte in the input-output mode, under n unounded-dely model, nd hve, s primitive elements, the join, the toggle, nd the merge, for exmple. Event-sed formlisms re prtiulrly onvenient for designing synhronous iruits when high degree of onurreny is involved. Severl tools hve een generted for the utomti verition of synhronous iruits with event-sed formlisms [15, 16]. Exmples of event-sed formlisms re Tre Theory [17{19], DI Alger [20], Petri nets, nd Signl Trnsition Grphs [21, 22]. 3 Design Tehniques This setion introdues the most populr types of synhronous iruits nd riey desries some of their design tehniques. 3.1 Types of Asynhronous Ciruits There re speil types of synhronous iruits for whih forml nd informl speitions hve een given. Here re rief informl desriptions of some of them in historil ontext. 9

10 There re two types of logi iruits: omintionl nd sequentil. The output of omintionl iruit depends only on the urrent inputs, wheres the output of sequentil iruit depends lso on the previous sequenes of the inputs. With this denition of sequentil iruit, lmost ll synhronous iruit styles fll into this tegory. However, the term synhronous sequentil iruits or mhines generlly refers to those synhronous iruits sed on nite stte mhines similr to those in synhronous sequentil iruits [14,23]. Muller ws the rst to give rigorous formliztion of speil type of iruits for whih he oined the nme speed-independent iruits. An ount of this formliztion is given in [24, 25]. Informlly, speed-independent iruit is network of gtes tht stises its speition irrespetive ofny gte delys. From design disipline tht ws developed s prt of the Mromodules projet [6] t Wshington University in St. Louis, the onept of nother typeofsynhronous iruits evolved, whih ws given the nme dely-insensitive iruit, tht is, network of modules tht stises its speition irrespetive ofny element nd wire delys. It ws relized tht proper formliztion of this onept ws needed to speify nd design suh iruits in well-dened mnner. Suh formliztion ws given y Udding [26]. Another nme frequently used in designing synhronous iruits is self-timed systems. This nme ws introdued y Seitz [27]. A self-timed system is desried reursively s either self-timed element or legl onnetion of self-timed systems. The ide is tht self-timed elements n e implemented with their own timing disipline, nd some my even hve synhronous implementtions. In omposing self-timed systems from self-timed elements, however, no referene to the timing of events is mde only the sequene of events is relevnt. In other words, the elements \keep time to themselves." Some hve found the unounded gte-nd-wire dely ssumption, on whih the onept of dely-insensitive iruit is sed, to e too restritive in prtie. For exmple, the unounded gte-nd-wire dely ssumption implies tht signl sent tomultiple reipients y fork n inur dierent unounded dely for eh of the reipients. They proposed to relx this dely ssumption slightly y usingisohroni forks [28]. An isohroni fork is fork whose dierene in the delys of its rnhes is negligile ompred with the delys in the element to whih it is onneted. A dely-insensitive iruit tht uses isohroni forks is lled qusi-dely-insensitive iruit [17, 28]. Although the use of isohroni forks gives more design freedom in exhnge for less dely insensitivity, re hs to e tken with its implementtion [29]. 10

11 3.2 Asynhronous Sequentil Mhines The design of synhronous sequentil nite stte mhines ws initited with the pioneering work of Humn [23]. He proposed struture similr to tht of synhronous sequentil iruits onsisting of omintionl logi iruit, inputs, outputs, nd stte vriles [14]. Humn iruits, however, store the stte vriles in feedk loops ontining dely elements, insted of in lthes or ip-ops, s synhronous sequentil iruits do. The design proedure egins with reting ow tle nd reduing it through some stte minimiztion tehnique. After stte ssignment, the proedure otins the Boolen expressions nd implements them in omintionl logi with the id of logi minimiztion progrm. To gurntee hzrd-free opertion, Humn iruits dopt the restritive single-inputhnge fundmentl mode, tht is, the environment hnges only one input nd wits until the iruit eomes stle efore hnging nother input. This requirement n sustntilly degrde the iruit performne. Hollr relized this ft nd introdued new struture in whih the fundmentl mode ssumption is relxed [30]. In his implementtion, the stte vriles re stored in nnd lthes, so tht inputs re llowed to hnge erlier thn the fundmentl modewould llow. Although Hollr's method improves the performne, it suers from the dnger of produing hzrds. Besides, neither tehnique seem to e dequte for designing onurrent systems. Models nd lgorithms for the nlysis of synhronous sequentil iruits hve een developed y Brzozowski nd Seger [12]. The quest for more onurreny, higher performne, nd hzrd-free opertion, resulted in the formultion of new genertion of synhronous sequentil iruits known s urstmode mhines [31,32]. A urst-mode iruit does not ret until the environment performs numer of input hnges lled n input urst. Theenvironment, in turn, is not llowed to introdue the next input urst until the iruit produes numer of outputs lled n output urst. A stte grph is used to speify the trnsitions used y the input nd output ursts. Two synthesis methods hve een proposed nd utomted for implementing urstmode iruits. The rst method employs lolly generted loktovoid some hzrds [33]. The seond method uses three-dimensionl ow tles nd is sed on Humn iruits [34]. One limittion of urst mode iruits is tht they restrit onurreny within urst. 3.3 Speed-Independent Ciruits nd STG synthesis Speed-independent iruits re usully designed y form of Petri nets [35]. A populr version of Petri nets, signl trnsition grphs (STG), ws introdued y Chu. He lso developed synthesis tehnique for trnsforming STGs into speed-independent iruits [21]. Chu's work 11

12 ws extended y Meng, who produed n STG-sed tool for synthesizing speed-independent iruits from high-level speitions [36]. In this tehnique, iruit is omposed of omputtionl loks nd interonnetion loks. Computtionl loks rnge from simple shifter module to more omplited ones, suh s ALUs, RAMs, nd ROMs. Interonnetion loks synhronize the opertion of omputtionl loks y produing pproprite ontrol signls. Computtionl loks generte ompletion signls fter their output dt eome vlid. The interonnetion loks use the ompletion signls to generte four-phse hndshke protools. 3.4 Dely-Insensitive Ciruits nd Compiltion Severl reserhers hve proposed tehniques for designing dely-insensitive iruits. Eergen [37] hs developed synthesis method sed on the formlism of Tre Theory. The method onsists of speifying omponenty progrm nd then trnsforming this progrm into dely-insensitive network of si elements. The progrm nottion llows speifying prllel ehvior. Eergen's method hs een pplied to the design of smll omponents like stks, vrious ounters, nd riters [18]. Mrtin proposes method [28] tht strts with speition of n synhronous iruit in high-level progrmming lnguge similr to Hore's Communiting Sequentil Proesses (CSP) [38]. An synhronous iruit is speied s group of proesses ommuniting over hnnels. After vrious trnsformtions, the progrm is mpped into network of gtes. This method led to the design of n synhronous miroproessor [39] in Mrtin's method yields qusi-dely-insensitive iruits. Vn Berkel [17] hs designed ompiler sed on high-level lnguge lled Tngrm. A Tngrm progrm lso speies set of proesses ommuniting over hnnels. A Tngrm progrm is rst trnslted into hndshke iruit. Then these hndshke iruits re mpped into vrious trget rhitetures, depending on the dt-enoding tehniques or stndrd-ell lirries used. The trnsltion is syntx-direted, whih mens tht every opertion ourring in Tngrm progrm orresponds to primitive in the trnslted hndshke iruit. This property is exploited y vrious tools tht quikly estimte the re, performne, nd energy dissiption of the nl design y nlyzing the Tngrm progrm. Vn Berkel's method lso yields qusi-dely-insensitive iruits. Other trnsltion methods from CSP-like lnguge to (qusi-) dely-insensitive iruit n e found in [40,41]. 12

13 4 A Typil Asynhronous Design In this setion we present typil synhronous design, miropipeline [42]. The iruit uses single-ril enoding with the two-phse signling protool to ommunite dt etween stges of the pipeline. The ontrol iruit for the pipeline is dely-insensitive iruit. First we present the primitives for the ontrol iruit, then we present the lthes tht store the dt, nd nlly we present the omplete design. 4.1 The Control Primitives Figure 3 shows few simple primitives used in event-sed design styles. The shemti symol for eh primitive is depited opposite its nme. WIRE IWIRE JOIN MERGE M TOGGLE Figure 3: Some dely-insensitive primitives The simplest primitive is the wire, two-terminl element tht produes n output event on its output terminl fter every input event on its input terminl. Input nd output events in wire must lternte. An input event must e followed y n output event efore nother event ours. A wire is physilly relizle with wire, nd events re implemented y voltge trnsitions. An initilized wire, oriwire, isvery similr to wire, exept tht it strts y produing n output event insted of epting n input event fter this, its ehvior extly resemlesthtofwire. 13

14 The primitive for synhroniztion is the join, lso lled the rendezvous [6]. A join hs two inputs nd nd one output. Thejoin performs the nd opertion of two events nd. It produes n output event only fter oth of its inputs, nd, reeived n event. The inputs n hnge gin fter n output is produed. A join n e implemented y Muller C-element, explined in the next setion. The merge omponent performs the or opertion of two events. If merge omponent reeives n event on either of its inputs, or, it produes n output event. After n input event, there must e n output event suessive input events re not llowed. A merge n e implemented y xor gte. The toggle hs single input nd two outputs nd. After n event on input, n event ours on output. The next event on results in trnsition on output. An input event must e followed y noutputevent efore nother input event n our. Thus, output events lternte or toggle fter eh input event. The dot in the toggle shemti indites the output whih produes the rst event. 4.2 The Muller C-Element The Muller C-element is nmed for its inventor D. E. Muller [24]. Trditionlly, its logil ehvior is desried s follows. If oth inputs re 0 (1), then the output eomes 0 (1) otherwise the output remins the sme. For the proper opertion of the C-element, it is lso ssumed tht, one oth inputs eome 0 (1), they will not hnge gin until the output hnges. A stte digrm is given in Figure 4. The ehvior of the output of the C-element Figure 4: Stte digrm of the C-element is expressed in terms of the inputs nd nd the previous stte of the output ^ y the following Boolen funtion =[^ ( + )] + ( ) (1) 14

15 The C-element n e used for implementing the join, whih hsslightly more restritive environment ehvior in the sense tht n input is not llowed to hnge twie in suession. A stte grph for the join is produed y repling the idiretionl rs y unidiretionl rs. There re mny implementtions of the C-element. We hve given two populr CMOS implementtions in Figure 5. Implementtion () is onventionl pull-up pull-down implementtion suggested y Sutherlnd [42]. Implementtion () is suggested yvn Berkel [29]. Eh implementtion hs its own hrteristis. Implementtion () is the est hoie for speed nd energy eieny [43]. V DD V DD P1 P2 P3 P5 P4 P6 P1 p2 P5 P3 P4 P6 N2 N1 N5 N3 N4 N6 N2 N1 N5 N4 N3 N6 () () Figure 5: Two CMOS implementtions of the C-element: () onventionl nd () symmetri 4.3 Storge Primitives Now we disuss two event-ontrolled lthes due to Sutherlnd [42], s depited in Figure 6. Their opertion is mnged through two input ontrol signls: pture nd pss, leled nd p respetively. They lso hve two output ontrol signls: pture done, d, nd pss done, pd. The input dt is leled D, nd the output dt is leled Q. Implementtion () is omposed of three so-lled doule-throw swithes. Implementtion () inludes merge, toggle, nd level-ontrolled lth onsisting of doule-throw swith nd n inverter. A doule-throw swithisshemtilly represented y ninverter nd swithing til. The til toggles etween two positions sed on the logi vlue of ontrolling signl. A doule-throw swith, in ft, is two-input multiplexer tht produes n inverted version of its seleted input. A CMOS implementtion of the doule-throw swith is shown in Figure 7 [42]. The position of the swith orresponds to the stte where is low. 15

16 p p M D D Q Q d () pd d () pd Figure 6: Two event-driven lth implementtions V DD z y x y x x y z Figure 7: A CMOS implementtion of doule-throw swith An event-ontrolled lth n ssume two sttes: trnsprent nd opque. In the trnsprent stte no dt is lthed, ut the output replites the input, euse pth of two inverting stges exists etween the input nd the output. In the opque stte, this pth is disonneted so tht the input dt n hnge without eting the output the urrent dt t the output, however, is lthed. Implementtions in Figures 6() nd 6() re oth shown in their initil trnsprent sttes. The pture nd pss signls in n event-ontrolled lth lwys lternte. Upon trnsition on, thelth ptures the urrent input dt nd eomes opque. The following trnsition on d is n knowledgment to the dt provider tht the urrent dt hs een ptured nd tht the input dt n e hnged sfely. A susequent trnsition on p returns the lth k to its trnsprent stte to pss the next dt to its output. The p signl is knowledged y trnsition on pd. Notie tht in implementtion () of Figure 6, signls d nd pd re merely delyed nd possily mplied versions of nd p, respetively. A group of event-ontrolled lthes, similr to implementtion () of Figure 6, n e 16

17 onneted, shring pture wire nd pss wire, to form n event-ontrolled register of ritrry dt width. Implementtion () of Figure 6 n e generlized similrly into register y inserting dditionl level-ontrolled lthes etween the merge nd the toggle. A omprison of dierent miropipeline lthes is reported in [44] nd lter in [45]. 4.4 Pipelining Pipelining is powerful tehnique for onstruting high-performne proessors. Miropipelines re elegnt synhronous iruits tht hve gined muh ttention in the synhronous ommunity. Mny VLSI iruits sed on miropipelines hve een suessfully frited. The AMULET miroproessor [9] is one exmple. The simplest form of miropipeline is FIFO. A four-stge FIFO is shown in Figure 8. It hs ontrol iruit omposed solely of interonneted joins nddtpthofevent- ontrolled registers. The ontrol signls re indited y dshed lines. The thik rrows show the diretion of dt ow. Dt is implemented with single-ril enoding, nd the dt pth is s wide s the registers n ommodte. Adjent stges of the FIFO ommunite through two-phse, undled-dt signling protool. This mens tht request rrive t the next stge only when the dt for tht stge eomes vlid. A ule t the input of join is shorthnd for join with n iwire on tht input. It implies tht, initilly, n event hs lredy ourred on the input with the ule, nd the join n produe n output event immeditely upon reeiving n event on the other input. Rin 1 r2 3 Rout pd d p pd d p Din REG REG REG REG Dout d p pd d p pd Ain r1 2 r3 Aout Figure 8: A four-stge miropipeline FIFO struture Initilly, ll ontrol wires of the FIFO re t low voltge, nd the dt in the registers re 17

18 not vlid. The FIFO is tivted y rising trnsition on R in, whih indites tht input dt is vlid. Susequently, the rst-stge join produes rising output trnsition. This signl is request to the rst-stge register to pture the dt nd eome opque. After pturing the dt, the register produes rising trnsition on its d output terminl. This uses trnsition on A in nd trnsition on r1, whih is request to the seond stge of the FIFO. Menwhile, the dt hs proeeded to the seond-stge register nd hs rrived there efore the trnsition on r1 ours. If the environment does not send ny new dt, the rst stge remins idle, nd the dt nd the request signls propgte further to the right. Notie tht eh time the dt is ptured y stge, n knowledgment is sent k to the previous stge whih uses its lth to eome trnsprent gin. When the dt hs propgted to the lst register, it is stored nd request signl R out is forwrded to the onsumer of the FIFO. At thispoint, ll ontrol signls re t high voltge exept for A out. If the dt is not removed out of the FIFO, tht is, A out remins low, the next dt oming from the produer dvne only up to the third-stge register, euse the fourth-stge join nnot produe n output. Finlly, A out lso eomess high when the onsumer knowledges reeipt of the dt. Further dt storge nd removl follows the sme pttern. The opertion of eh join n e interpreted s follows. If the previous stge hs sent request for dt pture nd the present stge is empty, then send signl to pture the dt in the present stge. The FIFO n e modied esily to inlude dt proessing. A four-stge miropipeline, in its generl form, is illustrted in Figure 9. Now the dt pth onsists of lterntely positioned event-driven registers nd omintionl logi iruits. The event-driven registers store the input nd output dt of the omintionl iruits, nd the omintionl iruits perform the neessry dt proessing. To stisfy the dt undling onstrint, dely elements my osionlly e required to slow down the propgtion of the request signls. A dely element must t lest mth the dely through its orresponding omintionl logi iruit, either y some ompletion detetion mehnism or through the insertion of worst-se dely. A miropipeline FIFO is exile in the numer of dt items it uers. There is no restrition on the rte t whih dt enters or exits the miropipeline, exept for the delys imposed y the iruit elements. Tht is why this FIFO nd miropipelines generlly, re termed elsti. Inontrst, in n ordinry synhronous pipeline, the rtes t whih dt enter nd exit the pipeline re the sme, ditted y the externl lok signl. A miropipeline is lso exile in the mount of energy it dissiptes, whih is proportionl to the numer of dt movements. A loked pipeline, however, ontinuously dissiptes energy s if ll 18

19 Rin 1 r2 3 DELAY DELAY Rout pd d p pd d p Din REG d p LOGIC REG pd LOGIC REG d p LOGIC REG pd LOGIC Dout Ain DELAY r1 2 DELAY r3 Aout Figure 9: A generl four-stge miropipeline struture stges of the pipeline pture nd pss dt ll the time. Another ttrtive feture of miropipeline is tht it utomtilly shuts o when there is no tivity. Aloked pipeline, on the other hnd, requires speil lok mngement mehnism to implement this feture. This sensing mehnism, however, onstntly onsumes energy, euse it should never go idle. 5 Conluding Remrks We hve touhed only on few topis relevnt to the re of synhronous iruits nd omitted mny others. Among the topis omitted re the importnt res of verition, testing, nd performne nlysis of synhronous iruits. We hope, however, tht within the sope of these pges we hveprovided enough informtion for further redings. For more informtion on synhronous iruits, plese see [46], [12], or [47]. A omprehensive iliogrphy of synhronous iruits n e found in [48]. Up-to-dte informtion on reserh in synhronous iruit design n e found t [49]. The uthors wish to thnk Bill Cotes for his generous ritiisms of previous drft of this rtile. Referenes [1] T. E. Willims nd M. A. Horowitz, \A zero-overhed self-timed 160ns 54 CMOS divider," IEEE Journl of Solid-Stte Ciruits, vol. 26, pp. 1651{1661, Nov

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